Semiconductor Component Patents (Class 428/620)
  • Publication number: 20040115464
    Abstract: A thermoelectric transducing material according to this invention includes a layered cobaltite based substance represented by the chemical formula AxCoO2, wherein A consists of an element or element group selected from alkali metal elements and alkali earth group elements and is compositionally modulated in a thickness-wise direction of layers in a structure of the layered cobaltite based substance.
    Type: Application
    Filed: December 9, 2003
    Publication date: June 17, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hideaki Adachi, Akihiro Odagawa
  • Patent number: 6746777
    Abstract: A substrate including a base substrate, an interfacial bonding layer disposed on the base substrate, and a thin film adaptive crystalline layer disposed on the interfacial bonding layer. The interfacial bonding layer is solid at room temperature, and is in liquid-like form when heated to a temperature above room temperature. The interfacial bonding layer may be heated during epitaxial growth of a target material system grown on the thin film layer to provide the thin film layer with lattice flexibility to adapt to the different lattice constant of the target material system.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: June 8, 2004
    Assignee: Applied Optoelectronics, Inc.
    Inventor: Wen-Yen Hwang
  • Patent number: 6737173
    Abstract: The surface to be plated of a composite made of a metallic and a non-metallic material is degreased and otherwise cleaned and immersed in a palladium activator fluid conditioned with a hydrogencarbonate to a pH of 2˜5. After this pretreating process, the composite is plated with a metal and becomes most suitable for use as a material for heat sink on hybrid ICs since it can be efficiently soldered and has better corrosion resistance.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: May 18, 2004
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Ken Iyoda, Susumu Shimada
  • Patent number: 6733901
    Abstract: The present invention provides a process for producing an epoxy resin composition for semiconductor encapsulation which, when used in encapsulation of a semiconductor chip, can minimize voids appearing in the semiconductor device obtained.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: May 11, 2004
    Assignee: Sumitomo Bakelite Company Limited
    Inventors: Noriyuki Takasaki, Kenji Takayama, Kazuo Noda
  • Patent number: 6733902
    Abstract: A liquid epoxy resin composition includes (A) a liquid epoxy resin, (B) a curing agent, (C) a curing accelerator, (D) an inorganic filler, and (E) a silicone-modified resin resulting from addition reaction of an alkenyl-containing epoxy or phenolic resin with an organopolysiloxane, the liquid epoxy resin composition curing into a product having a Tg of 30-120° C. and a specific dynamic viscoelasticity behavior. The composition is adherent to silicon chips, the cured product is highly resistant to heat and thermal shocks, and the composition is useful as sealant for flip chip type semiconductor devices.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: May 11, 2004
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Kazuaki Sumita, Tatsuya Kanamaru, Toshio Shiobara
  • Patent number: 6723452
    Abstract: Epoxy resin compositions comprising (A) an epoxy resin having an epoxy equivalent of at least 185 and possessing a structure in which two benzene rings can be directly conjugated, carbon atoms having an sp2 type atomic orbital accounting for at least 50% of all the carbon atoms, (B) a &bgr;-naphthol type phenolic resin curing agent, (C) a curing accelerator, and (D) an inorganic filler cure into products having satisfactory solder crack resistance on use of lead-free solder and improved flame retardance despite the absence of halogenated epoxy resins and antimony compounds and are thus suited for semiconductor encapsulation.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: April 20, 2004
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Yasuo Kimura, Kazutoshi Tomiyoshi, Tarou Shimoda, Eiichi Asano, Takayuki Aoki, Toshio Shiobara
  • Patent number: 6716371
    Abstract: This invention relates to an organic semiconductor device comprising a substrate bearing an organic layer sandwiched between electrode structures wherein the organic layer comprises a polymer of general Formula (I): wherein X is selected from H, CN, F, Cl, Br, COOCH3. Y is given by the following general Formula (II): wherein A is a phenyl group which may be further substituted in 1 or 2 or 3 positions with groups independently selected from C1-8 alkyl, CN, F, Cl; B and C are both phenyl groups which may be further substituted, independently of each other, in 1 or 2 or 3 or 4 or 5 positions with groups independently selected from C1-8 alkyl, CN, F, Cl; A, B and C may also be, independently of each other, selected from pyrimidine, pyridazine and pyridine; m=5-20,000.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: April 6, 2004
    Assignee: Qinetiq Limited
    Inventors: Ian C Sage, Emma L Wood, Stephen J Till, William J Feast, Richard J Peace
  • Patent number: 6717218
    Abstract: A contact hole is formed, by etching that uses buffered hydrofluoric acid, in a gate insulating film made of SiO2 and an interlayer insulating layer, formed on the gate insulating film, which is made of SiN. In this contact hole, there is formed an electrode which includes: a first protective metal layer made of a refractory metal; a wiring layer, formed on the first protective metal layer, which is made of a metal whose resistance is lower than that of the refractory metal; and a second protective metal layer, made of a refractory metal, which is formed thicker than the gate insulating film.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: April 6, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Isao Hasegawa, Koji Suzuki
  • Patent number: 6710020
    Abstract: The present invention provides a new composite material comprising a porous matrix made of metal, metal alloy or semiconducting material and hollow fullerene-like nanoparticles of a metal chalcogenide compound or mixture of such compounds. The composite material is characterized by having a porosity between about 10% and about 40%. The amount of the hallow nanoparticles in the composite material is 1-20 wt. %.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: March 23, 2004
    Assignees: Yeda Research and Development Co. Ltd., Holon Academic Institute of Technology
    Inventors: Reshef Tenne, Lev Rapoport, Mark Lvovsky, Yishay Feldman, Volf Leshchinsky
  • Publication number: 20040051332
    Abstract: A semiconductor system is provided that uses semiconductive organic polymers, electronics and semiconductor technology to provide a wide array of semiconductor components and a system of preventing corrosion of a surface of a metal structure in contact with a corrosive environment involving:
    Type: Application
    Filed: March 28, 2003
    Publication date: March 18, 2004
    Applicant: APPLIED SEMICONDUCTOR, INC.
    Inventor: David B. Dowling
  • Patent number: 6706417
    Abstract: This invention relates to fluxing underfill compositions useful for fluxing metal surfaces in preparation for providing an electrical connection and sealing the space between semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”), flip chip assemblies (“FCs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), or semiconductor chips themselves and a circuit board to which the devices or chips, respectively, are electrically interconnected. The inventive fluxing underfill composition begins to cure at about the same temperature that solder used to establish the electrical interconnection melts.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: March 16, 2004
    Assignee: Henkel Loctite Corporation
    Inventors: Mark M. Konarski, Jeremy J. Bober
  • Patent number: 6696173
    Abstract: Described are conductor track structures on a nonconductive support material, especially fine conductor track structures, which are comprised of a base containing a heavy metal and a metallized coating applied to this, and a method for their production. The invention is characterized in that the heavy metal base in the area of the conductor track structures contains heavy metal nuclei, which have been created by the breakup of an organic nonconductive heavy metal complex, and that the support material contains microporous or microrough support particles to which the heavy metal nuclei are bound. An outstanding strength of adhesion of the deposited metal conductor tracks is achieved. The method is especially suitable also for the production of three-dimensional circuit supports.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: February 24, 2004
    Assignee: LPKF Laser & Electronics AG
    Inventors: Gerhard Naundorf, Horst Wissbrock
  • Publication number: 20040023057
    Abstract: A method of forming a patterned thin film comprises the step of forming a frame having an undercut near the bottom thereof on an electrode film, and the plating step of forming the patterned thin film by plating through the use of the frame. The patterned thin film includes a plurality of linear portions disposed side by side. Each of the linear portions has a portion close to the electrode film. This portion has a width greater than the width of the remaining portion of each of the linear portions.
    Type: Application
    Filed: July 11, 2003
    Publication date: February 5, 2004
    Applicant: TDK CORPORATION
    Inventor: Akifumi Kamijima
  • Patent number: 6686059
    Abstract: A semiconductor device having a reduced overlap capacity between a gate electrode and extensions. Specifically, a stacked structure made up of a polysilicon film, tungsten silicide film, and silicon nitride film is partially formed in first and second regions of a silicon substrate, respectively. Sidewall oxide films are formed on side surfaces of the polysilicon films in the first and second regions, respectively. A width of the sidewall of the first structure is smaller than a width of the sidewall of the second structure such that an overlap amount between a second conductive layer and a second impurity region is smaller than an overlap amount between a first conductive layer and a first impurity region.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: February 3, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Masayoshi Shirahata
  • Patent number: 6680007
    Abstract: A conductive resin composition comprising (A) an epoxy resin, (B) a phenolic resin, (C) a curing accelerator, and (D) a conductive filler is provided wherein component (A) and/or (B) is a copolymer obtained by reacting an epoxy resin or phenolic resin with an organopolysiloxane, the organopolysiloxane component in the cured composition does not form a phase separation structure, and a weight ratio of (D) to (A) plus (B) is in the range: 300/100≦D/(A+B)≦1500/100. It possesses adhesion, heat resistance, moisture resistance, flexibility and impact resistance.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: January 20, 2004
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsuyoshi Honda, Toshio Shiobara
  • Publication number: 20040004982
    Abstract: A structure including a grating and a semiconductor nanocrystal layer on the grating, can be a laser. The semiconductor nanocrystal layer can include a plurality of semiconductor nanocrystals including a Group II-VI compound, the nanocrystals being distributed in a metal oxide matrix. The grating can have a periodicity from 200 nm to 500 nm.
    Type: Application
    Filed: November 15, 2002
    Publication date: January 8, 2004
    Inventors: Hans J. Eisler, Vikram C. Sundar, Michael E. Walsh, Victor I. Klimov, Moungi G. Bawendi, Henry I. Smith
  • Patent number: 6673709
    Abstract: The reactive element is introduced to the surface of the metal substrate in the form of an oxide powder and the aluminide-type coating is then formed.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: January 6, 2004
    Assignee: SNECMA Moteurs
    Inventors: Yann Jaslier, Alain Martinez, Marie-Christine Ntsama Etoundi, Guillaume Oberlaender
  • Patent number: 6666994
    Abstract: The present invention provides a conductive adhesive and a packaging structure that can keep moisture-proof reliability even when a multipurpose base metal electrode is used. A conductive adhesive according to the present invention includes first particles having a standard electrode potential that is equal to or higher than a standard electrode potential of silver, and second particles having a standard electrode potential lower than a standard electrode potential of silver. A metal compound coating having a potential higher than that of metal particles as the first particles can be formed on a surface of an electrode having a potential lower than that of the metal particles.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: December 23, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Takezawa, Takashi Kitae, Yukihiro Ishimaru, Tsutomu Mitani, Tousaku Nishiyama
  • Patent number: 6667194
    Abstract: A latent fluxing agent comprising a material which liberates phenol or a carboxylic acid containing compound when heated above 140° C. The latent fluxing agent may be incorporated into a thermoset resin, which includes an epoxy resin. The uncured epoxy resin, which includes the epoxy resin, the latent fluxing agent and an epoxy curing agent are useful as an underfill composition in a method for applying a chip die, having one or more solder balls, to a substrate. The method is used to produce an integrated circuit chip that includes a chip die having electrical contacts arranged in a predetermined pattern and capable of providing electrical engagement with a carrier substrate.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: December 23, 2003
    Assignee: Henkel Loctite Corporation
    Inventors: Lawrence N. Crane, Mark M. Konarski, J. Paul Krug, Andrew D. Messana, John G. Woods
  • Publication number: 20030224554
    Abstract: A package is configured as a composite component with a substrate, at least one semiconductor component, and an enclosure, which are joined to one another. The heat-dissipating substrate is a single-layer or multilayer substrate with a thermal conductivity, transversely with respect to a joining surface to which the semiconductor component is joined, of greater than 170 W/m. The substrate may be a layered structure and/or a structure of graduated material composition, and it has an asymmetrical thermal expansion characteristic. By suitable selection the layers or the material graduation, it is possible to reduce and limit the shear distortion of the composite component formed of the substrate, the semiconductor component, and the enclosure.
    Type: Application
    Filed: March 24, 2003
    Publication date: December 4, 2003
    Inventors: Arndt Ludtke, Heiko Wildner
  • Patent number: 6657297
    Abstract: A flexible plastic thermally conductive multilayer semiconductor mounting pad having a highly thermally conductive bulk layer with thermally conductive surface skin layers bonded integrally to opposed major surfaces thereof. The bulk layer and the surface skin layers are each filled with a finely divided thermally conductive particulate, with the skin layers being harder than the bulk layer and being blended with an amount of filler which is less than that present in the bulk layer.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: December 2, 2003
    Assignee: The Bergquist Company
    Inventors: Radesh Jewram, Kasyap Venkata Seethamraju, Kevin L. Hanson
  • Publication number: 20030219619
    Abstract: A thermosetting resin composition which contains:
    Type: Application
    Filed: March 21, 2003
    Publication date: November 27, 2003
    Applicant: NITTO DENKO CORPORATION
    Inventors: Hiroshi Noro, Mitsuaki Fusumada
  • Patent number: 6649278
    Abstract: A process for forming a thin layer exhibiting a substantially uniform property on an active surface of a semiconductor substrate. The process includes varying the temperature within a reaction chamber while a layer of a material is formed upon the semiconductor substrate. Varying the temperature within the reaction chamber facilitates temperature uniformity across the semiconductor wafer. As a result, a layer forming reaction occurs at a substantially consistent rate over the entire active surface of the semiconductor substrate. The process may also include oscillating the temperature within the reaction chamber while a layer of a material is being formed upon a semiconductor substrate.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: November 18, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Garry Anthony Mercaldi, Don Carl Powell
  • Patent number: 6645643
    Abstract: A polymeric composition for making semiconductor device packaging includes at least one epoxy resin, at least one curing agent in an amount between 30 and 110 parts by weight per 100 parts by weight of the epoxy resin, at least one silica-based reinforcing filler in an amount between 300 and 2300 parts by weight per 100 parts of the epoxy resin, and at least one control agent for a rheology of the polymeric composition. The at least one control agent may be substantially free from polar groups and present in an amount between 0.1 and 50 parts by weight per 100 parts by weight of the epoxy resin. The invention also relates to a plastic packaging material for microelectronic applications which may be obtained from the above polymeric composition, and to a semiconductor electronic device including such packaging material.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: November 11, 2003
    Assignees: STMicroelectronics S.r.l., Toshiba Chemical Kawaguchi Works
    Inventors: Roberto Zafarana, Antonino Scandurra, Salvatore Pignataro, Yuichi Tenya, Akira Yoshizumi
  • Patent number: 6641928
    Abstract: An adhesive for semiconductor chips contains a first resin component which is polymerizable, a first hardener for inducing a self-polymerization reaction of the first resin component and a second hardener which is addition-polymerized with the first resin component. When the adhesive is applied on a wiring board and a semiconductor chip is applied thereon and heat is applied, the second hardener is addition-polymerized with the backbone of the three-dimensional network formed by the self-polymerization reaction of the first resin component. The first temperature at which the addition polymerization zone becomes a rubbery structure is lower than the second temperature at which the backbone becomes a rubbery structure, so that the elastic modulus loss sharply increases at the first temperature to reduce the stress between the semiconductor chip and the wiring board.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: November 4, 2003
    Assignee: Sony Chemicals Corp.
    Inventors: Motohide Takeichi, Misao Konishi, Junji Shinozaki, Yasushi Akutsu
  • Patent number: 6635323
    Abstract: The present invention provides a raw material 1 used for production of GaAs crystals by utilizing solidification of melt, wherein As 12 is accommodated in the inside of Ga 10, 11. Because As 12 is covered with Ga 10, 11, As 12 is not brought into contact with the air and can thus be conveyed without oxidizing As 12. The raw material 1 can be heated and melted as such to produce GaAs crystals by the Czochralski method.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: October 21, 2003
    Inventors: Tadashi Kihara, Takeharu Yamamura, Kenichi Tayama
  • Patent number: 6630745
    Abstract: A semiconductor encapsulating epoxy resin composition is provided comprising (A) an epoxy resin, (B) a phenolic resin curing agent, (C) a molybdenum compound, (D-i) an organopolysiloxane, (D-ii) an organopolysiloxane cured product, or (D-iii) a block copolymer obtained by reacting an epoxy resin or alkenyl group-bearing epoxy resin with an organohydrogenpolysiloxane, and (E) an inorganic filler. The composition has improved moldability and solder crack resistance while exhibiting high flame retardance despite the absence of halogenated epoxy resins and antimony oxide.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: October 7, 2003
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoichi Osada, Eiichi Asano, Shigeki Ino, Takayuki Aoki, Kazutoshi Tomiyoshi, Toshio Shiobara
  • Publication number: 20030186072
    Abstract: An electronic equipment is capable of improving falling down shock resistance or impact resistance in an electronic equipment and of improving reliability of a solder joint in a semiconductor device die-bonded Si chip or the like to which thermal shock causing large deformation may act, bump mounting of BGA, CSP, WPP, flip-chip and so forth, a power module acting large stress and so forth. The electronic equipment has a circuit board and an electronic parts to be electrically connected to an electrode of the circuit board. The electrode of the circuit board and an electrode of the electronic part are connected by soldering using a lead free solder consisted of Cu: 0-2.0 mass %, In: 0.1-10 mass %, and Sn: remaining amount.
    Type: Application
    Filed: March 25, 2003
    Publication date: October 2, 2003
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Masato Nakamura, Yuji Fujita, Toshiharu Ishida, Masahide Okamoto, Koji Serizawa, Toshihiro Hachiya, Hideki Mukuno
  • Patent number: 6627328
    Abstract: An epoxy resin composition comprising (A) an epoxy resin, (B) a curing accelerator, and (C) an inorganic filler is light transmissive when it satisfies formulae (1) and (2): [{2(nA2+nC2)−(nA+nC)2}/2]½<3.0×10−3  (1) [{2(fA2+fC2)−(fA+fC)2}/2]½<1.0×10−5  (2) wherein nA is the refractive index at T1° C. of the cured unfilled composition, nC is the refractive index at T1° C. of the inorganic filler, fA is a temperature coefficient of the refractive index of the cured unfilled composition, and fC is a temperature coefficient of the refractive index of the inorganic filler. The cured composition has improved heat resistance, humidity resistance and low stress as well as high transparency over a wide temperature range. The composition is suited for the sealing of optical semiconductor devices.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: September 30, 2003
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tatsuya Kanamaru, Tsuyoshi Honda, Eiichi Asano, Toshio Shiobara
  • Patent number: 6623845
    Abstract: A multilayer LC composite component includes a glass-ceramic composition and internal electrodes containing silver or copper as a main component. The multilayer LC composite component is outstanding in mounting reliability particularly to a resin substrate, easy to manufacture, and has excellent electric characteristics at high frequency. The glass-ceramic composition includes 45 to 35 wt. % of forsterite powder and 55 to 65 wt. % of glass composite powder, and compositions of the glass composite powder include 40 to 50 wt. % of SiO2, 30 to 40 wt. % of BaO, 3 to 8 wt. % of Al2O3, 8 to 12 wt. % of La2O3, and 3 to 6 wt. % of B2O3. It is high in flexural strength, moderately high in coefficient of thermal expansion, easy to use in manufacturing a greensheet, and densely sintered at a temperature of less than 950 degrees C.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: September 23, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidenori Katsumura, Ryuichi Saito, Masahiro Hiraka
  • Patent number: 6617055
    Abstract: At least a portion of a free layer structure in a spin valve sensor is composed of nickel iron molybdenum (NiFeMo) so that the free layer structure does not have to be reduced in thickness in order to have a reduced magnetic moment for responding to lower signal fields from smaller bits on a rotating magnetic disk.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventor: Hardayal Singh Gill
  • Patent number: 6617010
    Abstract: A semiconductor thin film which is deposited by using a chemical vapor deposition method at an underlying layer temperature of 400° C. or less, and contains, as main component elements, a Group IV atom and hydrogen atom. A temperature dependency of an amount of release of hydrogen atoms within the film when the film is heated from room temperature exhibits a profile having a peak of the hydrogen releasing amount at 370° C. or higher and 410° C. or less, and a half-value width of the peak is 30° C. or less.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: September 9, 2003
    Assignee: Kaneka Corporation
    Inventors: Masashi Yoshimi, Takafumi Fujihara
  • Patent number: 6617046
    Abstract: A thermosetting resin composition usable for sealing a gap formed between a printed circuit board and a semiconductor element in a semiconductor package having a face-down structure; a semiconductor device comprising a printed circuit board, a semiconductor element, and the thermosetting resin composition mentioned above, wherein a gap formed between the printed circuit board and the semiconductor element is sealed by the thermosetting resin composition; and a process for manufacturing the semiconductor device.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: September 9, 2003
    Assignee: Nitto Denko Corporation
    Inventors: Hiroshi Noro, Mitsuaki Fusumada
  • Patent number: 6613449
    Abstract: A solventless non-filler underfill material for COF mounting comprising an organic material, which is used to fill the gap between an FPC having a polyimide film substrate and a copper circuit layer having a thickness of 9 &mgr;m or smaller and an IC chip mounted on the FPC, exhibits such adhesion as to destroy a silicon wafer in a polyimide film/silicon wafer adhesion test, and provides a cured film having a tensile modulus of 150 kg/mm2 or less.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: September 2, 2003
    Assignee: UBE Industries, Ltd.
    Inventors: Hiroaki Yamaguchi, Masafumi Kohda
  • Patent number: 6607840
    Abstract: Redundantly constrained laminar structures as weak-link mechanisms and a novel method for manufacturing the redundantly constrained laminar structures as weak-link mechanisms are provided. The method for producing the redundantly constrained laminar structures as weak-link mechanisms is carried out by lithographic techniques. A designed pattern is repeatedly chemically etched with a mask to produce a plurality of individual identical units. The units are stacked together to form the laminar structure and are secured together with fasteners. A high quality adhesive can be applied to the sides of the laminar structure to provide the mechanism equivalent to a single piece mechanism. The redundantly constrained laminar structures as weak-link mechanisms of the invention include a stack of a plurality of thin material structures.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: August 19, 2003
    Assignee: The University of Chicago
    Inventors: Deming Shu, Thomas S. Toellner, E. Ercan Alp
  • Publication number: 20030129438
    Abstract: Curable compositions that comprise two separately curable chemistry sets or compositions with curing temperatures sufficiently separated so that one chemistry composition can be fully cured during a B-staging process, and the second can be left uncured until a final cure is desired, such as at the final attach of a semiconductor chip to a substrate.
    Type: Application
    Filed: December 14, 2001
    Publication date: July 10, 2003
    Inventors: Kevin Harris Becker, Harry Richard Kuder
  • Publication number: 20030124378
    Abstract: This invention relates to fluxing underfill compositions useful for fluxing metal surfaces in preparation for providing an electrical connection and sealing the space between semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”), flip chip assemblies (“FCs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), or semiconductor chips themselves and a circuit board to which the devices or chips, respectively, are electrically interconnected. The inventive fluxing underfill composition begins to cure at about the same temperature that solder used to establish the electrical interconnection melts.
    Type: Application
    Filed: November 25, 2002
    Publication date: July 3, 2003
    Applicant: HENKEL LOCTITE CORPORATION
    Inventors: Mark M. Konarski, Jeremy J. Bober
  • Patent number: 6586113
    Abstract: Systems and methods of manufacturing etchable heterojunction interfaces and etched heterojunction structures are described. A bottom layer is deposited on a substrate, a transition etch layer is deposited over the bottom layer, and a top layer is deposited over the transition etch layer. The transition etch layer substantially prevents the bottom layer and the top layer from forming a material characterized by a composition substantially different than the bottom layer and a substantially non-selective etchability with respect to the bottom layer. By tailoring the structure of the heterojunction interface to respond to heterojunction etching processes with greater predictability and control, the transition etch layer enhances the robustness of previously unreliable heterojunction device manufacturing processes. The transition etch layer enables one or more vias to be etched down to the top surface of the bottom layer in a reliable and repeatable manner.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: July 1, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Sandeep R. Bahl, Yu-Min Houng, Virginia M. Robbins, Fred Sugihwo
  • Patent number: 6572980
    Abstract: This invention relates to thermosetting resin compositions useful for mounting onto a circuit board semiconductor devices, such as CSPs, BGAs, LGAs and the like, each of which having a semiconductor chip, such as LSI, on a carrier substrate. The compositions of this invention are reworkable when subjected to appropriate conditions.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: June 3, 2003
    Assignee: Henkel Loctite Corporation
    Inventors: Philip T. Klemarczyk, Andrew D. Messana
  • Patent number: 6562482
    Abstract: A liquid potting composition, a semiconductor device manufactured using such composition and a process for manufacturing a semiconductor device using such composition. The liquid potting composition comprises: (a) a liquid epoxy resin; (b) a hardener comprising a multi-hydroxy aromatic compound containing at least two hydroxy groups and at least one carboxyl group; and (c) an accelerator. Suitable hardening agents include 2,3-dihydroxybenzoic acid; 2,4-dihydroxybenzoic acid; 2,5-dihydroxybenzoic acid; 3,4-dihydroxybenzoic acid; gallic acid; 1,4-dihydroxy-2-naphthoic acid; 3,5-dihydroxy-2-naphthoic acid; phenolphthaline; diphenolic acid and mixtures thereof.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: May 13, 2003
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventor: Yushi Sakamoto
  • Patent number: 6558812
    Abstract: A liquid epoxy resin composition comprising (A) a liquid epoxy resin, (B) a curing agent, (C) a curing accelerator, and (D) an inorganic filler is provided, the curing agent (B) comprising 5 to 75 parts by weight of a mixture of 3,4-dimethyl-6-(2-methyl-1-propenyl)-1,2,3,6-tetrahydrophthalic acid and 1-isopropyl-4-methyl-bicyclo[2.2.2]oct-5-ene-2,3-dicarboxylic acid per 100 parts by weight of the entire curing agent. The composition is adherent to the surface of silicon chips, and especially to polyimide resins and nitride films and has high thermal shock resistance. A semiconductor device sealed with the cured epoxy resin composition remains reliable.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: May 6, 2003
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Kazuaki Sumita, Toshio Shiobara
  • Patent number: 6548189
    Abstract: In the present invention an adhesive composition is provided. The adhesive composition includes epoxidized cashew nutshell liquid, a catalyst, and diglycidyl ether of bisphenol A. The invention may further include at least one additive selected from the group including curing agents, bonding enhancers, hardeners, flexibilizers, tackifiers, and mixtures thereof.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: April 15, 2003
    Assignee: General Electric Company
    Inventors: Somasundaram Gunasekaran, Thomas Bert Gorczyca, Herbert Stanley Cole
  • Patent number: 6548196
    Abstract: Wallpaper for shielding electromagnetic waves, which can effectively shield wideband frequency electromagnetic waves and prevent static electricity, is provided. The wallpaper is prepared by applying and coating onto at least one surface of raw paper a coating composition comprising, mixed in a predetermined ratio based on the total weight of the composition, 1 to 69% by weight of at least one material selected from the group consisting of a conductive polymer material with about 1% to about 100% solids by weight of the conductive polymer material, conductive carbon and graphite, 30 to 98% by weight of matrix polymer with about 1% to about 50% solids by weight of the matrix polymer, 0 to 59% by weight of a solvent and 1 to 40% by weight of additives. Also, in order to form a protection layer for protecting the electromagnetic wave shielding layer and to enhance commodity attraction, a patterned layer is further formed and the resulting structure is dried.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: April 15, 2003
    Assignee: AD-Tech Co., Ltd.
    Inventors: Jae-Mok Ha, Jin-U Park, Jin-Ouk Jang, Hyun-Sik Hahm
  • Publication number: 20030068519
    Abstract: A method for assembly including the steps of:
    Type: Application
    Filed: August 12, 2002
    Publication date: April 10, 2003
    Applicant: HRL LABORATORIES, LLC
    Inventors: Peter D. Brewer, Andrew T. Hunter, Luisa M. Deckard
  • Patent number: 6534193
    Abstract: A liquid epoxy resin composition includes (A) a liquid epoxy resin, (B) an optional curing agent, (C) a curing accelerator, (D) an inorganic filler, and (E) an indene-styrene or indene-chroman-styrene copolymer having a Mn of 200-2,000 in an amount of 0.1-20 parts by weight per 100 parts by weight of components (A) and (B) combined. The indene polymer (E) is previously melt mixed with a part or all of the liquid epoxy resin (A) prior to compounding with the remaining components. A semiconductor device sealed with the cured product of the liquid epoxy resin composition remains reliable.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: March 18, 2003
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Kazuaki Sumita, Toshio Shiobara
  • Patent number: 6534192
    Abstract: A printed wiring board (PWB) and a method of manufacturing the same. In one embodiment, the PWB includes: (1) a substrate having a conductive trace located thereon and (2) a multi-purpose finish including palladium alloy where palladium is alloyed with cobalt or a platinum group metal and is located on at least a portion of the conductive trace, which forms both a non-contact finish and a contact finish for the PWB.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: March 18, 2003
    Assignee: Lucent Technologies Inc.
    Inventors: Joseph A. Abys, Chonglun Fan, Brian T. Smith, Bruce F. Stacy, Chen Xu
  • Patent number: 6531232
    Abstract: The invention relates to a system comprising a first substrate (100) with at least one bonding area (110a, 110b), liable to be assembled with a second substrate (200), the bonding area (110a, 110b) comprising an area made of a material (104) that can be wetted with a meltable material. According to the invention, the bonding area (110a, 110b) comprises at least one cavity (120) to receive meltable material.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: March 11, 2003
    Assignee: Commissariat a l'Energie Atomique
    Inventors: François Baleras, Pierre Renard
  • Patent number: 6528179
    Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: March 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Lisa J. Jimarez, Miguel A. Jimarez
  • Publication number: 20030038036
    Abstract: A method of electroplating metal onto a low conductivity layer combines a potential or current reversal waveform with variation in the amplitude and duration of the applied potential or current pulse. The method includes, over time, varying the duration of the pulse and continuously decreasing the amplitude of both the cathodic and anodic portions of the waveform across the surface of the low conductivity layer as the deposition zone moves from the center of the surface of the low conductivity layer to the outside edge. By virtue of the ability to vary the amplitude and duration of the pulse, the method facilitates the filling of structures in the center of the low conductivity layer without overdepositing on the outside edge, thus ensuring a controlled deposition of material across the surface of the low conductivity layer.
    Type: Application
    Filed: August 27, 2001
    Publication date: February 27, 2003
    Inventor: Dale W. Collins
  • Patent number: 6524721
    Abstract: The present invention provides a conductive adhesive and a packaging structure that can keep moisture-proof reliability even when a multipurpose base metal electrode is used. A conductive adhesive according to the present invention includes first particles having a standard electrode potential that is equal to or higher than a standard electrode potential of silver, and second particles having a standard electrode potential lower than a standard electrode potential of silver. A metal compound coating having a potential higher than that of metal particles as the first particles can be formed on a surface of an electrode having a potential lower than that of the metal particles.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: February 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Takezawa, Takashi Kitae, Yukihiro Ishimaru, Tsutomu Mitani, Tousaku Nishiyama