Abstract: In a conventional diamond semiconductor element, because of high density of crystal defects, it is impossible to reflect the natural physical properties peculiar to a diamond, such as high thermal conductivity, high breakdown field strength, high-frequency characteristics and the like, in the transistor characteristics. By slightly shifting surface orientation of a diamond substrate in a [001] direction, a significant reduction in crystal defects peculiar to a diamond is possible. The equivalent effects are also provided by shifting surface orientation of a single-crystal diamond thin-film or channel slightly from a [001] direction. It is possible to obtain a significantly high transconductance gm as compared with that in a transistor produced using conventional surface orientation.

Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.

Abstract: Epitaxial silicon carbide layers are fabricated by forming features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. The epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes features therein.

Abstract: A patterned structure forms a portion of the mold for a diamond molded structure but is separable from the mold by the same processes that release the diamond part. The mold portion may itself be a component in a MEMS or NEMS structure or device or the precursor to such a structure or device. The mold portion may be made from sapphire or silicon carbide. The mold portion may be coated and polished to obtain an optically smooth surface over the diamond mold inside pit. The coating may be formed from one or more of silicon carbide, PTFE, silicon nitride, silicon dioxide, sapphire, a metal, a plastic, and an epoxy.

Abstract: In general, this disclosure describes a semiconductor device that exhibits an increased resistance and reduced leakage current in a reverse-biased state, and a method for manufacturing such a semiconductor device. For example, in one embodiment, the increased resistance in the reverse-biased state is obtained by introducing either a P+ or P? type impurity in a polycrystalline silicon layer formed on an N? type epitaxial layer. Additionally, the semiconductor device maintains a low resistance in a forward-biased state. To keep the forward-biased resistance low, the polycrystalline silicon layer in the vicinity of a gate electrode may be of an N+ type. Furthermore, an N+ type source extracting region is formed on the surface of the polycrystalline silicon layer to connect a source electrode to a drain electrode and maintain a low resistance when forward-biased.

Abstract: Gallium nitride material structures are provided, as well as devices and methods associated with such structures. The structures include a diamond region which may facilitate conduction and removal of heat generated within the gallium nitride material during device operation. The structures described herein may form the basis of a number of semiconductor devices and, in particular, transistors (e.g., FETs).

Abstract: A method of depositing nanocrystalline diamond film on a substrate at a rate of not less than about 0.2 microns/hour at a substrate temperature less than about 500° C. The method includes seeding the substrate surface with nanocrystalline diamond powder to an areal density of not less than about 1010sites/cm2, and contacting the seeded substrate surface with a gas of about 99% by volume of an inert gas other than helium and about 1% by volume of methane or hydrogen and one or more of acetylene, fullerene and anthracene in the presence of a microwave induced plasma while maintaining the substrate temperature less than about 500° C. to deposit nanocrystalline diamond on the seeded substrate surface at a rate not less than about 0.2 microns/hour. Coatings of nanocrystalline diamond with average particle diameters of less than about 20 nanometers can be deposited with thermal budgets of 500° C.-4 hours or less onto a variety of substrates such as MEMS devices.

Abstract: A method of forming a high thermal conductivity diamond film and its associated structures comprising selectively nucleating a region of a substrate, and forming a diamond film on the substrate such that the diamond film has large grains, which are at least about 20 microns in size. Thus, the larger grained diamond film has greatly improved thermal management capabilities and improves the efficiency and speed of a microelectronic device.

Abstract: The field effect transistor comprises a source and a drain connected by a channel controlled by a gate electrode separated from the channel by a gate insulator. The channel is formed by a diamond-like carbon layer. The method for making the transistor successively comprises deposition of a diamond-like carbon layer on a substrate, deposition of a gate insulating layer and deposition of at least one conducting layer. The conducting layer is etched to form the gate electrode. Then an insulating material is deposited on the flanks of the gate electrode to form a lateral insulator. Then the gate insulating layer is etched and the diamond-like carbon layer is etched so as to delineate the channel. Then a semi-conducting material designed to form the source and a semi-conducting material designed to form the drain are deposited on each side of the channel.

Abstract: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a heat flow control heat transfer part for drawing heat from the processing object to generate a heat flow from a central area to a peripheral area of the processing object.

Abstract: A method for surface treatment of diamond comprising exposing the surface of diamond to UV light containing wavelengths of 172 nm to 184.9 nm and 253.7 nm at an integrated exposure of 10 to 5,000 J/cm2 in an environment of an atmosphere having an oxygen concentration of 20 to 100% and an ozone concentration of 10 to 500,000 ppm to adsorb oxygen on the surface of diamond.

Abstract: In the SiC vertical MOSFET having a low-concentration p-type deposition film provided therein with a channel region and a base region resulting from reverse-implantation to n-type through ion implantation, dielectric breakdown of gate oxide film used to occur at the time of off, thereby preventing a further blocking voltage enhancement. This problem has been resolved by interposing of a low-concentration n-type deposition film between a low-concentration p-type deposition film and a high-concentration gate layer and selectively forming of a base region resulting from reverse-implantation to n-type through ion implantation in the low-concentration p-type deposition film so that the thickness of deposition film between the high-concentration gate layer and each of channel region and gate oxide layer is increased.

Abstract: The present invention discloses a method of manufacturing a wiring substrate to which a semiconductor chip mounted. The method includes the steps of forming a base, forming a peeling layer on the base, forming a capacitor having a plurality of layers on the peeling layer, and forming a wiring part in the capacitor for connecting the capacitor to the semiconductor chip.

Abstract: A dual damascene structure comprising a composite barrier/etch stop layer including a lower silicon carbide (SiC) layer and an upper first oxygen doped SiC layer formed over a substrate is provided. A first dielectric layer is formed over the first oxygen doped SiC layer followed by a second oxygen doped SiC etch stop layer, and a second dielectric layer. An opening with a via and an overlying trench extends through the second dielectric layer, the second oxygen doped SiC etch stop layer, the first dielectric layer, the upper first oxygen doped SiC layer and at least a portion of the lower silicon carbide (SiC) layer. The opening is filled with a diffusion barrier layer and a metal layer.

Abstract: A semiconductor device includes: a semiconductor layer 10; a semiconductor region 15s of a first conductivity type defined on the surface 10s of the semiconductor layer; a semiconductor region 14s of a second conductivity type defined on the surface 10s of the semiconductor layer to surround the semiconductor region 15s; and a conductor 19 with a conductive surface 19s to contact with the semiconductor regions 15s and 14s. The semiconductor layer 10 includes silicon carbide. At least one of the semiconductor region 15s and the conductive surface 19s is not circular. The semiconductor region 15s and the conductive surface 19s are shaped such that as the degree of misalignment between the conductive surface 19s and the semiconductor region 15s increases from zero through one-third of the width of the conductive surface 19s, a portion of the profile of the conductive surface 19s that crosses the semiconductor region 15s has smoothly changing lengths.

Abstract: A semiconductor device of the invention includes a first conductive type semiconductor base substrate; and a switching mechanism which is formed on a first main surface of the semiconductor base substrate and switches ON/OFF of a current. In the semiconductor base substrate, a plurality of columnar hetero-semiconductor regions are formed at spaced intervals within the semiconductor substrate, and the hetero-semiconductor regions are made of a semiconductor material having a different band gap from the semiconductor substrate and extend between the first main surface and a second main surface opposite to the first main surface.

Abstract: A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n? and p? SiC epilayers. I-V measurements on p+ NCD/n? SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the valence band or acceptor level of the NCD film.

Abstract: A nitride semiconductor device mainly made of a nitride semiconductor material having excellent heat dissipation characteristics and great crystallinity and a method for manufacturing thereof are provided. The method for manufacturing the nitride semiconductor includes vapor-depositing a diamond layer on a silicon substrate, bonding an SOI substrate on a surface of the diamond layer, thinning the SOI substrate, epitaxially growing an GaN layer on the thinned SOI substrate, removing the silicon substrate, and bonding, on a rear-surface of the diamond layer, a material having a thermal conductivity greater than a thermal conductivity of the silicon substrate. The SOI substrate has an outermost surface layer and a silicon oxide layer. In the thinning, the SOI substrate is thinned by selectively removed through the silicon oxide layer, so that only the outermost surface layer is left.

Abstract: Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer onto the base layer such that the semiconductor layer lattice is substantially oriented with respect to the base layer lattice, and disposing a layer of diamond onto the semiconductor layer. The base layer may include numerous materials, including, without limitation, aluminum phosphide (AlP), boron arsenide (BAs), gallium nitride (GaN), indium nitride (InN), and combinations thereof. Additionally, the method may further include removing the lattice-orienting Si substrate and the base layer from the semiconductor layer. In one aspect, the Si substrate may be of a single crystal orientation.

Abstract: A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites accessible for electrical coupling to other electrical structures. A plurality of electrically conductive couplers are connected between the first connection sites and the second connection sites, with neighboring conductive couplers being spaced apart to define at least one flow channel. The at least one flow channel is in fluid communication with a region external to the microelectronic substrate. The generally non-conductive material can be spaced apart from the support member to allow the microelectronic substrate to be separated from the support member.

Abstract: A method of manufacturing a silicon carbide semiconductor substrate is disclosed in which the density of basal plane dislocations (BPDs) in particular is reduced in an SiC crystal substrate. Irregularities in the surface of the substrate due to this reduction also can be flattened. A method of manufacturing a silicon carbide semiconductor substrate is disclosed in which, prior to forming an epitaxial growth layer on a silicon carbide substrate with an off-axis angle of 1° to 8°, parallel line-shape irregularities, which have an irregularity cross-sectional aspect ratio equal to or greater than the tangent of the off-axis angle of the silicon carbide substrate, are formed in the substrate surface. The irregularites have a height between 0.25 ?m and 5 ?m.

Abstract: The semi-conducting support comprises a graphite substrate having a front surface and a rear surface and at least a first stack arranged on the front surface of the substrate. The first stack successively comprises a single-crystal diamond layer, an electrically insulating oxide layer and a semi-conducting layer. The support can comprise a second stack arranged on the rear surface of the substrate and comprising the same succession of layers as the first stack or comprising a polymer material layer. A thermal connection passing through the first and/or second stacks and connecting the graphite substrate to an external surface of the support enables heat to be removed. The method can comprise production of the semi-conducting layer by molecular bonding of rectangular silicon strips onto the oxide layer.

Abstract: Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices. The method comprises depositing a first insulating film on exposed portions of the first surface of the semiconductor substrate and on exposed surfaces of the hetero semiconductor material and forming a second insulating film between the first insulating film and facing surfaces of the semiconductor substrate and the hetero semiconductor region by performing a thermal treatment in an oxidizing atmosphere.

Abstract: Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed.

Abstract: A compact large density memory piezoactuated storage device and process for its fabrication provides an integrated microelectromechanical (MEMS) and/or nanoelectromechanical (NEMS) system and structure that features an integrated large density array of nanotips made of wear-resistant conductive ultrananocrystalline diamond (UNCD) in which the tips are actuated via a piezoelectric thin film integrated with the UNCD tips. The tips of the special piezoactuated storage device effectively contact an underlying metal layer (top electrode) deposited on a polarizable ferroelectric layer that is grown on top of another metal layer (bottom electrode) to form a ferroelectric capacitor. Information is imprinted in the ferroelectric layer by the polarization induced by the application of a voltage pulse between the top and bottom electrodes through the conductive UNCD tips.

Abstract: A method is shown for manufacturing silicon semiconductor nanowires on graphite cloth conducting substrates. The nanowires are grown on the substrate by first depositing a thin gold film on the graphite cloth using RF sputtering. The substrate structure is then exposed to dilute silane, resulting in a uniform coating of Si nanowires on the cloth. A method is also shown for growing calcified mineral phases on such nanowire surfaces as well as for the incorporation of anti-osteoporotic drugs or anti-bacterial agents onto the surface of the nanowires. Lastly, a method is shown for promoting the growth of bone-forming cells onto the nanowire materials by exposing specially treated nanowires to bone marrow cells.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

Abstract: A method of making a mold includes forming spaced mold cavities in a mold body. The mold cavities include geometrically similar portions, but have respective depths below an initial reference surface that vary as a function of position along a particular direction. The mold cavities can be formed using anisotropic etching of preferred crystal directions in single crystal materials such as silicon. A portion of the mold material adjacent the initial reference surface is removed to expose a new reference surface at a tilt angle with respect to the initial reference surface. The modified mold cavities have their respective axes at a new desired tilt angle relative to the new reference surface.

Abstract: An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide.

Abstract: Materials, devices, and methods for enhancing performance of electronic devices such as solar cells, fuels cells, LEDs, thermoelectric conversion devices, and other electronic devices are disclosed and described. A diamond-like carbon electronic device can include a conductive diamond-like carbon cathode having specified carbon, hydrogen and sp2 bonded carbon contents. In some cases, the sp2 bonded carbon content may be sufficient to provide the conductive diamond-like carbon material with a visible light transmissivity of greater than about 0.70. A charge carrier separation layer can be coupled adjacent and between the diamond-like carbon cathode and an anode. The conductive diamond-like carbon material of the present invention can be useful for any other application which can benefit from the use of conductive and transparent electrodes which are also chemically inert, radiation damage resistance, and are simple to manufacture.

Abstract: The invention relates to a method of manufacture of a substrate for fabrication of semi-conductor layers or devices, comprising the steps of providing a wafer of silicon including at least one first surface suitable for use as a substrate for CVD diamond synthesis, growing a layer of CVD diamond of predetermined thickness and having a growth face onto the first surface of the silicon wafer, reducing the thickness of the silicon wafer to a predetermined level, and providing a second surface on the silicon wafer that is suitable for further synthesis of at least one semiconductor layer suitable for use in electronic devices or synthesis of electronic devices on the second surface itself and to a substrate suitable for GaN device growth consisting of a CVD diamond layer intimately attached to a silicon surface.

Abstract: According to the first aspect of the present invention, a method for fabricating a semiconductor device with a silicon carbide (SiC) film is comprised of a process to grow a silicon carbide film on a substrate; and a process to form a groove in the periphery of a region on the silicon carbide film in which crystal defects are aggregated. According to the second aspect of the present invention, a method for fabricating a semiconductor device with a silicon carbide (SiC) film is comprised of a process to grow a silicon carbide film on a substrate; and a process to form a groove on said silicon carbide film so that a region in which crystal defects are aggregated in said silicon carbide film is removed.

Abstract: The conventional detection technique has the following problems in detecting interference fringes: (1) Setting and adjustment are complex and difficult to conduct; (2) A phase image and an amplitude image cannot be displayed simultaneously; and (3) Detection efficiency of electron beams is low. The invention provides a scanning interference electron microscope which is improved in detection efficiency of electron beam interference fringes, and enables the user to observe electric and magnetic information easily in a micro domain of a specimen as a scan image of a high S/N ratio under optimum conditions.

Abstract: Self-aligned fabrication of silicon carbide semiconductor devices is a desirable technique enabling reduction in the number of photolithographic steps, simplified alignment of different device regions, and reduced spacing between the device regions. This invention provides a method of fabricating silicon carbide (SiC) devices utilizing low temperature selective epitaxial growth which allows avoiding degradation of many masking materials attractive for selective epitaxial growth. Another aspect of this invention is a combination of the low temperature selective epitaxial growth of SiC and self-aligned processes.

Abstract: Epitaxial silicon carbide layers are fabricated by forming features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. The epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes features therein.

Abstract: A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in contact with the electrically conductive diamond layer, and a gate contact is on the electrically insulating diamond layer. The diamond layers may be homoepitaxial, polycrystalline, nanocrystalline or ultrananocrystalline in various combinations. A method of making a substantially all diamond self-aligned gate transistor is disclosed in which seeding and patterning can be avoided or minimized, if desired.

Abstract: The invention relates to an electrical component having a resistance area and contacts electrically connected to the resistance area, the resistance area including electrically conductive diamond. The resistance area can be configured as a resistance layer on top of a substrate while the substrate can be made at least in part of electrically non-conducting diamond.

Abstract: A manufacturing method for a large-scale diamond substrate and the produced substrate that is suitable for semiconductor lithography processing and large-scale optical parts, semiconductor materials, thermal-release substrate, semiconductor wafer processing, back-feed devices, and others. The manufacturing method of the present invention includes: preparing a substrate having a main face including a first region which is a concave and a second region which surrounds the first region, and mounting, on the first region, a single crystalline diamond seed substrate having a plate thickness thicker than the concave depth of the first region; forming a CVD diamond layer from the single crystalline diamond seed substrate using a chemical vapor deposition, and mutually connecting by forming a CVD diamond layer on the second region at the same time; and polishing to substantially flatten both the CVD diamond layers and on the second region by mechanically polishing.

Abstract: Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region of a first conductivity type, a buried silicon carbide region of a second conductivity type opposite to the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer. The source region and the buried silicon carbide region are formed utilizing a first window of the mask layer. Then, the well region is formed utilizing a second window of the mask layer, the second window being provided by a subsequent etch of the mask layer having the first window.

Abstract: Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, an electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance and contacting the semiconductor substrate and the gate insulation layer, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate. A mask layer is formed on the hetero semiconductor region, and the electric field alleviation region and the heterojunction driving end are formed by using at least a portion of the first mask layer.

Abstract: A light-emitting diode chip (1), in which over a substrate (2), a series of epitaxial layers (3) with a radiation-emitting active structure (4) based on InGaN is disposed. Between the substrate (2) and the active structure (4), a buffer layer (20) is provided. The material or materials of the buffer layer (20) are selected such that their epitaxial surface (6) for the epitaxy of the active structure (4) is unstressed or slightly stressed at their epitaxial temperature. The active structure (4) has In-rich zones (5), disposed laterally side by side relative to the epitaxial plane, in which zones the In content is higher than in other regions of the active structure (4). A preferred method for producing the chip is disclosed.

Abstract: The invention relates to a method of producing an n-type diamond. The inventive method comprises an n-doping stage during which a donor species is vacuum diffused in a diamond that was initially doped with an acceptor, in order to form donor groups containing the donor species, at a temperature that is less than or equal to the dissociation temperature of the complexes formed between the acceptor and the donor species.

Abstract: Semiconductor-on-diamond devices and methods for making such devices are provided. One such method may include depositing a semiconductor layer on a semiconductor substrate, depositing an adynamic diamond layer on the semiconductor layer opposite the semiconductor substrate, and coupling a support substrate to the adynamic diamond layer opposite the semiconductor layer to support the adynamic layer.

Abstract: Various embodiments of the present invention are directed to methods for coupling semiconductor-based photonic devices to diamond. In one embodiment of the present invention, a method for coupling a photonic device with a diamond structure comprises embedding the diamond structure in a first substrate, where the first substrate comprises a first transparent material. The photonic device is formed in a semiconductor material, which is supported by a second substrate. An intermediate structure is formed by depositing a second transparent material over the photonic device. The second transparent material may have substantially the same refractive index as the first transparent material. The intermediate structure is then separated from the second substrate, and the intermediated structure is adhered to the first substrate so that the photonic device optically couples with the diamond structure.

Abstract: A semiconductor device, includes: 1) an electric field relaxing area, including: i) a hetero junction formed by the followings: a) a first semiconductor material, and b) a second semiconductor material different from the first semiconductor material in band gap, and ii) an impurity introducing area so formed on the first semiconductor material as to contact the hetero junction.

Abstract: In at least some embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit fabricated on a silicon carbide substrate, and a thick passivation layer. In other embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit formed from silicon located on a sapphire substrate, and a thick passivation layer. The electronic devices may be implemented in the context of hydrocarbon drilling and production operations.

Abstract: Diamond heat spreaders are produced having thermal properties approaching that of pure diamond. Diamond particles of relatively large grain size are tightly packed to maximize diamond-to-diamond contact. Subsequently, smaller diamond particles may be introduced into the interstitial voids to further increase the diamond content per volume. An interstitial material is then introduced which substantially fills the remaining voids and should have favorable thermal properties as well as form chemical bonds with the diamond. Alternatively, the packed diamond may be subjected to ultrahigh pressures over 4 GPa in the presence of a sintering aid. The resulting diamond heat spreader has diamond particles which are substantially sintered together to form a continuous diamond network and small amounts of a sintering agent.

Abstract: A method of forming a layer of silicon carbide wherein silicon clusters are dissociated in a gas phase. Silicon clusters may be dissociated by a silicon-etching gas such as a group VII-containing component. A semiconductor device is also disclosed having a layer formed by the methods of the invention.

Abstract: A process for defining and controlling the mask height of sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are used to form the mask structure. Having an RIE-resistant layer precisely defines the DLC edge and minimizes the line edge roughness that result from fast removal of duramide during RIE. This solution controls the formation of the edges of the sensors and provides good definition for DLC mask edges. The image layer may be chemical mechanical polished to eliminate ion milling before the final RIE step.

Abstract: A process for defining and controlling the track width for sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are used to form the mask structure. Having an RIE-resistant layer precisely defines the DLC edge and minimizes the line edge roughness that result from fast removal of duramide during RIE. This solution controls the formation of the edges of the sensors and provides good definition for DLC mask edges. The image layer may be chemical mechanical polished to eliminate ion milling before the final RIE step.