Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.

Abstract: A fingerprint chip package and method for processing same, relating to a field of biometric identification. The fingerprint chip package includes: a lead frame (1), a chip (2), and a plastic packaging part enclosing the lead frame (1) and the chip (2); the lead frame (1) comprises a base island (13), a connecting rib (11), and a golden finger (12); the base island (13) is used for bearing the chip (2); the connecting rib (11) is used for supporting the lead frame (1) and connecting the base island (13) via the golden finger (12); and the golden finger (12) is used for fixing the base island (13) and electrically connecting with the chip (2).

Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Abstract: A lead frame includes a lead formed of a conductive material and having first and second ends, opposing first and second main surfaces, and opposing first and second side surfaces each extending between the first and second main surfaces. A polymeric layer is formed at least on the first main surface and the first and second side surfaces of the lead at least proximate the second end of the lead. An opening in the polymeric layer on the first main surface of the lead proximate the second end is provided for connecting the lead to, for example, a semiconductor die via a bond wire.

Abstract: Apparatus and methods provide for utilizing continuous curved composite stringers to control the loads and corresponding moments within curved regions of an aircraft or other vehicle without delamination or other interlamina failures. According to embodiments described herein, any number of tapered height curved composite stringers may be coupled to continuous skin components to create a curved continuous panel. The tapered height curved composite stringers may have webs that taper to a reduced height within curved regions and corresponding base flanges that widen during web tapering. Reinforcement fittings may be coupled to the base flanges in the curved regions for further strengthening and to provide for the attachment of supplemental panels to the stringers.

Abstract: A method for manufacturing open cavity integrated circuit packages, the method comprising: placing a wire-bound integrated circuit in a mold; forcing a pin to contact a die of the wire-bound integrated circuit by applying a force between the pin and the mold; injecting plastic into the mold; allowing the plastic to set around the integrated circuit to form a package having an open cavity defined by the pin; and removing the open cavity integrated circuit package from the mold. A mold for forming a package for an integrated circuit sensor device, comprising: a bottom part for supporting an integrated circuit die; a top part that is operable to be placed on top of said bottom part to form a cavity into which a plastic material can be injected to form the package, wherein the top part of the mold comprises a spring-loaded pin arrangement comprising a cover that covers a sensor area on the integrated circuit die and provides for an opening when the plastic material is injected.

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract: A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.

Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.

Abstract: A self-assembly apparatus for assembling a plurality of devices with a predetermined aspect ratio is provided. The self-assembly apparatus includes a guiding element, a vibration device, and a magnetic field inducing device. The guiding element has a mesh structure. The vibration device is coupled to the guiding element and configured to vibrate the guiding element. The magnetic field inducing device is disposed below the guiding element and configured to generate a time-varying magnetic field to rotate each of the devices. Through a collective effect of the vibration of the guiding element, the time-varying magnetic field, and the self-gravity of each of the devices, the devices are positioned on a plate between the guiding element and the magnetic field inducing device through the mesh structure.

Abstract: In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice is mounted on a semiconductor substrate, and neighboring ones of the dice are separated by a distance at which a first one of the neighboring dice will contact a meniscus of a flange of the neighboring die during underfill to form a capillary bridge between the neighboring dice. Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact terminals on a top surface of the substrate. Underfill is deposited along one or more edges of one or more of the plurality of dice. As a result of the capillary bridge formed between neighboring dice, flow of underfill is induced between the bottom surfaces of the neighboring dice and the top surface of the substrate. The dispensed underfill is cured.

Abstract: An ultrasonic welding tool is used to bond end portions of an external connection terminal to circuit patterns of an insulating substrate, with a Vickers hardness not lower than 90. Bonding end portions are provided integrally with a bar in the external connection terminal. A bonding end portion located substantially in the lengthwise center of the bar is bonded first, then others are bonded alternately in order toward either end. Hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased, and displacement of the bonding end portion in either end from its regular position is suppressed to keep bonding strength high. Bonding strength of the ultrasonic welding portions between the external connection terminal and the circuit patterns of the insulating substrate can be increased so that long-term reliability can be secured in a semiconductor device.

Abstract: A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

Abstract: A semiconductor device has a first semiconductor die mounted to a first contact pad on a leadframe or substrate with bumps. A conductive pillar is formed over a second semiconductor die. The second die is mounted over the first die by electrically connecting the conductive pillar to a second contact pad on the substrate with bumps. The second die is larger than the first die. An encapsulant is deposited over the first and second die. Alternatively, the conductive pillars are formed over the substrate around the first die. A heat sink is formed over the second die, and a thermal interface material is formed between the first and second die. An underfill material is deposited under the first semiconductor die. A shielding layer is formed between the first and second die. An interconnect structure can be formed over the second contact pad of the substrate.

Abstract: This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips.

Abstract: There is provided an LED package having high heat dissipation efficiency. An LED package according to an aspect of the invention may include: a package body including a first groove portion being recessed into the package body and provided as a mounting area on the top of the package body; first and second lead frames arranged on a lower surface of the first groove portion while parts of the first and second lead frames are exposed; an LED chip mounted onto the lower surface of the first groove portion and electrically connected to the first and second lead frames; and a plurality of heat dissipation patterns provided on the bottom of the package body and formed of carbon nanotubes.

Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate and a die, and coupling the die to the substrate, wherein a gap remains between the die and the substrate. The method also includes placing an underfill material on the substrate and delivering at least part of the underfill material into the gap. The method also includes controlling the flow of the underfill material in the gap using magnetic force. Other embodiments are described and claimed.

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract: By increasing the area of a source electrode 3a of a semiconductor element 3 and the area of a source terminal 2b of a lead frame 2, it is possible to extend a joint 8a of the source electrode 3a bonded to a conductive ribbon 6 and a joint 8b of the source terminal 2b. Thus it is possible to reduce an on resistance and easily reduce the number of times a bonding tool comes into contact with the joints to reduce a stress on the semiconductor element 3.

Abstract: Retaining regions 310a and 310b are added to a pad shaped portion 303a of leads and a die pad 302 that are electrically connected via a conductive ribbon 309, so that during the bonding of the ribbon, strong ultrasonic waves can be applied in a state in which the retaining regions 310a and 310b are pressed and fixed. It is therefore possible to reduce a resistance at a joint while firmly bonding the conductive ribbon 309. Further, the bonding strength of the conductive ribbon 309 increases and thus it is possible to eliminate the need for stacking the conductive ribbons 309 and easily reduce a stress caused by ultrasonic waves on a semiconductor chip 306.

Abstract: Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die.

Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed.

Abstract: A method, system and program product for bonding two circuitry-including semiconductor substrates, and a related stage, are disclosed. In one embodiment, a method of bonding two circuitry-including substrates includes: providing a first stage for holding a first circuitry-including substrate and a second stage for holding a second circuitry-including substrate; identifying an alignment mark on each substrate; determining a location and a topography of each alignment mark using laser diffraction; creating an alignment model for each substrate based on the location and topography the alignment mark thereon; and bonding the first and second circuitry-including substrates together while aligning the first and second substrate based on the alignment model.

Abstract: The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.

Abstract: A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed.

Abstract: In one example embodiment, a process for cleaving a wafer cell includes several acts. First a wafer cell is affixed to an adhesive film. Next, the adhesive film is stretched substantially uniformly. Then, the adhesive film is further stretched in a direction that is substantially orthogonal to a predetermined reference direction. Next, the wafer cell is scribed to form a notch that is oriented substantially parallel to the predetermined reference direction. Finally, the wafer cell is cleaved at a location substantially along the notch.

Abstract: An ultrasonic bonding equipment for manufacturing a semiconductor device comprises a tip portion. The tip portion has a top surface which is faced to a member to be bonded, and propagates an ultrasonic vibration to the top surface. A plurality of protruding portions are provided on the top surface. Each of the protruding portions has: a first pair of opposite side surfaces inclined with respect to the top surface; and a second pair of opposite side surfaces substantially vertical to the top surface. A semiconductor device comprises: a semiconductor chip; a lead; and a bonding strap electrically connecting the semiconductor chip and the lead. A recess is formed on an upper surface of the bonding strap in at least one of a first region where the bonding strap and the semiconductor chip are connected and a second region where the bonding strap and the lead is connected.

Abstract: A method for making micro-electromechanical system devices includes: (a) forming a sacrificial layer on a device wafer; (b) forming a plurality of loop-shaped through-holes in the sacrificial layer so as to form the sacrificial layer into a plurality of enclosed portions; (c) forming a plurality of cover caps on the sacrificial layer such that the cover caps respectively enclose the enclosed portions of the sacrificial layer; (d) forming a device through-hole in each of active units of the device wafer so as to form an active part suspended in each of the active units; and (e) removing the enclosed portions of the sacrificial layer through the device through-holes in the active units of the device wafer.

Abstract: A mounting apparatus applies ultrasonic vibration exactly to a junction between a SMD and a SMD receiving device and maintains the junction at the suitable temperature, in simple construction in ultrasonic bonding of the SMD and the SMD receiving device held by holding unit. This includes SMD holding unit, SMD receiving device holding unit, moving unit moving at least one of the SMD holding unit and SMD receiving device holding units to contact each other, vibration generating unit applying ultrasonic vibration to the a contact portion between the SMD and the SMD receiving device, pressing unit applying an bias force between the SMD and SMD receiving device, heating unit arranged movably so as to surround in a noncontact manner a portion of the SMD holding unit near the SMD and heating the SMD holding unit, and interlocking unit interlocking the heating unit with the SMD holding unit.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a packaging substrate, a chip, an interposer substrate, a wire and an adhesive layer. The packaging substrate has an upper packaging surface. The chip is disposed on the upper packaging surface. The wire connects the packaging substrate and the interposer substrate. The adhesive layer is disposed between the packaging substrate and the interposer substrate, and covers the entire chip and part of the upper packaging surface. The adhesive layer includes a first adhesive part and a second adhesive part. The first adhesive part adheres the interposer substrate and the chip. The second adhesive part surrounds the first adhesive part, adheres the interposer substrate and the packaging substrate, and supports a periphery of the interposer substrate.

Abstract: Attaching a semiconductor chip to a substrate by applying mechanical vibrations (150) to a polymeric compound (130) and the contacting areas (114, 124) of a first (113) and a second (121) metallic member immersed in the compound, while the two metallic members approach (140) each other until they touch. The mechanical vibration causes displacements of the first member relative to the second member, and the vibration includes displacements (150) oriented at right angles to the direction (140) of the approach. The polymeric compound (130) includes a non-conductive adhesive resin paste (NCP) and filler particles; the paste is deposited before the attaching step. The first member (113) is affixed to the chip and the second member (121) to the substrate.

Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.

Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.

Abstract: A semiconductor device includes a mount substrate and a semiconductor chip mounted upon the mount substrate via a metal bump, wherein metal bump includes an inner part joined to the semiconductor chip and an outer part covering the inner part, the outer part having an increased hardness as compared with the inner part.

Abstract: In a flip chip mounted body in which a semiconductor chip (20) having a plurality of electrode terminals (21) is disposed so as to be opposed to a wiring board (10) having a plurality of connection terminals (11), with the connection terminals (11) and the electrode terminals (21) being connected electrically, a resin (13) containing electrically conductive particles (12) is supplied between the connection terminals (11) and the electrode terminals (21), the electrically conductive particles (12) and the resin (13) are heated and melted, and vibrations are applied so as to make them flow. The molten electrically conductive particles (12) are allowed to self-assemble between the connection terminals (11) and the electrode terminals (21), thereby forming connectors (22) that connect them electrically.

Abstract: A method of manufacturing a semiconductor device includes a bonding step of bonding a chip on a wiring board by means of a bonding layer, and a wire bonding step of bonding a wire to a pad on the chip while applying ultrasonic vibration after the bonding step. A material having an elastic modulus of 100 MPa or higher at a process temperature in the wire bonding step is used as the bonding layer.

Abstract: A flip-chip package structure comprises a carrier, a block bump, and a die. The carrier is a lead frame or substrate that comprises a lead pattern side, and an electrode pin is disposed on the lead pattern side. The die comprises an active side, and a bond pad is disposed on the active side. The block bump is bonded to the electrode pin; the bond pad of the die is attached on the carrier through the block bump, so that the die and the carrier joint together to form the flip chip package structure. Besides, the block bump is formed by the wedge bonding, and therefore in bumping size and shapes can easily form larger bump, which will increase the compactness between the die and the carrier.

Abstract: A small structure which uses bonding wires to prevent disturbance and provide support and a method of fabricating the same are provided. The small structure includes a floating body having a plurality of first contact pads, a base having a plurality of second contact pads, and a plurality of bonding wires electrically connecting the first and second contact pads and elastically supporting the floating body. The method of fabricating the small structure includes preparing a base, forming a sacrificial layer on the base, disposing a floating body on the sacrificial layer, connecting the base and the floating body with bonding wires, and removing the sacrificial layer. Thereby, fabrication costs of the small structure are reduced.

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract: Circuit elements, such as aluminum interconnects, and a protective film for protecting these circuit elements are formed on a surface of a semiconductor substrate. Resist is formed covering the protective film. The semiconductor substrate on which the resist covering the protective film is formed is dipped into pure water so as to allow the water to filter into a gap between the resist and semiconductor substrate. Then the semiconductor substrate having the resist thereon is dried in high temperature air, and the resist is adhered to the semiconductor substrate by a sticking function due to the surface tension generated when the water is decreasing. The semiconductor substrate to which the resist is adhered is cleaned by a hydrogen fluoride aqueous solution.

Abstract: The objective of this invention is to provide an assembling method for electronic members characterized by the fact that electronic members can be joined reliably and easily without using solder paste. The semiconductor device of the present invention has the following parts: silicon substrate 100 with circuit elements formed on it, plural protrusion-shaped metal electrodes 110A, 110B formed on silicon substrate 100, and capacitor 140 having Au-plated electrodes 142, 144. The electrodes 142, 144 of capacitor 140 are metallurgically joined to protrusion-shaped metal electrodes 110A, 110B by means of ultrasonic thermo-compression bonding.

Abstract: A semiconductor module and a method. One embodiment provides a housing with a housing frame and a pluggable carrier which is plugged in the housing frame. The pluggable carrier is equipped with a lead which includes an internal portion which is arranged inside the housing, and an external portion which is arranged outside the housing. The internal portion is electrically coupled to an electric component of the power semiconductor module. The external portion allows for electrically coupling the power semiconductor module.

Abstract: Attaching a semiconductor chip to a substrate by applying mechanical vibrations (150) to a polymeric compound (130) and the contacting areas (114, 124) of a first (113) and a second (121) metallic member immersed in the compound, while the two metallic members approach (140) each other until they touch. The mechanical vibration causes displacements of the first member relative to the second member, and the vibration includes displacements (150) oriented at right angles to the direction (140) of the approach. The polymeric compound (130) includes a non-conductive adhesive resin paste (NCP) and filler particles; the paste is deposited before the attaching step. The first member (113) is affixed to the chip and the second member (121) to the substrate.

Abstract: A method of packaging a semiconductor includes providing a support structure. An adhesive layer is formed overlying the support structure and is in contact with the support structure. A plurality of semiconductor die is placed on the adhesive layer. The semiconductor die are laterally separated from each other and have electrical contacts that are in contact with the adhesive layer. A layer of encapsulating material is formed overlying and between the plurality of semiconductor die and has a distribution of filler material. A concentration of the filler material is increased in all areas laterally adjacent each of the plurality of semiconductor die.

Abstract: A method for fabricating a semiconductor component with through interconnects can include the steps of providing a semiconductor substrate with substrate contacts, and forming openings from a backside of the substrate aligned with the substrate contacts. The method can also include the steps of providing an interposer substrate (or alternately a second semiconductor substrate), forming projections on the interposer substrate (or on the second semiconductor substrate), and forming conductive vias in the projections. The method can also include the steps of placing the projections in physical contact with the openings, and placing the conductive vias in electrical contact with the substrate contacts. The method can also include the steps of bonding the conductive vias to the substrate contacts, and forming terminal contacts on the interposer substrate (or alternately on one of the semiconductor substrates) in electrical communication with the conductive vias.

Abstract: The method of bonding flying leads is capable of efficiently supersonic-bonding the flying leads to pads of a board and improving bonding reliability therebetween. The method comprises the steps of: mechanically processing the board so as to form projections, which act as margins for deformation, in boding faces of the pads, on each of which the flying lead will be bonded, positioning the flying leads to correspond to the pads; and applying supersonic vibrations to a bonding tool so as to deform and crush the projections, whereby the flying leads are respectively bonded to the pads.

Abstract: Systems and methods are provided to mitigate excess die attachment material accrual, and parasitic conductive paths formed thereby. A die attachment material (e.g., solder) is melted using a combination of localized heat sources and ultrasonic energy. The heat sources bring the die attachment material close to its melting point, which reduces an amount of bonding force associated with purely ultrasonic bonding techniques. An ultrasonic transducer brings the die attachment material the rest of the way up to its melting point, which reduces the overall temperature that the die and/or sensitive components thereon endure during the bonding process.

Abstract: A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 ?m thick) has on its first surface first copper contact pads (221) covered with a continuous thin nickel layer (222) of about 0.04 to 0.12 ?m thickness. Gold including stud (212) is contacting the nickel. On the second substrate surface are second copper contact pads (231) covered with an alloy layer (about 2 to 3 ?m thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body (103) comprising tin is metallurgically attached to the alloy layer of each second pad.

Abstract: The structure of mounting an electronic component on a circuit board is capable of securely flip-chip-bonding the electronic component having bumps, whose separations are very short, to the circuit board without displacement. The structure of mounting an electronic component on a circuit board is characterized in that bumps of the electronic component are respectively flip-chip-bonded to electrodes of the circuit board by applying ultrasonic vibrations to the electronic component, and that a center of each of the bumps is previously relatively displaced, with respect to a center of each of the electrodes in a width direction, in a direction parallel to a direction of the ultrasonic vibrations.