Abstract: A silicon carbide substrate includes: an n type drift layer having a first surface and a second surface opposite to each other; a p type body region provided in the first surface of the n type drift layer; and an n type emitter region provided on the p type body region and separated from the n type drift layer by the p type body region. A gate insulating film is provided on the p type body region so as to connect the n type drift layer and the n type emitter region to each other. A p type Si collector layer is directly provided on the silicon carbide substrate to face the second surface of the n type drift layer.

Abstract: A semiconductor device including a substrate, a metal layer, an insulating layer, a semiconductor layer, a drain and a source is provided. The substrate has a surface and a first cavity. The metal layer is disposed on the substrate and covers the surface and inner-wall of the first cavity to define a second cavity corresponding to the first cavity. The insulating layer covers the metal layer and inner-wall of the second cavity to define a third cavity corresponding to the second cavity. The semiconductor layer exposes a portion of the insulating layer and covers the inner-wall of the third cavity to define a fourth cavity corresponding to the third cavity. The drain and source are disposed on the semiconductor layer and covers a portion of the semiconductor layer and a portion of the insulating layer, in which the drain and source expose the fourth cavity.

Abstract: Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

Abstract: Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.

Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.

Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.

Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

Abstract: A continuity testing device is provided which can reliably detect incomplete-fitting of the retainer of the connector. The continuity testing device includes a connector guide block into which the connector is inserted in a transverse direction and which is fixed above an opening formed on a cover plate of a case of the continuity testing device, a detection plate provided to the connector guide block and arranged above the connector so as to contact with the incompletely-fitted retainer of the connector when moved downward, a detection pin arranged at the detection plate, a continuity testing part arranged to move in the vertical direction toward the connector, a drive mechanism that operates the detection plate to move in the vertical direction in conjunction with the continuity testing part, and a switch that is activated by the detection pin when the detection pin is completely moved down to the switch.

Abstract: A method of forming an electromechanical power switch for controlling power to integrated circuit (IC) devices and related devices. At least some of the illustrative embodiments are methods comprising forming at least one IC device on a front surface of a semiconductor substrate. The at least one IC device includes at least one circuit block and at least one power switch circuit. A dielectric layer is deposited on the IC device, and first and second electromechanical power switches are formed on the dielectric layer. The first power switch gates a voltage to the circuit block and the second power switch gates the voltage to the IC device. The first power switch is actuated by the power switch circuit, and the voltage to the circuit block is switched off. Alternatively, the second power switch is actuated by the power switch circuit, and the voltage to the IC device is switched off.

Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.

Abstract: An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

Abstract: A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.

Abstract: On a single-crystal substrate, a drift layer is formed. The drift layer has a first surface facing the single-crystal substrate, and a second surface opposite to the first surface, is made of silicon carbide, and has first conductivity type. On the second surface of the drift layer, a collector layer made of silicon carbide and having second conductivity type is formed. By removing the single-crystal substrate, the first surface of the drift layer is exposed. A body region and an emitter region are formed. The body region is disposed in the first surface of the drift layer, and has the second conductivity type different from the first conductivity type. The emitter region is disposed on the body region, is separated from the drift layer by the body region, and has first conductivity type.

Abstract: Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed.

Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.

Abstract: A silicon carbide (SiC) bipolar junction transistor (BJT) including a collector region and a base region having an extrinsic part. The SiC BJT including an emitter region and a surface passivation layer deposited on the extrinsic part between an emitter contact contacting the emitter region and a base contact contacting the base region. The SiC BJT also including a surface gate at the surface passivation layer.

Abstract: A method for manufacturing a reverse-conducting semiconductor device (RC-IGBT) with a seventh layer formed as a gate electrode and a first electrical contact on a emitter side and a second electrical contact on a collector side, which is opposite the emitter side, a wafer of a first conductivity type with a first side and a second side opposite the first side is provided. For the manufacturing of the RC-IGBT on the collector side, a first layer of the first conductivity type or of a second conductivity type is created on the second side. A mask with an opening is created on the first layer and those parts of the first layer, on which the opening of the mask is arranged, are removed. The remaining parts of the first layer form a third layer. Afterwards, for the manufacturing of a second layer of a different conductivity type than the third layer, ions are implanted into the wafer on the second side into those parts of the wafer, on which the at least one opening is arranged.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a microelectronic die, a plurality of electrical couplers projecting from the die, and a flowable material disposed on the die. The die includes an integrated circuit and a plurality of terminals operably coupled to the integrated circuit. The electrical couplers are attached to corresponding terminals on the die. The flowable material includes a plurality of spacer elements sized to space the die apart from another component. The flowable material may be a no-flow underfill, a flux compound, or other suitable material.

Abstract: There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.

Abstract: A method of manufacturing a reverse blocking insulated gate bipolar transistor to form an isolation layer for bending and extending a pn junction, which exhibits a high reverse withstand voltage, to the front surface side. This ensures a high withstand voltage in the reversed direction and reduces leakage current in the reversely biased condition. Formation of a tapered groove by an anisotropic alkali etching process is conducted, resulting in a semiconductor substrate left with a thickness of at least 60 ?m between one principal surface and the bottom surface of the tapered groove formed from the other principal surface.

Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

Abstract: A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

Abstract: A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region.

Abstract: An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer.

Abstract: A semiconductor device includes a direct light-triggered thyristor triggered by an optical gate signal, a first optical fiber connected to the direct light-triggered thyristor and through which the optical gate signal is transmitted, a second optical fiber used to extend the first optical fiber, and a inter-optical-fiber relaying unit configured to connect the first optical fiber to the second optical fiber and to input the optical gate signal output from the second optical fiber to the first optical fiber.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an epitaxial layer over a semiconductor substrate, a first well region over a epitaxial layer, a first isolation layer and/or a third isolation layer at opposite sides of said first well region and/or a second isolation layer over a first well region between first and third isolation layers. A semiconductor device may include a gate over a second isolation layer. A semiconductor device may include a second well region over a first well region between a third isolation layer and a gate, a first ion-implanted region over a second well region between a third isolation layer and a gate, and/or a second ion-implanted region between a first ion-implanted region and a gate. A semiconductor device may include an accumulation channel between a second well region and a gate.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

Abstract: Semiconductor switching devices include a wide band-gap drift layer having a first conductivity type (e.g., n-type), and first and second wide band-gap well regions having a second conductivity type (e.g., p-type) on the wide band-gap drift layer. First and second wide band-gap source/drain regions of the first conductivity type are on the first and second wide band-gap well regions, respectively. A wide band-gap JFET region having the first conductivity type is provided between the first and second well regions. This JFET region includes a first local JFET region that is adjacent a side surface of the first well region and a second local JFET region that is adjacent a side surface of the second well region. The local JFET regions have doping concentrations that exceed a doping concentration of a central portion of the JFET region that is between the first and second local JFET regions of the JFET region.

Abstract: A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.

Abstract: A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a second gate structure overlies the second well region, a third gate structure overlies the third well region and is integral with the second gate structure, and a fourth gate structure overlies the fourth well region. Sidewall spacers are formed adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures. In addition, an insulating spacer block is formed overlying a portion of the first well region and a portion of the first gate structure. The insulating spacer block is adjacent a second sidewall of the first gate structure.

Abstract: Disclosed herein is a tunneling fin field effect transistor comprising a fin disposed on a box layer disposed in a wafer; the wafer comprising a silicon substrate and a buried oxide layer. The fin comprises a silicide body that comprises a first silicide region and a second silicide region and forms a short between N and P doped regions. The silicide body is disposed on a surface of the buried oxide layer. A tunneling device disposed between the first silicide region and the second silicide region; the tunneling device comprising a first P-N junction. A gate electrode is further disposed around the fin; the gate electrode comprising a second P-N junction, and a third silicide region; the third silicide region forming a short between N and P doped regions in the gate electrode.

Abstract: An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type.

Abstract: An HF control bi-directional switch component of the type having its gate referenced to the rear surface formed in the front surface of a peripheral well of the component, including two independent gate regions intended to be respectively connected to terminals of a transformer having a midpoint connected to the rear surface terminal of the component.

Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device having a thyristor formed by joining a first p-type semiconductor layer, a first n-type semiconductor layer, a second p-type semiconductor layer, and a second n-type semiconductor layer in order, the method including the steps of: forming the second p-type semiconductor layer including a p-type impurity in a surface layer of a semiconductor substrate; forming the first n-type semiconductor layer including an n-type impurity on the semiconductor substrate including the second p-type semiconductor layer by epitaxial growth; forming a non-doped semiconductor layer on the first n-type semiconductor layer by epitaxial growth; and forming the first p-type semiconductor layer including a p-type impurity on the non-doped semiconductor layer by epitaxial growth.

Abstract: A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device having a thyristor formed by joining a first p-type semiconductor layer, a first n-type semiconductor layer, a second p-type semiconductor layer, and a second n-type semiconductor layer in order, the method including the steps of: forming the second p-type semiconductor layer including a p-type impurity in a surface layer of a semiconductor substrate; forming the first n-type semiconductor layer including an n-type impurity on the semiconductor substrate including the second p-type semiconductor layer by epitaxial growth; forming a non-doped semiconductor layer on the first n-type semiconductor layer by epitaxial growth; and forming the first p-type semiconductor layer including a p-type impurity on the non-doped semiconductor layer by epitaxial growth.

Abstract: A thyristor-based semiconductor device includes a filled trench separating and electrically insulating adjacent thyristor control ports. According to an example embodiment of the present invention, the filled trench is formed in a substrate adjacent to at least one thyristor body region. The filled trench includes a conductive filler material, an insulative material formed on the conductive filler material and at least two laterally-adjacent thyristor control ports separated from one another by the conductive filler material and the insulative material. One of the control ports is adapted for capacitively coupling to the thyristor body region for controlling current in the thyristor. With this approach, two or more control ports can be formed in a single filled trench and electrically isolated by the conductive filler material/insulative material combination.

Abstract: A compact, inexpensive static induction thyristor (SIThy) which is less likely to be broken down at a high voltage rise-up rate during operation and which is used in a high-voltage pulse generator capable of generating a high-voltage short pulse is provided. Thicknesses and impurity concentrations of a base region and a buffer region are determined such that a peak voltage obtained by a peak current at which a punch-through state is brought about does not exceed a breakdown voltage of the SIThy. Such design can achieve an SIThy having a self protecting function of autonomously preventing its breakdown without compromising a turn-on performance in which the peak voltage does not drastically exceed the breakdown voltage of the SIThy even when the peak current increases. Further, a compact SIThy capable of generating a short pulse can be achieved by reducing a gate-channel current-carrying area to a minimum.

Abstract: A semiconductor device including a metal oxide layer, a channel area of the metal oxide layer, a preservation layer formed on the channel area of the metal oxide layer, and at least two channel contacts coupled to the channel area of the metal oxide layer, and a method of forming the same.

Abstract: A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including a base substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, which are laminated in this order; a cell portion disposed in the semiconductor substrate and providing an electric part forming portion; and a periphery portion surrounding the cell portion. The periphery portion includes a trench, which penetrates the second and the third semiconductor layers, reaches the first semiconductor layer, and surrounds the cell portion so that the second and the third semiconductor layers are divided by the trench substantially. The periphery portion further includes a fourth semiconductor layer disposed on an inner wall of the trench.

Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.

Abstract: A method of epitaxially growing backward diodes and diodes grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.

Abstract: A method for stabilizing a tunnel junction component, in which a mask is formed on the surface of a substrate, and conductors are constructed by evaporation onto the substrate in an evaporation chamber, and at least one thin oxide layer element is oxidized on top of a selected conductor. This remains partly under the following conductor, thus forming a tunnel junction element with those conductors and titanium (Ti) or another gettering substance is evaporated on top of the said following conductor, before the tunnel junction component is removed from the evaporation chamber, when the titanium layer thus created protects the tunnel junction element from the detrimental effects of air molecules.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.