Abstract: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.

Abstract: An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.

Abstract: Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by forming diffusion regions at both sides of the isolation region, then by contacting electrodes to the respective diffusion regions. The anti-fuse is initially in a non-conductive state, and is programmed to be in a permanently conductive state by a simple writing circuit.

Abstract: A semiconductor device comprising a substrate, a plurality of dielectric films formed on the substrate, laid one upon another, and a fuse interconnect-wire formed above the substrate and covered with a predetermined one of the dielectric films, and including a fuse main body which is to be blown to electrically disconnect the fuse interconnect-wire, which is smaller than a bottom of a fuse-blowing recess made in the predetermined dielectric film, which has a length not less than the diameter of a fuse-blowing laser beam and which opposes the bottom of the fuse-blowing recess.

Abstract: A method and apparatus for providing an electrical fuse is provided. An electrical fuse is patterned from the active layer of a semiconductor-on-insulator (SOI) wafer. One shape of the electrical fuse may be a first and second portion electrically coupled via a third section. The third section is typically thinner than the first and second portion. An ion implant is performed to fully deplete the electrical fuse, and a silicidation process is performed. Thereafter, standard processing techniques may be used to form vias and other integrated circuit structures.

Abstract: A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.

Abstract: A method for fabricating a fuse for a semiconductor device. The method including: providing a substrate; forming a first dielectric layer on a top surface of said substrate; forming a dielectric mandrel on a top surface of said first dielectric layer; forming a second dielectric layer on top of said mandrel and a top surface of said first dielectric layer forming contact openings down to said substrate in said first and second dielectric layers on opposite sides of said mandrel, said contacts spaced away from said mandrel and leaving portions of said second dielectric layer between said mandrel and said contacts; removing said second dielectric layer from over said mandrel between said contact openings to form a trough; and filling said trough and contact openings with a conductor.

Abstract: Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by applying a programming current to the fuse link. The silicon or polysilicon in the fuses may be provided with a p-n junction. When a fuse is programmed, the silicide or other conductive film forms an open circuit. This forces current though the underlying p-n junction. Unlike conventional silicided polysilicon fuses, fuses with p-n junctions change their qualitative behavior when programmed. Unprogrammed fuses behave like resistors, while programmed fuses behave like diodes. The presence of the p-n junction allows sensing circuitry to determine in a highly accurate qualitative fashion whether a given fuse has been programmed.

Abstract: A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the channel region beneath the gate, causing localized annealing of the channel region. The heated gate causes dopants to diffuse from the source and drain into the channel region, permanently changing the properties of the transistor material and programming the fuse device. The fuse device functions as a transistor in an unprogrammed state, and acts as a shunt in a programmed state, caused by the shorting of the source and drain of the transistor during programming.

Abstract: An increased number of fuses per area are provided in this semiconductor device while complying with the predetermined distance between the fuses. The device having a first patterned, conductive interconnect plane on a passivated substrate; a second patterned, conductive interconnect plane on the first patterned, conductive passivated interconnect plane; contact devices for selectively electrically contact-connecting the patterned, conductive interconnect planes to one another; a fuse device in a nonpassivated section of the second patterned, conductive interconnect plane with predetermined fuse regions for selectively linking interconnects; the fuse device being divided into fuse modules with fuse pairs and the fuse regions thereof at a predetermined distance from one another, which can be linked to a predetermined potential via a central interconnect.

Abstract: A method of forming an integrated circuit device can include forming a plurality of fuse wires on an integrated circuit substrate, and forming an insulating layer on the integrated circuit substrate and on the plurality of fuse wires so that the fuse wires are between the integrated circuit substrate and the insulating layer. A plurality of fuse cutting holes can be formed in the insulating layer wherein each of the fuse cutting holes exposes a target spot on a respective one of the fuse wires, and a cross-sectional area of the fuse wires can be reduced at the exposed target spots. Related structures are also discussed.

Abstract: In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.

Abstract: A configuration of fuses in a semiconductor structure having Cu metallization planes is provided. The semiconductor structure has an Al metal layer on the topmost interconnect plane for providing Al bonding pads. The fuses are configured as Al fuses and, in the semiconductor structure having Cu metallization planes, are provided above the diffusion barrier of the topmost Cu metallization plane but below a passivation layer.

Abstract: A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications.

Abstract: Disclosed is a conductive fuse for a semiconductor device, comprising: a pair of contact portions integrally connected to a fusible portion by connecting portions; the contact portions thicker than the connecting portions and the connecting portions thicker than the fusible portion; a first dielectric under the connecting portions and the fusible portion and extending between the pair of contact portions; and a second dielectric between the first dielectric and the fusible portion, the second dielectric extending between the connecting portions and defining the length of the fusible portion.

Abstract: A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.

Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link.

Abstract: A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.

Abstract: To provide a super high-speed heterojunction bipolar transistor, a semiconductor device including such a heterojunction bipolar transistor has a structure wherein a subcollector layer, collector layer, base layer, emitter layer (InGaP layer) and emitter cap layer are successively formed in predetermined shapes a surface of a semi-insulating GaAs substrate, an inner edge part of a base electrode overlaps a periphery of the emitter layer, and the base electrode is electrically connected to the base layer by an alloy layer formed by alloying the emitter layer under the base electrode. The emitter layer is selectively formed on the base layer. The base electrode extends from the peripheral part of the emitter layer across the base layer, and the alloy layer extends to a midway depth of the base layer. The edge of the base layer is situated further inside than the outer edge of the base electrode.

Abstract: A defect removable semiconductor element and the manufacturing method thereof are provided with a protective layer covering fuses exposed at a part of the redundancy memory cell region, the layer being thinner than the one covering the main memory cell region, so that a predetermined fuse is cut off for removing a defect without damaging adjacent fuses even if the amount of energy of laser beam to be applied is greater and the size of the spot to be focused is bigger, thereby improving operational conditions in the energy of the laser beam to be applied and the size of a spot to be focused and the operational reliability in removing a defect.

Abstract: A substrate having at least one fuse in a fuse layer. An upper etch-stop layer over the fuse, a lower etch-stop layer having a different etch-chemistry over the fuse and, optionally, a diffusion barrier layer immediately over the fuse. The lower etch-stop later and the optional diffusion barrier providing a uniform passivation thickness for use in conjunction with laser fuse deletion processes. An upper etch-resistant layer over the lower etch-resistant layer and having an etch chemistry selective to that of the lower etch-resistant layer. Methods for providing a uniform passivation thickness over all the fuses, and for deleting such fuses.

Abstract: A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low k nanopore/nanofoam dielectric material adjacent the conductive line ends.

Abstract: A method of forming metal fuses. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.

Abstract: An integrated circuit fuse is formed on a substrate by etching a polysilicon, metal or alloy layer deposited thereon to include a central region, at the end of which are zones with electrical contacts. The central region has at least two first electrically parallel arms. A zone of intersection of the first two arms forms a point for focusing a fusing current which facilitates the fusing of the fuse by increasing local current density flowing through the integrated circuit.

Abstract: A fuse for semiconductor devices, in accordance with the present invention, includes a cathode formed from a first material, an anode formed from a second material and a fuse link connecting the cathode and the anode and formed from the second material. The second material is more susceptible to material migration than the first material when the fuse is electrically active such that material migration is enhanced in the second material.

Abstract: An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.

Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer.

Abstract: In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap subsequent to blowing the fuse by an energizing laser, the fuse comprising:

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Abstract: There is described a semiconductor device having a copper fuse which prevents damage to a silicon substrate beneath the copper fuse, which would otherwise be caused by a laser beam radiated to blow the copper fuse. A light absorbing layer is formed on the copper fuse layer from material whose light absorption coefficient is greater than that of a copper wiring layer. Light absorbed by the light absorbing layer is transmitted, through heat conduction, to the copper wiring layer beneath the light absorbing layer and further to a barrier metal layer beneath the copper wiring layer. Even when the widely-used conventional laser beam of infrared wavelength is used, the copper fuse can be blown. Since a guard layer is formed below the fuse layer, there can be prevented damage to the silicon substrate, which would otherwise be caused by exposure to the laser beam of visible wavelength.

Abstract: In the fuse element structure of the semiconductor device, the first insulating film region is provided in a groove-like manner in the semiconductor substrate. Further, the fuse element is formed on the first insulating film region, and the second insulating film region is formed on the region on the fuse element and the first insulating film. The metal plug is connected to the fuse element, and the surface thereof is exposed to the surface of the second insulating film region. With this structure, the meltdown of the fuse by the laser blow is facilitated, and the area of the fuse is reduced. Thus, as the downsizing of the element is further advanced, it is possible to provide a fuse element structure capable of melting down a fuse without causing an affect on another fuse adjacent to the melted-down fuse with the scattering pieces thereof.

Abstract: A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.

Abstract: A defect removable semiconductor element and the manufacturing method thereof are provided with a protective layer covering fuses exposed at a part of the redundancy memory cell region, the layer being thinner than the one covering the main memory cell region, so that a predetermined fuse is cut off for removing a defect without damaging adjacent fuses even if the amount of energy of laser beam to be applied is greater and the size of the spot to be focused is bigger, thereby improving operational conditions in the energy of the laser beam to be applied and the size of a spot to be focused and the operational reliability in removing a defect.

Abstract: A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor and an antenna. The protection transistor is connected between a metal line having devices to be protected electrically connected thereto and a ground supply, where the metal line is connected to devices to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna is connected to a gate of the protection transistor. Optionally, there is a metal ring around the antenna which is connected to a drain of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off.

Abstract: A structure and method for making a cavity fuse over a gate conductor stack.

Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.

Abstract: A method of forming a grooved fuse (plug fuse) in the same step that via plugs are formed in the guard ring area 14 and in product device areas. A key point of the invention is to form fuses from the via plug layer, not from the metal layers. Also, key guard rings are formed around the plug guise. The invention can include the following: a semiconductor structure is provided having a fuse area, a guard ring area surrounding the fuse area; and a device area. First and second conductive strips are formed. First and second insulating layers are formed over the first and second conductive strips. Plug contacts and fuse plugs are formed through the first and second insulating layers to the first and second conductive strips. A third insulating layer is formed over the second insulating layer. Metal lines are formed over the third insulating layer in the device area. A fuse via opening is formed in the third insulating layer. A plug fuse is formed in the fuse via opening.

Abstract: An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC substrate with the electrical traces extending from an IC chip mounting area near the center to the periphery of the IC substrate. Electrically shorting the electrical traces together with a conductive material such as conductive tape or epoxy, thereby, protecting the IC substrate against the accumulation of static charges during the assembly of the IC chip on the IC substrate. The IC chip is mounted in the mounting area on the IC substrate and the conductive material is removed before final testing.

Abstract: A semiconductor device (10) is formed to have multiple external connection pads (17, 18) for an active element (12). The multiple external connection pads (17, 18) are electrically connected together with a electrical link (19). After testing, the electrical link (19) is removed to disconnect the multiple external connection pads (17, 18) from each other.

Abstract: The present invention provides a structure and method for forming a moisture barrier guard ring structure 38 44 48 52 54 for around a fuse window 30 in a semiconductor device. The invention begins by forming a fuse structure 32 33 34 over the isolation regions cross the fuse window area. A cap layer 38 and an interlevel dielectric layer (ILD) 40 are formed over the fuse structure. A first annular ring 44 (e.g., contact w-plug) is formed over the isolation region 20 surrounding the fuse window area 30 and over the fuse structure 32 33 34. A key feature is that the first annular ring 44 and the cap layer 38 form a moisture proof seal over the fuse structure. A first conductive wiring line 48 is formed over the first annular ring 44. Next, an inter metal dielectric (IMD) layer 50 is formed over the interlevel dielectric layer 40. A second annular ring 52 is formed through the inter metal dielectric layer 50 on the first conductive wiring line 48.

Abstract: A method for forming a semiconductor device is disclosed. The method comprises the step of irradiating a laser light to a surface of a semiconductor through a mask provided on said surface in an atmosphere comprising an impurity of one conductivity type to diffuse said impurity into a region of said semiconductor.

Abstract: Methods of forming semiconductor active regions having channel-stop regions therein include the steps of forming an oxide layer and first nitride layer on a face of a semiconductor substrate and then patterning the first nitride layer to expose first portions of the oxide layer. The patterned first nitride layer is then used as a mask during implantation of dopants of second conductivity type into the substrate. A second nitride layer is then deposited on the exposed first portions of the oxide layer and on the first nitride layer. A second photoresist layer is then patterned and used as a mask to etch the second nitride layer and patterned first nitride layer, to expose second portions of the oxide layer. A third photoresist layer is then patterned to cover the first portions of the oxide layer. The patterned third photoresist layer and remaining portions of the patterned first and second nitride layers are then used as implant masks during implantation of second conductivity type dopants.

Abstract: An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.