Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.

Abstract: The present invention relates to a high performance heterojunction bipolar transistor (HBT) having a base region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 nm thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content. The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.

Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.

Abstract: A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate having a first semiconductive body and a second plate having a floating electrode. The first and second semiconductive bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.

Abstract: A method for forming an interface free layer of silicon on a substrate of monocrystalline silicon is provided. According to the method, a substrate of monocrystalline silicon having a surface substantially free of oxide is provided. A silicon layer in-situ doped is deposited on the surface of the substrate in an oxygen-free environment and at a temperature below 700° C. so as to produce a monocrystalline portion of the silicon layer adjacent to the substrate and a polycrystalline portion of the silicon layer spaced apart from the substrate. The silicon layer is heated so as to grow the monocrystalline portion of the silicon layer through a part of the polycrystalline portion of the silicon layer. Also provided is a method for manufacturing a bipolar transistor.

Abstract: A data carrier for noncontacting control of persons with nontransferable entitlement to utilize a service is integrated into a bracelet (1) so as to be useless after the bracelet (1) is opened.

Abstract: A low thermal budget transistor is fabricated by first forming a gate on a semiconductor substrate. First amorphous regions and first inactive dopant regions are then created in the substrate by ion implantation. Sidewall spacers, which align subsequent implantation steps, are formed adjacent to the gate. Thereafter, second amorphous regions and second inactive dopant regions are created in the substrate by ion implantation. Dopants in the first and second inactive dopant regions are then activated using a low temperature annealing process to create source/drain regions and source/drain extension regions. The aforementioned process simplifies the fabrication of a low thermal budget transistor by dispensing with the requirement to remove the sidewall spacers.

Abstract: The present invention relates to a method of forming a bipolar transistor or a heterojunction bipolar transistor. The method comprises forming a collector region associated with a semiconductor substrate, and forming a base region base region over at least a portion of the collector region. The method further comprises forming a diffusion blocking layer over the base region, and forming an emitter polysilicon region over the diffusion blocking layer. The diffusion blocking layer reduces an amount of diffusion from the emitter polysilicon region into the base region, thereby allowing improved process control and emitter/base doping profile, leading to improved transistor performance. In addition, the present invention relates to a heterojunction bipolar transistor, and comprises a collector region, and a graded profile SiGe base layer overlying the collector region.

Abstract: Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching speed and current gain of bipolar transistors. Current fabrication techniques involve high temperature procedures that melt desirable low-resistance substitutes, such as aluminum, during fabrication. Accordingly, one embodiment of the invention provides an emitter contact structure that includes a polysilicon-carbide layer and a low-resistance aluminum, gold, or silver member to reduce emitter resistance. Moreover, to overcome manufacturing difficulties, the inventors employ a metal-substitution technique, which entails formation of a polysilicon emitter, and then substitution of metal for the polysilicon.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.

Abstract: A method for producing a semiconductor device including a bipolar transistor, has the steps of: forming an element isolating region in a major surface of a semiconductor substrate to define an element forming region to form a collector region in the element forming region surrounded by the element isolating region; allowing the epitaxial growth of a semiconductor layer on the major surface of the semiconductor substrate to form a base region of the semiconductor layer on the collector region; forming a growth inhibiting film on a region forming the base region of the semiconductor layer; removing the growth inhibiting film to expose a part of the semiconductor layer; covering the upper surface and side wall of the conductive film, which is exposed in the predetermined region, with an insulator film; covering the side wall of the conductive film, which is exposed in the predetermined region; and forming an emitter region in a surface region of the predetermined region of the semiconductor layer, which is surro

Abstract: A very thin coating layer having a thickness of the order of 1-100 angstroms of a hydroxymethyl substituted phenol is applied to the surface of a metal material. The hydroxylmethyl substituted phenol, such as saligenin, is applied in the gaseous phase to the surface of the metal material maintained at a high temperature.By forming this ultra-thin coating layer, the heat bondability of a thermoplastic resin layer to the metal material can be effectively improved. This technique is advantageously used in various fields, for example, for production of bonded cans. The metal material comprises a steel plate substrate and a chromium-containing layer on the surface of the substrate, and the very thin layer is applied on the chromium-containing layer.