Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process.

Abstract: Within both a method for fabricating a bipolar transistor device and a method for fabricating a BiCMOS device there is: (1) formed contacting a base contact region a polysilicon base contact of a second polarity; and (2) formed contacting an emitter contact region a polysilicon emitter contact of a first polarity. Within the methods, there is then implanted into the polysilicon base contact a dose of a dopant of the second polarity while masking the polysilicon emitter contact. The methods provide for enhanced performance of the bipolar transistor device and the BiCMOS device.

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

Abstract: In the fabrication of a transistor device, particularly a low-voltage high-frequency transistor for use in mobile telecommunications, a method for improving the transistor performance and the high-frequency characteristics of the device is described. The method includes providing a semiconductor substrate (1) with an n-doped collector layer (5) surrounded by isolation areas (4), implanting antimony ions into the collector layer such that a thin highly n-doped layer (18) is formed in the uppermost portion of the collector layer, and forming a base on top of said thin highly n-doped layer (18).

Abstract: A method is described for forming a high gain bipolar junction transistor in a optimized CMOS integrated circuit. The bipolar junction transistor comprises a compensated base region (130) which is formed by forming the p-well region (20) and the n-well region (30) in a common substrate region.

Abstract: A method for forming a self-aligned bipolar transistor includes the steps of combination etching a silicon substrate in an opening to form a concave surface on the silicon substrate, and forming an intrinsic base and an associated emitter on the concave surface. The combination etching includes an isotropic etching and subsequent wet etching. The concave surface increases the distance between the external base for the intrinsic base and the emitter to thereby increase the emitter-base breakdown voltage.

Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.

Abstract: A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an opening; annealing to form a third thin oxide layer and harden the second oxide layer; implanting a P-type dopant; depositing a fourth silicon nitride layer; depositing a fifth silicon oxide layer and etching it; anisotropically etching the fifth, fourth, and third layers; performing cleanings during which the fifth layer is reetched and takes a flared profile; depositing a sixth polysilicon layer; and implanting an N-type dopant.

Abstract: A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a bass region; a lower portion of the second semiconductor region which at least fills th

Abstract: A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Gecontent is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

Abstract: The present invention provides a method of manufacturing a bipolar transistor. The method includes producing an opening in a dielectric layer located over a substrate and forming a collector in the substrate by implanting a first dopant through the opening. The method further includes creating an intrinsic base region contacting the collector and constructing an emitter contacting the intrinsic base region, both of which are through the opening.

Abstract: A method of forming an NPN semiconductor device includes the steps of forming a collector region within a substrate, forming a base region over the collector region, and forming an oxide-nitride-oxide stack over the base region. Once these three structures are formed, an opening is created through the oxide-nitride-oxide stack to expose the top surface of the base region. Then, a doped polysilicon material is used to fill the opening and make electrical contact to the base region. The use of the oxide-nitride-oxide stack with appropriate etching of the opening eliminates the exposure of the base region to reactive ion etch environment typical of prior art methods for forming NPN semiconductor devices. As an option, after the opening of the oxide-nitride-oxide stack is formed, a local oxidation of silicon (LOCOS) and etched can be preformed to create oxide spacers to line the opening wall above the base region.

Abstract: In producing a thin film transistor, after an amorphous silicon film is formed on a substrate, a nickel silicide layer is formed by spin coating with a solution (nickel acetate solution) containing nickel as the metal element which accelerates (promotes) the crystallization of silicon and by heat treating. The nickel silicide layer is selectively patterned to form island-like nickel silicide layer. The amorphous silicon film is patterned. A laser light is irradiated while moving the laser, so that crystal growth occurs from the region in which the nickel silicide layer is formed and a region equivalent to a single crystal (a monodomain region) is obtained.

Abstract: A method of manufacturing a hetero-junction bipolar transistor including a carbon-doped base layer includes the steps of (a) growing a base layer on an underlying layer through chemical vapor deposition, (b) forming at least one semiconductor layer over the base layer, and (c) then subjecting the base layer to thermal annealing at a temperature of 520° C. to 650° C.

Abstract: A semiconductor rectifying device which emulates the characteristics of a low forward voltage drop Schottky diode and which is capable of a variety of electrical characteristics from less than 1 A to greater than 1000 A current with adjustable breakdown voltage. The manufacturing process provides for uniformity and controllability of operating parameters, high yield, and readily variable device sizes. The device includes a semiconductor body with a guard ring on one surface to define a device region in which are optionally formed a plurality of conductive plugs. Between the guard ring and the conductive plugs are a plurality of source/drain, gate and channel elements which function with the underlying substrate in forming a MOS transistor.

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

Abstract: A semiconductor device including a bipolar transistor formed by epitaxial growth or ion implantation is provided has an epitaxial silicon collector layer, a base region directly under an emitter defined as an intrinsic base and a peripheral region thereof defined as an outer base region is formed by the step of implanting ions into the collector layer to form a high concentration collector region at a location close to a buried region using a photoresist to form an aperture, and the step of implanting ions into the collector layer to form a high concentration collector region directly beneath the base region after forming the base region.

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via multiple ion implantation procedures, performed through, and self-aligned to, an overlying emitter opening, in an oxide layer. The self-aligned collector regions, completely fill the space in the lighter doped collector region, located between the overlying base region, and the underlying subcollector region.

Abstract: A power rectifier having low on resistance, mass recovery times and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common metallization. This provides a low Vf path through the channel regions of the MOSFET cells to the source region on the other side of the integrated circuit. A thin gate structure is formed annularly around the pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and Vf. A parallel Schottky diode is also provided which increases the switching speed of the MOSFET cells.

Abstract: The manufacturing of a bipolar transistor, including the steps of depositing a P-type polysilicon layer and an insulating layer on an N-type substrate; defining in said layers a base-emitter opening; performing a P-type doping and annealing to form a heavily-doped region partially extending under the periphery of the polysilicon layer; forming a spacer in an insulating material inside the opening; isotropically etching the silicon across a thickness greater than that of the heavily-doped region to form a recess; conformally forming by selective epitaxy a P-type silicon layer to form the transistor base layer; and depositing N-type heavily-doped polysilicon to form the transistor emitter.

Abstract: The present invention relates to a method for semiconductor manufacturing of one semiconductor circuit, having a multiple of transistors NMOS1, NMOS2, NPN1, NPN2 of one type. The method comprises the steps of arranging a first region 4, 16 on a semiconductor substrate 1, and implementing two transistors of said type, having different sets of characteristics, in said first region 4, 16. The step of implementing said active devices comprises a step of creating a first 6′, 10′ and a second 6″, 10″ subregion within said first region 4, 16, and said step further comprising a step of introducing dopants having different sets of dose parameters, into a first and a second area, respectively, of said first region, said dopants being of a similar type, and a step of annealing said substrate 1 to create said first 6′, 10′ and second 6″, 10″ subregion, respectively, whereby two subregions, having different doping profiles, can be manufactured on a single integrated circuit.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device)d a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.

Abstract: A method of manufacturing a hetero-junction bipolar transistor including a carbon-doped base layer includes the steps of (a) growing a base layer on an underlying layer through chemical vapor deposition, (b) forming at least one semiconductor layer over the base layer, and (c) then subjecting the base layer to thermal annealing at a temperature of 520° C. to 650° C.

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: Methods of forming bipolar junction transistors having preferred base electrode extensions include the steps of forming a base electrode of second conductivity type (e.g., P-type) on a face of a substrate. A conductive base electrode extension layer is then formed in contact with a sidewall of the base electrode. The base electrode extension layer may be doped or undoped. An electrically insulating base electrode spacer is then formed on the conductive base electrode extension layer, opposite the sidewall of the base electrode. The conductive base electrode extension layer is then etched to define a L-shaped base electrode extension, using the base electrode spacer as an etching mask. Dopants of second conductivity type are then diffused from the base electrode, through the base electrode extension and into the substrate to define an extrinsic base region therein.

Abstract: A circuit protects against electrostatic discharge and includes a pad which receives an external signal source. The transistor of the present invention is connected to the circuit to be protected and includes a semiconductor body of a first conductivity type and serves as the collector of the transistor and is connected to the pad. A first doped region of a second conductivity type is contained in the semiconductor body and serves as the base of the transistor and forms a collector-to-base junction surface with the semiconductor body. A second doped region of the first conductivity type is contained in the first doped region and serves as the emitter of the transistor and forms a base-to-emitter junction surface with the first doped region. The first and second doped regions are electrically connected for establishing a shorted connection between the base and emitter.

Abstract: A process is set forth for providing a self-aligned, vertical bipolar transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency microwave applications. A microwave transistor is provided by this technique.

Abstract: A photoresist pattern is formed on a field oxide film and an element forming region across the field oxide film and the element forming region such that a portion of a surface of the field oxide film and a portion of a surface of a silicon epitaxial layer are continuously exposed. The photoresist pattern is used as a mask to inject boron ions into the silicon epitaxial layer and heat treatment is performed thereon to form an external base containing the relatively significant crystal defect present in the silicon epitaxial layer in the vicinity of the field oxide film. Thus, a semiconductor device can be obtained including a bipolar transistor which provides improved breakdown voltage between the collector and the base and contemplates reduction of current leakage.

Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.

Abstract: A process for fabricating a bipolar junction transistor, (BJT), featuring reduced junction capacitance, resulting from the decreased dimensions of extrinsic, and intrinsic base, regions, has been developed. The BJT device, is comprised with only a single polysilicon level, used for the emitter structure, while an extrinsic base, and intrinsic base region, are accommodated in an epitaxial silicon layer, grown on an underlying silicon, active device region, and grown on a silicon seed layer, which in turn overlays insulator isolation regions. A boron doped, intrinsic base region can be formed in an undoped version of the epitaxial silicon layer, or the boron doped, intrinsic base region can be contained in the as deposited, epitaxial silicon layer, or contained in an as deposited, epitaxial, silicon-germanium layer.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: The present invention relates to a bipolar transistor of NPN type implemented in an epitaxial layer within a window defined in a thick oxide layer, including an opening formed substantially at the center of the window, this opening penetrating into the epitaxial layer down to a depth of at least the order of magnitude of the thick oxide layer, an N-type doped region at the bottom of the opening, a first P-type doped region at the bottom of the opening, a second lightly-doped P-type region on the sides of the opening, and a third highly-doped P-type region in the vicinity of the upper part of the opening, the three P-type regions being contiguous and forming the base of the transistor.

Abstract: The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.

Abstract: A method for producing a semiconductor device including a bipolar transistor, has the steps of: forming an element isolating region in a major surface of a semiconductor substrate to define an element forming region to form a collector region in the element forming region surrounded by the element isolating region; allowing the epitaxial growth of a semiconductor layer on the major surface of the semiconductor substrate to form a base region of the semiconductor layer on the collector region; forming a growth inhibiting film on a region forming the base region of the semiconductor layer; removing the growth inhibiting film to expose a part of the semiconductor layer; covering the upper surface and side wall of the conductive film, which is exposed in the predetermined region, with an insulator film; covering the side wall of the conductive film, which is exposed in the predetermined region; and forming an emitter region in a surface region of the predetermined region of the semiconductor layer, which is surro

Abstract: A method for forming a polycide/oxide/polysilicon capacitor on a silicon wafer with improved dielectric stability and reliability is described wherein an in-situ high temperature anneal is applied to the wafer within a CVD reactor immediately prior to the deposition of the silicon oxide capacitor dielectric layer. The in-situ anneal causes sufficient fluorine outgassing of the polycide layer to prevent fluorine degradation of the subsequently deposited oxide capacitor dielectric. The capacitance of the completed capacitor is increased by as much as 10% when compared to a comparable not in-situ anneal conducted prior to the insertion of the wafer into the CVD reactor.

Abstract: A BiCMOS integrated circuit with Nwell compensation implants and a method for fabricating the same is disclosed. In accordance with the method of fabricating a BiCMOS integrated circuit, a plurality of Nwell regions are created in a semiconductor substrate. At least some of the Nwell regions comprise lightly doped collector regions of bipolar transistors while others of the Nwell regions comprise Nwell regions of MOS transistors. A plurality of isolation regions are created to electrically isolate at least some of the Nwell regions. A p-type dopant is implanted in at least some of the lightly doped collector regions of the bipolar transistors.

Abstract: In a method for manufacturing a bipolar transistor, a first insulating layer, a first polycrystalline silicon layer of a second conductivity type, and a second insulating layer are sequentially formed on a semiconductor substrate of a first conductivity type. Then, the second insulating layer and the first polycrystalline silicon layer are patterned to form an opening therein. Then, the first insulating layer is over etched by using the second insulating layer and the first polycrystalline silicon layer as a mask. Then, a second polycrystalline silicon layer is formed on the entire surface. Then, an oxidizing process is performed upon the second polycrystalline silicon layer except for a part of the second polycrystalline silicon layer under the first polycrystalline silicon layer, and the oxidized part of the second polycrystalline silicon layer is removed by a wet etching process. Then, impurities of the second conductivity type are implanted into the semiconductor substrate to form a base region.

Abstract: A BiCMOS process where a base region is formed in a relatively highly doped n-type substrate region. Boron is implanted at two different energy levels to form the base region and a counter doped n region near the base collector junction to prevent impact ionization.

Abstract: The invention relates to a method of manufacturing a discrete or integrated bipolar transistor comprising a base (1A), an emitter (2) and a collector (3). The base (1A) and a connecting region (1B) of the base (1A) are formed by providing a semiconductor body (10) with a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body which forms the collector (3). Outside said base, the layer (1) borders on a non-monocrystalline part (4) of the semiconductor body (10) and forms a non-monocrystalline connecting region (1B) of the base (1A). By means of a mask (5), the doping concentration of the layer (1) outside the mask (5) is selectively increased, resulting in a highly conducting connection region (1B) and a very fast transistor. In the known method, an ion implantation is used for this purpose.

Abstract: A method of manufacturing a bipolar transistor having a self-registered base-emitter structure is provided.

Abstract: Methods of forming bipolar junction transistors having preferred base electrode extensions include the steps of forming a base electrode of second conductivity type (e.g., P-type) on a face of a substrate. A conductive base electrode extension layer is then formed in contact with a sidewall of the base electrode. The base electrode extension layer may be doped or undoped. An electrically insulating base electrode spacer is then formed on the conductive base electrode extension layer, opposite the sidewall of the base electrode. The conductive base electrode extension layer is then etched to define a L-shaped base electrode extension, using the base electrode spacer as an etching mask. Dopants of second conductivity type are then diffused from the base electrode, through the base electrode extension and into the substrate to define an extrinsic base region therein.

Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.

Abstract: An improved method and an apparatus for forming a self-aligned epitaxial base bipolar transistor in a semiconductor material is disclosed. The method of the invention involves forming an intrinsic base region formed by growing an epitaxial semiconductor material over a collector region. A raised sacrificial emitter core is then formed on the intrinsic base region followed by depositing a substantially conformal spacer layer over the sacrificial emitter core. Next, the spacer material is anisotropically etched such that a protective spacer ring is formed about the sacrificial emitter core. An extrinsic base is then formed by implanting dopant into the epitaxial base region wherein the sacrificial emitter core and the spacer ring preserve an emitter region. The spacer ring also serves to self-align the extrinsic base region to the emitter region. The protective sacrificial emitter core and spacer ring are then removed.

Abstract: Disclosed is a method for the fabrication of an extrinsic base of an NPN transistor using high frequency bipolar technology. According to the method, using a doping of the extrinsic base of the transistor by ion implantation, the amorphous crystal lattice is recrystallized by very high-speed thermal annealing before the dopants of the extrinsic base are diffused in the epitaxial layer.

Abstract: A process for forming a structure of a high-frequency bipolar transistor on a layer of a semiconductor material with conductivity of a first type. The process includes forming a first shallow base region by implantation along a selected direction of implantation and using a dopant with a second type of conductivity. The region extends from a first surface of the semiconductor material layer and encloses, toward said first surface, an emitter region with conductivity of the first type. In accordance with the invention, the implantation step includes at least one process phase at which the direction of implantation is maintained at a predetermined angle significantly greatly than zero degrees from the direction of a normal line to said first surface. Preferably, the implantation angle is of about 45 degrees.

Abstract: In fabricating a bipolar transistor, semiconductor dopant is introduced into a semiconductor body during a base doping operation to define a doped region, that forms a PN junction with adjoining semiconductor material and abuts a slanted sidewall of a field insulating region. The doped region constitutes a base region for the transistor. The base doping operation entails ion implanting the dopant into the body at a tilt angle of at least 15.degree. relative to the vertical. The minimum lateral base thickness and, the minimum sidewall base thickness increase relative to the minimum vertical base thickness. As a result, the magnitude of the collector-to-emitter breakdown voltage typically increases. The minimum lateral, sidewall, and vertical base thicknesses vary with the tilt angle and base-implant energy in such a manner that the minimum lateral base thickness and the minimum sidewall base thickness are separately controllable from the minimum vertical base thickness.

Abstract: A bipolar junction transistor structure and method of forming the bipolar junction transistor structure comprising an intrinsic base surrounded by a base link and an extrinsic base surrounding the base link. An emitter is formed above the base. The extrinsic base, base link, and intrinsic base are formed using ion implantation. A single layer of doped polysilicon is used to provide the doping source for the emitter and a collector contact. Silicide contacts to the emitter, collector, or base are not required or used.

Abstract: A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.