Abstract: Provided are a semiconductor device including a desired snubber part in accordance with use of the semiconductor device and a method of manufacturing the semiconductor device. A snubber region having a snubber part is defined in a gate pad region defined on a side close to a first main surface of a semiconductor substrate. A p-type diffusion layer and an n-type column layer contacted to each other are formed in the snubber region. The p-type diffusion layer and the n-type column layer are formed as a parasitic capacitance of the snubber part while the n-type column layer is electrically coupled to a drain. The p-type diffusion layer, which extends in a Y-axis direction, is a resistance of the snubber part and electrically coupled to a source.

Abstract: An adhesive for adhering a protective film, the protective film having a water vapor transmission rate of about 100 g/m2·day or less at 40° C. and about 90% RH during manufacture of an optical member including a polarizing plate, a polarizing plate including an adhesive layer prepared from the adhesive, and an optical member including the polarizing plate, the adhesive including a (meth)acrylic copolymer, the (meth)acrylic copolymer having a weight average molecular weight of about 800,000 g/mol or more; a curing agent; and a silane coupling agent, wherein an adhesive layer prepared from the adhesive has a storage modulus, after curing, of about 8×103 Pa or more at about 85° C. and a frequency of about 10?3 rad/s to about 102 rad/s.

Abstract: The present invention relates to a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material layer, a first pressure-sensitive adhesive layer and a second pressure-sensitive adhesive layer stacked in this order, and a film for semiconductor back surface stacked on the second pressure-sensitive adhesive layer of the dicing tape, in which a peel strength Y between the first pressure-sensitive adhesive layer and the second pressure-sensitive adhesive layer is larger than a peel strength X between the second pressure-sensitive adhesive layer and the film for semiconductor back surface, and in which the peel strength X is from 0.01 to 0.2 N/20 mm, and the peel strength Y is from 0.2 to 10 N/20 mm.

Abstract: The present invention relates to a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material layer, a first pressure-sensitive adhesive layer and a second pressure-sensitive adhesive layer stacked in this order, and a film for semiconductor back surface stacked on the second pressure-sensitive adhesive layer of the dicing tape, in which a peel strength Y between the first pressure-sensitive adhesive layer and the second pressure-sensitive adhesive layer is larger than a peel strength X between the second pressure-sensitive adhesive layer and the film for semiconductor back surface, and in which the peel strength X is from 0.01 to 0.2 N/20 mm, and the peel strength Y is from 0.2 to 10 N/20 mm.

Abstract: An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in contact with a doped tank region located underneath a contacting sinker. The second bipolar transistor structure has a doped buried region that is the same dopant type as its doped tank region. A method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer. A first patterned photomask is used to form a doped buried region and a doped tank region within the first bipolar transistor structure. A second patterned photomask is used to form a doped buried region and a doped tank region within the second bipolar transistor, plus a doped buried region and a doped tank region underneath a contacting sinker adjacent to the first bipolar transistor.

Abstract: In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.

Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.

Abstract: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

Abstract: Antimony-based semiconductor devices are formed over a substrate structure (10) that includes an antimony-based buffer layer (24) and an antimony-based buffer cap (26). Multiple epitaxial layers (30–42) formed over the substrate structure (10) are dry etched to form device mesas (12) and the buffer cap (26) provides a desirably smooth mesa floor and electrical isolation around the mesas.

Abstract: A method for enhancing operation of a bipolar light-emitting transistor includes the following steps: providing a bipolar light-emitting transistor having emitter, base, and collector regions; providing electrodes for coupling electrical signals with the emitter, base, and collector regions; and adapting the base region to promote carrier transport from the emitter region toward the collector region by providing, in the base region, several spaced apart quantum size regions of different thicknesses, with the thicknesses of the quantum size regions being graded from thickest near the collector to thinnest near the emitter.

Abstract: A method of fabricating a high performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used. In the preferred embodiment, this is of the Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) type, although other Anti-Reflective Coatings (ARCs) or layers, such as a conductive film like TiN may be employed. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. In one embodiment, a Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.

Abstract: In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.

Abstract: The present invention provides a method of manufacturing semiconductor devices, by which InGaAs-base C-top HBTs are manufactured at low cost. Helium ions with a smaller radius are implanted into a p-type InGaAs layer (in external base regions) not covered with a lamination consisting of an undoped InGaAs spacer layer, n-type InP collector layer, n-type InGaAs cap layer, and collector electrode from a direction vertical to the surface of the external base layer or within an angle of 3 degrees off the vertical. In consequence, the p-type InGaAs in the external base regions remains p-type conductive and low resistive and the n-type InAlAs layer in the external emitter regions can be made highly resistive. By this method, InGaAs-base C-top HBTs can be fabricated on a smaller chip at low cost without increase of the number of processes.

Abstract: The pressure-sensitive adhesive sheet for surface protection has a three-layered film formed by laminating a layer A, a layer B and a layer C in this order and a pressure-sensitive adhesive layer formed on the layer C; wherein the layer A contains a polyethylene in an amount of at least 60% by weight based on a total weight of the layer A; the layer B contains a polypropylene type polymer in an amount of at least 50% by weight of based on a total weight of the layer B; and the layer C contains a hydrogenated styrene/diene type hydrocarbon copolymer in an amount of at least 10% by weight based on the total weight of the layer C. This sheet has excellent weathering resistance to undergo neither chalking nor fracture in the substrate at peeling, even after a prolonged outdoor exposure, develops less corona odor to enable extended operation of applying it, and can be manufactured inexpensively with reduced manufacturing process, since no anchor coat treating procedure is required.

Abstract: In a method for fabricating a semiconductor device, a silicide material is formed at least on the surface of an area to be silicided. Then, a first RTA (Rapid Thermal Annealing) process is performed to form a first-reacted silicide region. Next, a supplemental silicon layer is formed over the entire surface; and a second RTA process is performed to form a second-reacted suicide region.

Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

Abstract: Disclosed is a semiconductor device including a SOI substrate having a SOI layer, in which a structure made from a semiconductor device is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidation preventive film formed both on the SOI layer and on a region in which a contact reaching the structure is to be formed; an interlayer dielectric film formed on the structure, the SOI layer and the thick oxide film; and a plurality of connection holes formed in the interlayer dielectric film and including at least a connection hole positioned on the region in which the contact is to be formed. With this semiconductor device, a contact reaching a back gate electrode can be formed without increasing an aspect ratio of the contact even when a thick oxide film is grown on the back gate electrode in the filed area by selectively oxidizing the back gate electrode in the field area.

Abstract: Disclosed is a method for manufacturing a hetero junction bipolar transistor capable of forming a ledge by using a low-priced contact aligner and in a selective wet etching manner, without having any expensive stepper and dry etching and forming a ballasting resistor, without having an additional NiCr thin film, whereby the manufacturing processes thereof can be embodied in simple and easy manners, thereby improving productivity and an economical efficiency.

Abstract: A bipolar transistor includes an oxide layer having graded portions with greatly reduced stress on a silicon substrate. The method of making the oxide preferably includes growing a first oxide portion by upwardly ramping the silicon substrate to a first temperature lower than a glass transition temperature, and exposing the silicon substrate to an oxidizing ambient at the first temperature and for a first time period. Also, the method includes growing a second oxide portion between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period. The second oxide portion may have a thickness in a range of about 2 to 75% of a total thickness of the graded, grown, oxide layer. The step of upwardly ramping preferably includes upwardly ramping the temperature at a relatively high ramping rate to reduce any oxide formed during the upward ramping.

Abstract: A trench isolation structure characterized by a dielectric stud filling and spanning a trench in a semiconductor substrate is suggested for isolating the integrated circuits fabricated in the semiconductor substrate. The dielectric stud is formed by depositing isolating material in a space defined by the trench and a dielectric layer overlying the semiconductor substrate and being partially removed over an area which spans the trench and extends over the lengthwise edges of the trench.

Abstract: A method for fabricating a thin film transistor includes the steps of forming an active layer on a substrate, forming a metal gate electrode on the active layer, depositing a silicon layer on the metal gate electrode and the active layer, causing the metal gate electrode to react with the silicon layer to form a silicide layer around the metal gate electrode, removing the silicon layer, heavily doping impurities in the active layer using the silicide layer as a mask to form a source/drain region, removing the silicide layer, and lightly doping impurities in the active layer using the metal gate electrode as a mask to form an offset region.

Abstract: A multiple crown capacitor and a method of fabricating such a capacitor is described. The method is applicable to a substrate in which an isolation layer is formed on the substrate, with a node contact plug formed in the isolation layer. A sacrificial layer is then formed on the substrate followed by a patterning of the sacrificial layer to form a succession of openings above the node contact plug and its surroundings, exposing the isolation layer and a portion of the node contact plug upper surface. Thereafter, a conformal conductive layer is formed on the sacrificial layer and in the openings. A portion of the conductive layer, which is higher than the sacrificial layer, is removed, followed by removing the sacrificial layer to form a bottom electrode. A conformal dielectric layer and an upper electrode are sequentially formed on the bottom electrode to complete the formation of the capacitor.