Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An ESD protection device (20) comprises an N-type epitaxial collector (21), a first, lightly doped, deep base region (221) and second, highly doped, shallow base region (222) that extends a predetermined lateral dimension. The device responds to an ESD event by effecting vertical breakdown between the base regions and the N-type epitaxial collector. The ESD response is controlled by the predetermined lateral dimension, S, which, in one embodiment, may be is determined by a single masking step. Consequently, operation of the ESD protection device is rendered relatively insensitive to the tolerances of a fabrication process, and to variations between processes.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and’ a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into to the portion of a semiconductor substrate along the side wall of trench, impurity ions are irradiated in parallel to the side wall of trench to implant the impurity ions only into to the portion of semiconductor substrate beneath the bottom wall of trench; the substrate is heated to drive the implanted impurity ions to form an offset drain region around trench and to thermally oxidize semiconductor substrate to fill the trench 2 with an oxide. Alternatively, the semiconductor substrate is oxidized to narrow trench with oxide films leaving a narrow trench and the narrow trench left is filled with an oxide.

Abstract: The present invention provides a highly doped semiconductor layer.

Abstract: A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.

Abstract: A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.

Abstract: A CMOS device (10) having p-channel and n-channel transistors with aluminum implanted gates (20). When making the device (10), aluminum is non-selectively implanted to form a source and drain for the n-channel transistor and to reduce the resistivity of the gates (20). The aluminum diffuses through an upper polysilicon layer (22) of the gate, thereby reducing its resistivity, but does not diffuse through a lower oxide layer (24) of the gate, thereby preventing penetration problems. Thereafter, a compensating implant (e.g., phosphorus or arsenic) is selectively implanted to overcompensate the boron previously implanted in the p-type tub.

Abstract: An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.

Abstract: Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphized regions to form first deep halo implants, laser thermal annealing to recrystallize the first deep amorphized regions and activate the deep halo regions, ion implanting to form second shallow amorphized regions within the deep halo regions, ion implanting an impurity into the second shallow amorphous regions to form second shallow halo implants and laser thermal annealing to recrystallize the second shallow amorphous regions and to activate the shallow halo regions. Embodiments further include forming shallow source/drain extensions within the shallow halo implants and laser thermal annealing to activate the shallow source/drain extensions.

Abstract: A semiconductor device and a manufacturing method for the same can be obtained wherein a semiconductor substrate of a high resistance that can enhance the Q value of a passive circuit element is used and leak current due to the impurity fluctuation that easily occurs in this high resistance semiconductor substrate, and whereby noise resistance of an active element in the high resistance semiconductor substrate is increased. A semiconductor device including a bipolar transistor formed in the main surface of a semiconductor substrate is provided wherein the bipolar transistor includes a semiconductor layer of a first conductive type at a bottom portion thereof and this semiconductor device is provided with a buried layer of a second conductive type, which is located in the semiconductor substrate so as to face the semiconductor layer of the first conductive type.

Abstract: A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit having both bipolar and CMOS devices, the lateral bipolar transistor being formed according to the BiCMOS method and without additional steps relative to formation of vertical bipolar devices if provided in the same area. Among other things, an integrated circuit is provided in which P well structures are provided in the collector regions of an LPNP that have been found to affect a significant increase in the product of the Early voltage and the current gain.

Abstract: A method of fabricating an integrated circuit utilizes asymmetric source/drain junctions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS). The drain extension is deeper than the source extension. The source extension is more conductive than the drain extension. The transistor has reduced short channel effects and strong drive current and yet is reliable.

Abstract: Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and p-type InAs is used to create extremely high speed bipolar devices which, due to reduced turn-on voltages, lend themselves to circuits having drastically reduced power dissipation. The described HBTs are fabricated on InAs or GaSb substrates, and include an InPSb emitter. The base includes In and As, in the form of InAs when on an InAs substrate, and as InAsSb when on a GaSb substrate. The collector may be the same as the base to form a single heterojunction bipolar transistor (SHBT) or may be the same as the emitter to form a double heterojunction bipolar transistor (DHBT). Heterojunctions preferably include a grading layer, which may be implemented by continuously changing the bulk material composition, or by forming a chirped superlattice of alternating materials.

Abstract: The present invention aims to suppress certainly the single-crystallizing in polycrystalline silicon that is to compose an emitter electrode, as well as to prevent the interface oxide film from remaining, when a heat treatment is conducted to diffuse dopants, and thereby it is also aimed to regulate the emitter dopant concentrations according to the design as well as to lower the emitter electrode resistance, which will provide a stable hFE; and further, the present invention aims to prevent anomalous bodies such as water-marks to be accidentally produced in a cleaning step following dry etching step to form an emitter electrode, and thereby to achieve an increase in yield as well as an enhancement of device reliability; in the process of the present invention, after an insulating film 4 and a first polycrystalline silicon film 5 are selectively dry etched to form a contact hole, a substrate is cleaned with such a cleansing agent as that composed of ammonia, hydrogen peroxide and water.

Abstract: A method for fabricating an integrated circuit having analog and digital core devices. Using a first masking layer (118), a p-type type dopant is implanted to form drain extension regions (126, 122, 124) in the pMOS digital core region (102), pMOS I/O region (104), and the pMOS analog core region (106). Using a second masking layer (132), a n-type dopant is implanted into at least a drain side of the nMOS analog core region (110) and the nMOS I/O region (108) to for drain extension regions (142, 144) and into the pMOS digital core region (102). This forms a pocket region (140) in the pMOS digital core region (102) but not the pMOS analog core region (106) or the pMOS I/O region (104).

Abstract: A Schottky diode which provides a structure having no P-N junction while improving voltage resistance against a reverse bias when employed in combination with an insulated gate semiconductor device in particular. In order to attain the aforementioned object, a P-type impurity region having a surface exposed on a surface of an N-type semiconductor substrate functioning as a drain for functioning as a channel region and a gate insulator film covering it are provided. A gate electrode is extended from above the gate insulator film over a first taper of an oxide film. In a Schottky diode rendering the semiconductor substrate a cathode and having a boundary layer as a Schottky region, on the other hand, an anode electrode is extended from above the boundary layer over a second taper of the oxide film existing above an end portion of the boundary layer.

Abstract: According to one embodiment of the invention, a method used in manufacturing an intermediate structure in a bipolar junction transistor includes implanting a base dopant in a semiconductor substrate to form a base, forming a dielectric layer outwardly from the semiconductor substrate, etching a portion of the dielectric layer to form an emitter region, forming an emitter polysilicon layer on the semiconductor substrate, and after forming the emitter polysilicon layer, annealing the semiconductor substrate.

Abstract: A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via multiple ion implantation procedures, performed through, and self-aligned to, an overlying emitter opening, in an oxide layer. The self-aligned collector regions, completely fill the space in the lighter doped collector region, located between the overlying base region, and the underlying subcollector region.

Abstract: The invention relates to a semiconductor device comprising a preferably discrete bipolar transistor with a collector region (1), a base region (2), and an emitter region (3) which are provided with connection conductors (6, 7, 8). A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor (7) of the base region (2) is also put into contact with the collector region (1).

Abstract: An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P+ buried layers 8601 and 8602 on opposite sides of N+ buried layer 8605. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.

Abstract: A method of manufacturing a semiconductor device includes the step of doping an N-type impurity via a selective region formed on a semiconductor substrate by lithography, the step of doping a P-type impurity in the semiconductor substrate subsequent to the doping step without forming a selective region by lithography, and the step of self-aligningly forming an N-diffusion layer and a P-diffusion layer by performing wet oxidation with respect to the semiconductor substrate in which the N-type impurity and the P-type impurity are doped.

Abstract: The present invention relates to a method of manufacturing a thin film transistor for use in a liquid crystal display apparatus or the like. In the method, impurity ions are implanted into a semiconductor by intermittently generating a plasma which generates impurity ions, for a predetermined period at a predetermined interval. By changing the duty rate at which the plasma is generated, the effective value of a beam current can be controlled over a wide range with excellent accuracy without changing rates of ions. As a result, it is possible to form a channel portion and a lightly doped drain layer of a field effect transistor which contains silicon as a main component, so that a field effect transistor and a liquid crystal display device can be manufactured with high quality and excellent productivity.

Abstract: The invention relates to the manufacture of a so-called double poly bipolar transistor. In a layer structure of a first insulating layer (4), a polycrystalline layer (5) of silicon and a second insulating layer (6), an opening (7) is formed which extends to a monocrystalline part of the semiconductor body (10), a third insulating layer (8) being provided on the bottom of the opening (7). Via the opening (7) at least a part (1A) of the base (1) is formed. By means of a further opening (9) in the third insulating layer (8), the emitter (3) is formed. A drawback of the known method resides in that the transistors obtained by means of said method exhibit a relatively great spread in electrical characteristics, such as a base current which is not ideal and demonstrates a spread.

Abstract: High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. A layer of cobalt and a cap layer of titanium or titanium nitride are deposited on a substrate above intended source/drain regions, followed by silicidation. Embodiments include low-temperature rapid thermal annealing to form a high-resistivity phase cobalt silicide, removing the cap layer, depositing a doped film on the first phase cobalt silicide, and heating, as by high-temperature rapid thermal annealing, to form a low-resistance cobalt silicide during which impurities from the doped film diffuse through the cobalt silicide into the substrate to form source/drain regions having junctions extending into the substrate a constant depth below the cobalt silicide/silicon substrate interface. In another embodiment, impurities are diffused from the doped film to form source/drain regions and self-aligned junctions following formation of the low-resistance phase cobalt silicide.

Abstract: A photoresist pattern is formed on a field oxide film and an element forming region across the field oxide film and the element forming region such that a portion of a surface of the field oxide film and a portion of a surface of a silicon epitaxial layer are continuously exposed. The photoresist pattern is used as a mask to inject boron ions into the silicon epitaxial layer and heat treatment is performed thereon to form an external base containing the relatively significant crystal defect present in the silicon epitaxial layer in the vicinity of the field oxide film. Thus, a semiconductor device can be obtained including a bipolar transistor which provides improved breakdown voltage between the collector and the base and contemplates reduction of current leakage.

Abstract: A semiconductor device (10) is formed in a semiconductor substrate (11) and an epitaxial layer (14). The semiconductor device includes a p-type body region (16), a source region (17), a channel region (19), and a drain region (34) formed in the epitaxial layer (14). A doped region (13) is formed in the semiconductor substrate (11) to reduce the drift resistance of the semiconductor device (10). The drain region (34) is formed from a plurality of doped regions (30-33) that can be formed with high energy implants.

Abstract: A fabrication method for a MOSFET device including the steps of forming a first insulating film on a semiconductor substrate wherein an active region and an isolated region are defined, forming a channel ion region by implanting impurity ions into the active region of the semiconductor substrate, forming a first conductive film pattern on a portion of the semiconductor substrate which corresponds to the channel ion region, forming a channel region having lower concentration than the channel ion region by implanting impurity ions in a different type from the ions in the channel ion region into a center portion of the channel ion region through the first conductive film pattern, forming a second conductive film pattern on the first conductive film pattern, forming an impurity region of low concentration in the semiconductor substrate with the first and second conductive film patterns as a mask, forming a sidewall spacer at both sides of the first and second conductive film patterns, and forming an impurity regi

Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.

Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a surface of a p-type semiconductor region, and then removed from a selected portion of the p-type semiconductor region. An n-type region having a high concentration of arsenic atoms is formed in a surface layer of the selected portion of the p-type semiconductor region from which the insulating film is removed. Subsequently, boron ions are implanted over an entire surface of the device in a concentration that is lower than that of the n-type region and higher than that of the p-type semiconductor region, to a smaller depth than that of the n-type region, and heat treatment is then effected to form a high-concentration boron diffused region in a surface layer of the p-type semiconductor region.

Abstract: In a semiconductor device manufacturing method, a buried collector region (5) of a bipolar transistor is formed, and then born is ion-implanted into at least the lower portion of a graft base region (15) to form a region (10) having a low donor concentration, whereby the capacitance between the collector and the base of the bipolar transistor can be reduced to achieve a high-speed operation of a circuit.

Abstract: A bipolar transistor with MOS-controlled protection for a reverse-biased emitter-base junction is disclosed. A bipolar transistor and a MOS transistor are configured with the drain and the gate electrically coupled to the emitter, and the source and body electrically coupled to the base. A reverse-bias at the emitter-base junction, which is less than a breakdown voltage for the emitter-base junction, activates the MOS transistor which substantially reduces the resistance between the emitter and the base. Preferably, a first semiconductor region provides both the drain and the emitter, and a second semiconductor region provides both the body and the base, for reduced surface area on an integrated circuit chip.

Abstract: A method of fabricating semiconductor devices comprises the following process of: forming an electrode leading out window having its vertical side wall at a given position in the functional element formed on a semiconductor substrate; forming an insulating film on the surface of the side wall; and depositing an electrode metal in the leading out window.

Abstract: The present invention is directed to a man-made fiber comprising a cellulose ester and 0.05 to 5.0% by weight of a titanium dioxide having an average particle size of less than 100 nanometers.