Abstract: Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract: A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into to the portion of a semiconductor substrate along the side wall of trench, impurity ions are irradiated in parallel to the side wall of trench to implant the impurity ions only into to the portion of semiconductor substrate beneath the bottom wall of trench; the substrate is heated to drive the implanted impurity ions to form an offset drain region around trench and to thermally oxidize semiconductor substrate to fill the trench 2 with an oxide. Alternatively, the semiconductor substrate is oxidized to narrow trench with oxide films leaving a narrow trench and the narrow trench left is filled with an oxide.

Abstract: A process uses pressure changes and a pressure compensation factor to estimate the rate at which neutral atoms are implanted. While implanting a first wafer using a first pressure compensation factor, the rate at which ions are implanted is determined. The first wafer is moved radially with respect to an ion beam while implanting ions into the first wafer so as to achieve a uniform total dose based on the rate at which ions are implanted and the estimated rate at which neutral atoms are implanted. The pressure is determined while implanting the first wafer, determining the pressure. A second pressure compensation factor is selected, that would have achieved a uniform rate of implanted ions plus implanted neutral atoms across a surface of the first wafer. The second pressure compensation factor is different from the first pressure compensation factor. The second pressure compensation factor is used to implant a second wafer. The second wafer is tested by forming a sheet resistance contour map.

Abstract: A varactor designed to enable voltage controlled oscillator (VCO) integration in wireless systems is the base-emitter junction of a specially optimized NPN device formed with a double base implant. A first, shallow implant optimizes capacitance, leakage current, and tuning range. A second, deeper base implant is used to improve the quality factor of the device by reducing the base resistance. The varactor includes a third terminal (collector), which isolates the emitter-base junction from the substrate, providing flexibility in circuit applications. A method for fabricating a high performance varactor having the above-described structure is also provided.

Abstract: A method of monitoring and adjusting the position of a wafer with respect to an ion beam including setting the position of a wafer holder so that a wafer to be held therein is positioned at a tilt angle of 45 degrees and a twist angle of 45 degrees with respect to the path of an ion beam; positioning a n-type wafer without screen oxide in the wafer holder; implanting boron species into a region of the wafer at 160 KeV and a dose level of 5.0×1013 atoms/cm2; periodically measuring the sheet resistivity of a implanted wafer and readjusting the wafer tilt angle when the sheet resistivity is greater than 30 ohms/square.

Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.

Abstract: The present invention provides a method of forming a liquid crystal display (LCD). Active layers of N-type and P-type low temperature polysilicon thin film transistors and a bottom electrode of a storage capacitor are formed first. Then a N-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. After that, a P-type source/drain is formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.

Abstract: A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may further comprise a cap layer situated over the base layer. According to this embodiment, the method for fabricating the NPN bipolar transistor further comprises fabricating an emitter over the base layer, where the emitter defines an intrinsic and an extrinsic base region of the base layer. The emitter may comprise, for example, polycrystalline silicon. The method for fabricating the NPN bipolar transistor further comprises implanting germanium in the extrinsic base region of the base layer so as to make the extrinsic base region substantially amorphous. The method for fabricating the NPN bipolar transistor further comprises implanting boron in the extrinsic base region of the base layer.

Abstract: A resist material used to mask an underlying layer during an etch process is subjected to ion implantation to harden the resist material against damage from the etch process. In a particular embodiment, the resist material is compatible with exposure to 193 nm radiation for patterning the resist material.

Abstract: A manufacturing method of a semiconductor substrate comprising the steps of: (a) forming a SiGe layer on a substrate of which the surface is made of silicon; (b) further forming a semiconductor layer on the SiGe layer; and (c) implanting ions into regions of the SiGe layer in the substrate that become element isolation formation regions, and carrying out a heat treatment.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A method for fabricating a bipolar transistor includes: a first step of implanting, along the normal direction of the principle surface of a first-conductive-type semiconductor single crystalline substrates ions of a second-conductive-type first impurity into the semiconductor single crystalline substrate to form a second-conductive-type collector layer; a second step of implanting, along the direction tilted from the normal direction, ions of a second-conductive-type second impurity into the semiconductor single crystalline substrate at a higher injection energy than that in the ion implantation of the first step to form a buried collector layer in a lower portion of the collector layer; and a third step of forming each of a first-conductive-type base layer and a second-conductive-type emitter layer in a predetermined region of a surface portion of the collector layer.

Abstract: According to one exemplary embodiment, a method for fabricating a bipolar transistor, such as a heterojunction bipolar transistor (“HBT”), comprises fabricating a first inner spacer and a second inner spacer on a top surface of a base. The method further comprises forming a first outer spacer adjacent to the first inner spacer and a second outer spacer adjacent to the second inner spacer. According to this exemplary embodiment, the method further comprises depositing an emitter between the first and second inner spacers on the top surface of the base. The method may further comprise depositing an intermediate oxide layer on the first and second outer spacers after forming the first and second outer spacers. The method may further comprise depositing an amorphous layer on the intermediate oxide layer. The method may also comprise depositing an antireflective coating layer on the amorphous layer.

Abstract: A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost effective manner. The method provides for fewer masking operations during bipolar junction transistor formation, in a CMOS flow process, yet also provides for the bipolar junction transistor to be optimized.

Abstract: A dielectric layer comprises lanthanum, aluminum, nitrogen, and oxygen and is formed between two conductors or a conductor and substrate. In one embodiment, the dielectric layer is graded with among the lanthanum, nitrogen, or aluminum. An additional insulating layer may be formed between the conductor or substrate and the dielectric layer. The dielectric layer can be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

Abstract: A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component.

Abstract: A method of manufacturing a CMOS TFT including forming first and second semiconductor layers on an insulating substrate using a first mask, respectively, the substrate having first and second regions, the first semiconductor layer formed on the first region, the second semiconductor layer formed on the second region; forming sequentially a first insulating layer, a first metal layer and a second insulating layer over the whole surface of the substrate; etching a portion of the first metal layer and a portion of the second insulating layer over the first region of the substrate using a second mask to form a first gate electrode and a first capping layer; forming first spacers on both side wall portion of the first gate electrode and the first capping layer; ion-implanting a first conductive-type high-density impurity into the first semiconductor layer using the first spacers and the first gate electrode as a mask to form first high-density source and drain regions; etching a portion of the first metal layer an

Abstract: A method for fabricating a polysilicon emitter bipolar transistor employs a pair of ion implant methods. A first of the icon implant methods implants a portion of an intrinsic base region interposed between an extrinsic base region and a polysilicon emitter layer with an amorphizing non-active dopant. A second of the ion implant methods implants the polysilicon emitter layer with an active dopant to form a doped polysilicon emitter layer. The polysilicon emitter bipolar transistor is fabricated with enhanced performance.

Abstract: A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

Abstract: During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for producing two adjacent regions of a predetermined area in an integrated semiconductor, whereby a first region of the two adjacent regions includes a doping with a lower target concentration than a second region. The predetermined area of a semiconductor blank is doped with a dopant until a concentration of the dopant is obtained that is at least as high as the target concentration of the second region. A protective layer is applied to the second region, and the dopant is out-diffused from the first region until a concentration of dopant is obtained that corresponds to the target concentration of the first region.

Abstract: A CMOS device (10) having p-channel and n-channel transistors with aluminum implanted gates (20). When making the device (10), aluminum is non-selectively implanted to form a source and drain for the n-channel transistor and to reduce the resistivity of the gates (20). The aluminum diffuses through an upper polysilicon layer (22) of the gate, thereby reducing its resistivity, but does not diffuse through a lower oxide layer (24) of the gate, thereby preventing penetration problems. Thereafter, a compensating implant (e.g., phosphorus or arsenic) is selectively implanted to overcompensate the boron previously implanted in the p-type tub.

Abstract: A manufacturing method of a semiconductor substrate comprising the steps of: (a) forming a SiGe layer on a substrate of which the surface is made of silicon; (b) further forming a semiconductor layer on the SiGe layer; and (c) implanting ions into regions of the SiGe layer in the substrate that become element isolation formation regions, and carrying out a heat treatment.

Abstract: One aspect of the present invention relates to a method of making a flash memory cell, involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; forming a MDD mask over the substrate, the MDD mask covering the source lines and having openings corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region in the substrate adjacent the flash memory cell.

Abstract: A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit having both bipolar and CMOS devices, the lateral bipolar transistor being formed according to the BiCMOS method and without additional steps relative to formation of vertical bipolar devices if provided in the same area. Among other things, an integrated circuit is provided in which P well structures are provided in the collector regions of an LPNP that have been found to affect a significant increase in the product of the Early voltage and the current gain.

Abstract: A kill index classification method for prioritizing relational aspects of topological defect intersections, particularly in association with an intermediate analytical testing stage of a multi-stage semiconductor fabrication process. The method relates to an analysis of the geometrical relationship between non-predetermined portion(s), generally referred to as defects, and the surrounding predetermined topology of a conductive semiconductor pattern, to determine the effect of defects on the functionality and reliability of a wafer, and particularly an examined die thereon. Further, in accordance with this geometrical information, a preferred classification of the effects of defects into a numerical value, the “kill index”, is achieved. Preferably, this kill index is strongly linked, correlated and related to the damage caused by the defect to the functionality and/or reliability of the underlying integrated circuit.

Abstract: An ion implantation method which can accurately control the effective dose amount even in ion implantation at a very low energy. This ion implantation method comprises the steps of carrying out preamorphization ion implantation for a semiconductor substrate in an ion implantation apparatus; then cleaning the surface of semiconductor substrate in a cleaning apparatus so as to eliminate an oxidized film; and thereafter carrying out ion implantation again in the ion implantation apparatus under a low implantation energy so as to form a shallow junction in the semiconductor substrate. As a consequence, the influence of the oxidized film formed by preamorphization ion implantation can be suppressed, whereby the effective dose can be controlled accurately.

Abstract: A method for forming a self-aligned bipolar transistor includes the steps of combination etching a silicon substrate in an opening to form a concave surface on the silicon substrate, and forming an intrinsic base and an associated emitter on the concave surface. The combination etching includes an isotropic etching and subsequent wet etching. The concave surface increases the distance between the external base for the intrinsic base and the emitter to thereby increase the emitter-base breakdown voltage.

Abstract: A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

Abstract: A non-critical block mask exposes one of the source and drain in an SOI FET, which is implanted with a leakage implant that increases the leakage in the exposed element, thus providing a conductive path to draw away holes from the transistor body.

Abstract: A tunneling magnetoresistive device comprises an insulating barrier layer, and at least two ferromagnetic layers provided on the same plane of the layer. The insulating barrier layer can be initially formed, so that when a metal layer is oxidized to form the insulating barrier layer, it is unnecessary to pay care to the influence of oxidation on the ferromagnetic layers. The insulating barrier layer can be formed in large thickness, thereby suppressing defects, such as pinholes, from occurring. Thus, a tunneling magnetoresistive device having good characteristics can be manufactured.

Abstract: A method for fabricating an integrated circuit having analog and digital core devices. Using a first masking layer (118), a p-type type dopant is implanted to form drain extension regions (126, 122, 124) in the pMOS digital core region (102), pMOS I/O region (104), and the pMOS analog core region (106). Using a second masking layer (132), a n-type dopant is implanted into at least a drain side of the nMOS analog core region (110) and the nMOS I/O region (108) to for drain extension regions (142, 144) and into the pMOS digital core region (102). This forms a pocket region (140) in the pMOS digital core region (102) but not the pMOS analog core region (106) or the pMOS I/O region (104).

Abstract: A method to improve the characteristics of bipolar silicon high-frequency transistor by adding indium into the base of the transistor is described. Instead of replacing boron in the base with indium to improve the beta-Early voltage product, at the price of high beta and high base resistance, separate boron and indium doping profiles are combined in the base. Thus, a transistor, which preserves most of the properties of pure boron-base transistor, is obtained, but with some parameters improved due to the added indium profile. This “double-profile” or “indium-enhanced” transistor exhibits improved beta-Early voltage product, reduced collector-base capacitance swing and lower temperature dependence of beta, but preserves the advantageous properties of a pure boron-base transistor.

Abstract: The present invention provides a method to fabricate an MOS transistor and to reduce the gate-induced-drain-leakage current. The method is primarily to form a mask on the top of the gate. Because of the screening of the mask, spaced regions will be formed between the gate and the lightly doped drain/source regions in an ion-implantation process. Afterward, By using another ion-implantation process with opposite conductive type ions, package regions is then formed between the substrate and the lightly doped drain/source regions. Then, a sidewall of the gate is formed, and the drain/source regions are also formed by an ion-implantation process. Finally, an anneal process is performed to complete the fabrication of the MOS transistor. Because of the existence of the spaced regions that we propose in advance, such design can avoid overlap between a gate and lightly doped drain/source regions. Consequently, the method provided in the present invention can decrease the problem of gate-induced-drain-leakage current.

Abstract: A method of manufacturing a CMOS TFT including forming first and second semiconductor layers on an insulating substrate using a first mask, respectively, the substrate having first and second regions, the first semiconductor layer formed on the first region, the second semiconductor layer formed on the second region; forming sequentially a first insulating layer, a first metal layer and a second insulating layer over the whole surface of the substrate; etching a portion of the first metal layer and a portion of the second insulating layer over the first region of the substrate using a second mask to form a first gate electrode and a first capping layer; forming first spacers on both side wall portion of the first gate electrode and the first capping layer; ion-implanting a first conductive-type high-density impurity into the first semiconductor layer using the first spacers and the first gate electrode as a mask to form first high-density source and drain regions; etching a portion of the first metal layer an

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: According to one embodiment of the invention, a method used in manufacturing an intermediate structure in a bipolar junction transistor includes implanting a base dopant in a semiconductor substrate to form a base, forming a dielectric layer outwardly from the semiconductor substrate, etching a portion of the dielectric layer to form an emitter region, forming an emitter polysilicon layer on the semiconductor substrate, and after forming the emitter polysilicon layer, annealing the semiconductor substrate.

Abstract: The present invention relates to a method of manufacturing the base and emitter regions of a bipolar transistor, including the steps of depositing a first heavily-doped P-type polysilicon layer; eliminating the first polysilicon layer in its central portion; growing a thermal oxide layer; performing a P-type implantation at a first dose; forming silicon nitride spacers at the internal periphery of the first layer; performing a second P-type implantation at a second dose; eliminating the central oxide layer; depositing a second N-type polysilicon layer; and performing a fast thermal anneal; the second dose being selected to optimize the characteristics of the base-emitter junction and the first dose being smaller than the second dose.

Abstract: For fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a layer of gate dielectric material containing nitrogen is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A first P-type dopant, such as boron for example, is implanted into a first region of the layer of gate electrode material disposed over a first active device area of the semiconductor substrate. The first region of the layer of gate electrode material is patterned to form a PMOS gate electrode. The layer of gate dielectric material is patterned to form a PMOS gate dielectric disposed under the PMOS gate electrode.

Abstract: A method for fabricating an integrated circuit having analog and digital core devices. Using a first masking layer (118), a p-type type dopant is implanted to form drain extension regions (126, 122, 124) in the pMOS digital core region (102), pMOS I/O region (104), and the pMOS analog core region (106). Using a second masking layer (132), a n-type dopant is implanted into at least a drain side of the nMOS analog core region (110) and the nMOS I/O region (108) to for drain extension regions (142, 144) and into the pMOS digital core region (102). This forms a pocket region (140) in the pMOS digital core region (102) but not the pMOS analog core region (106) or the pMOS I/O region (104).

Abstract: The present invention relates to a method of manufacturing a thin film transistor for use in a liquid crystal display apparatus or the like. In the method, impurity ions are implanted into a semiconductor by intermittently generating a plasma which generates impurity ions, for a predetermined period at a predetermined interval. By changing the duty rate at which the plasma is generated, the effective value of a beam current can be controlled over a wide range with excellent accuracy without changing rates of ions. As a result, it is possible to form a channel portion and a lightly doped drain layer of a field effect transistor which contains silicon as a main component, so that a field effect transistor and a liquid crystal display device can be manufactured with high quality and excellent productivity.

Abstract: Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.

Abstract: A MOS transistor having a self-aligned well bias area and a method of fabricating the same provide for efficient application of well bias in a highly integrated semiconductor substrate without causing latch-up. The well bias area is formed at a trench, which is formed by etching a semiconductor substrate in a manner of self-alignment, so that well bias can be efficiently applied to the MOS transistor achieving reduction of the area of a chip without degradation of electrical characteristics.

Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.

Abstract: A photoresist pattern is formed on a field oxide film and an element forming region across the field oxide film and the element forming region such that a portion of a surface of the field oxide film and a portion of a surface of a silicon epitaxial layer are continuously exposed. The photoresist pattern is used as a mask to inject boron ions into the silicon epitaxial layer and heat treatment is performed thereon to form an external base containing the relatively significant crystal defect present in the silicon epitaxial layer in the vicinity of the field oxide film. Thus, a semiconductor device can be obtained including a bipolar transistor which provides improved breakdown voltage between the collector and the base and contemplates reduction of current leakage.

Abstract: A method for producing a low-impedance contact between a metallizing layer and a semiconductor material of a first conductivity type having a semiconductor surface, an insulation layer on the semiconductor surface and a semiconductor layer on the insulation layer, includes applying a first insulating layer with a predetermined content of dopants on the semiconductor layer, and structuring the first insulating layer by anisotropic etching, forming first and second openings. The semiconductor layer is anisotropically etched by using the first insulating layer as a mask. A first dopant of a second conductivity type is implanted and driven through the first opening into the semiconductor material with a first phototechnique, forming a first zone in the semiconductor material. A second dopant of the first conductivity type is implanted through the second opening into the semiconductor material with a second phototechnique. A second doped insulating layer is applied over the entire surface.

Abstract: A fabrication method for a MOSFET device including the steps of forming a first insulating film on a semiconductor substrate wherein an active region and an isolated region are defined, forming a channel ion region by implanting impurity ions into the active region of the semiconductor substrate, forming a first conductive film pattern on a portion of the semiconductor substrate which corresponds to the channel ion region, forming a channel region having lower concentration than the channel ion region by implanting impurity ions in a different type from the ions in the channel ion region into a center portion of the channel ion region through the first conductive film pattern, forming a second conductive film pattern on the first conductive film pattern, forming an impurity region of low concentration in the semiconductor substrate with the first and second conductive film patterns as a mask, forming a sidewall spacer at both sides of the first and second conductive film patterns, and forming an impurity regi

Abstract: Impurities are formed in the active region of a semiconductor substrate by diffusion from a gate electrode sidewall spacer. A gate electrode is formed on a semiconductor substrate with a gate dielectric layer therebetween. Sidewall spacers are formed on the side surfaces of the gate electrode. Dopant atoms are subsequently introduce to transform the spacers into solid dopant sources. Dopant atoms are diffused from the spacers into the semiconductor substrate to form first doped regions.

Abstract: Process for producing a structure having a low dislocation density comprising an oxide layer buried in a semiconductor substrate. This process for producing an epitaxied structure with a low dislocation density has the structure incorporating an oxide layer (6) in a substrate (4) made from a semiconductor material and successively involves at least one implantation of oxygen ions in the substrate (4), at least one first conditioning heat treatment of the substrate, an epitaxy of a layer (14) of a semiconductor material on the substrate and a second heat treatment for eliminating dislocations (8) from the structure.