Abstract: An electrical device having a voltage dependent capacitance is provided comprising a first region of a semiconductor material, and a second region and a third region of a semiconductor material formed in the first region, the second and third regions being separated by a separation region, and an electrically insulating layer formed on the first region at least at a region corresponding to the separation region, and a substantially conductive element formed on the insulating layer at least at a region corresponding to the separation region such that the insulating layer electrically insulates the substantially conductive element from the first, second and third regions, and a first electrode connected to the substantially conductive element, and a second electrode and third electrode are connected to the second and third regions. A method of manufacturing the device is also disclosed.

Abstract: The invention discloses a variable capacitor including a first storage electrode, a second storage electrode, and a variable length means coupled therebetween. The capacitance can be adjusted by varying a dielectric space therebetween according with an electrical input. The method for manufacturing a variable capacitor in an integrated circuit includes the steps of forming a first storage electrode, a first dielectric layer, a second dielectric layer, a pair of contact channels, and a second sacrificial layer. The method further includes forming a third sacrificial layer, a second storage electrode, a resistor pattern, a passivation layer, and etching the third, the second, and the first sacrificial layer for having a dielectric space between the first storage electrode and the second storage electrode.

Abstract: The invention discloses a variable capacitor including a first storage electrode, a second storage electrode, and a variable length means coupled therebetween. The capacitance can be adjusted by varying a dielectric space therebetween according with an electrical input. The method for manufacturing a variable capacitor in an integrated circuit includes the steps of forming a first storage electrode, a first dielectric layer, a second dielectric layer, a pair of contact channels, and a second sacrificial layer. The method further includes forming a third sacrificial layer, a second storage electrode, a resistor pattern, a passivation layer, and etching the third, the second, and the first sacrificial layer for having a dielectric space between the first storage electrode and the second storage electrode.

Abstract: A method of reducing metal contamination during semiconductor processing in a reactor having metal components is provided. The method includes forming an aluminum oxide layer on the surface of certain of the metal components before processing of substrates. The aluminum oxide layer substantially prevents the formation of volatile metal atoms from the metal components. The aluminum oxide layer is formed by heating the metal component first in a dry N.sub.2 atmosphere to a first temperature, and then in a dry H.sub.2 atmosphere to a second temperature. The component is then soaked at the second temperature in a wet H.sub.2 atmosphere to form the aluminum oxide layer, and is followed by soaking at the second temperature in a dry H.sub.2 atmosphere to reduce any other metal oxides that may have formed. The component is then cooled first in a dry H.sub.2 atmosphere, and then in a dry N.sub.2 atmosphere where a layer of substantially pure aluminum oxide is provided on the surface of the metal component.

Abstract: The invention relates to a method of manufacturing a semiconductor device with a pn junction, whereby an epitaxial layer (2) with a first zone (3) of a first conductivity type and with a second zone (4) of a second conductivity type opposed to the first is provided on a silicon substrate (1), a pn junction (5) being formed between the second and first zones (3, 4, respectively). According to the invention, the method is characterized in that the epitaxial layer (2) is provided by means of a CVD process at a temperature below 800.degree. C., the epitaxial layer (2) being provided in that first the first zone (3) and then the second zone (4) are epitaxially provided on the substrate (1), while no heat treatments at temperatures above 800.degree. C. take place after the epitaxial layer (2) has been provided.

Abstract: The invention relates to a method of manufacturing a varicap diode whereby a silicon substrate with an epitaxial layer of a first conductivity type is provided with a first zone through the provision of dopant atoms of a first conductivity type in the epitaxial layer and is provided with a second zone adjoining a surface of the epitaxial layer through the provision of dopant atoms of a second conductivity type opposed to the first in the epitaxial layer, a pn junction being formed between the second zone and the first zone. According to the invention, the method is characterized in that the second zone is provided in that a layer of polycrystalline silicon provided with dopant atoms of the second conductivity type is provided on the surface, and in that the dopant atoms are diffused from this layer into the epitaxial layer, whereby a pn junction is formed at a distance of less than 0.3 .mu.m from the polycrystalline silicon.

Abstract: A variable-capacitance device has an n-type diffusion layer which has an impurity concentration profile such that a region where the impurity concentration remains substantially constant and a region where the impurity concentration changes abruptly are alternately repeated, and the impurity concentration increases as the deepness from the surface increases. The impurity concentration profile can be achieved by implanting n-type impurity atoms a plurality of times with different energies in an ion implantation process or varying the concentration of n-type impurity atoms such as of phosphorus added upon epitaxial layer growth. The variable-capacitance device, and a semiconductor integrated circuit device composed of a plurality of such variable-capacitance devices can be fabricated on a semiconductor substrate, and are highly stable.

Abstract: The subject invention relates to a hybrid reinforcement material comprising a refractory metal core having a first coating comprising aluminum, oxygen and nitrogen, this coating of the general formula:Al.sub.x O.sub.y N.sub.zwhereinx is up to about 670 atomic % of the coatingy is from about 20 atomic % to about 55 atomic % ofthe coating; andz is from about 5 atomic % to about 45 atomic % of the coating, with the proviso that x+y+z=100, and having a second SiC coating.The subject invention further relates to a high strength, high temperature performance composite containing the hybrid reinforcement specified above.