Abstract: A method for fabricating a semiconductor device comprises the steps of forming a polysilicon film 32 on a silicon substrate 10, implanting a dopant into a region of the polysilicon film 32 for a resistance element to be formed in, patterning the polysilicon film 32 to from the resistance element 46 of the polysilicon film 32 with the dopant inplanted in and gate electrodes 44a, 44b of the polysilicon film 32 with the dopant not implanted in. Accordingly, resistance element can be formed while suppressing influences on characteristics of the transistor formed on one and the same substrate concurrently with forming the resistance element.

Abstract: First and second gate electrodes are formed on first and second regions of a semiconductor substrate. Second conductivity type impurities are implanted into the second region to form first impurity diffusion regions. Spacer films are formed on the side surfaces of the first and second gate electrodes. Second conductivity type impurities are implanted into the first and second regions to form second impurity diffusion regions. After the spacer films are removed, second conductivity type impurities are implanted into the first region to form third impurity diffusion regions. The third activation process is performed so that the gradient of impurity concentration distribution around the third impurity diffusion region becomes steeper than the gradient of impurity concentration distribution around the first impurity diffusion region.

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: A plurality of gate electrodes is formed on a semiconductor substrate having a DRAM area and a logic area. Next, sidewalls, each of which includes a silicon nitride film covering the sides of gate electrodes and a silicon oxide film covering the silicon nitride film, are formed on the sides of the gate electrodes respectively. After formation of a transistor having an LDD structure in the logic area, the silicon oxide film formed on the sides of the gate electrodes is removed by wet etching. Next, a silicon nitride film is formed on the whole surface of the semiconductor substrate, and an interlayer dielectric is formed on the silicon nitride film.

Abstract: A CMOS device includes a reverse electric conduction type well (2) formed on a monoelectric conduction type semiconductor substrate (1), a first MOS transistor (3) of a reverse electric conduction type channel formed on a surface of the semiconductor substrate, and a second MOS transistor (4) of monoelectric conduction type channel is formed on a surface of the well. In the present invention, resistance elements (8R, 7R, 2R) are formed in the semiconductor substrate on a lower side of a thick field oxide film (9) covering a surface of the semiconductor substrate. Further, a second resistance element (11R) composed of a polycrystal silicon layer is formed on an upper side of the field oxide film.

Abstract: A thin film resistor (55) is formed over an etch stop layer 40. Contact pads (65) are formed n the thin film resistor (55) and a dielectric layer (80) is formed over the thin film resistor (55). Metal structures (120 are formed above the thin film resistor (55) and metal (110) is used to fill a trench and via formed in the dielectric layer (80).

Abstract: A current mirror bias circuit for an RF amplifier transistor is modified whereby the reference transistor of the current mirror tracks hot carrier degradation in the RF transistor. Gate bias to the current mirror transistor is modified whereby the drain-to-gate voltage can be positive, and the lightly doped drain region in the lateral n-channel reference transistor is shortened and dopant concentration increased to increase the electric field of the reference transistor to provide the hot carrier injection degradation characteristics similar to the main transistor. Additionally, the gate length of the reference transistor can be shortened to effect the hot carrier injection degradation.

Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.

Abstract: A resistor layer (5) is formed on an isolation insulating film (4) selectively formed in a major surface (1S) of a semiconductor substrate (1). An interlayer insulation film (7) covering the resistor layer (5) has first and second plugs (9, 19) buried therein in the form of buried interconnections. The first and second plugs (9, 19) provide connection not only between an end portion of the resistor layer (5) and first and second interconnection layers (8, 18) but also between the end portion of the resistor layer (5) and the major surface (1S) of the semiconductor substrate (1).

Abstract: A thick film circuit with a perimeter anchored thick film pad is provided. The thick film circuit includes a base substrate, a thick film bonding pad, and a solder mask layer. The thick film bonding pad is formed on the surface of the base substrate. The solder mask layer is also formed on the surface of the base substrate, and overlaps a portion of the thick film bonding pad in order to improve adhesion between the thick film bonding pad and the base substrate.

Abstract: The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.

Abstract: The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.

Abstract: A method for the simultaneous formation of a gate electrode and a local interconnect or other interconnect structure in a semiconductor device is provided. In an embodiment of the method, an insulating layer disposed adjacent to a gate transistor is patterned to form an opening for the interconnect structure, and a sacrificial layer (e.g., silicon nitride) of the gate stack is removed to form a recess in the gate stack and expose an underlying conductive layer (e.g., polysilicon). A conductive material such as tungsten is deposited to simultaneously fill the recess of the gate stack and the opening in the insulating layer to form the interconnect structure. Exemplary interconnect structures include local interconnects, contacts, buried contacts, plugs, contact landing pads, and filled trenches.

Abstract: A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semiconductor processing to form a merged well. The normal wells and the small wells have a concentration that is greater than that of the merged well. The desired merging of the small wells is ensured by making sure that the small wells are sufficiently close together that the normal diffusion of well implants, which occurs from the particular semiconductor process that is being used, results in the merging. One desirable use of the merged well, with its lower doping concentration, is as a resistor that has more resistance than that of the regular well without requiring an additional implant.

Abstract: In one disclosed embodiment a layer is formed over a transistor gate and a field oxide region. For example, a polycrystalline silicon layer can be deposited over a PFET gate oxide and a silicon dioxide isolation region on the same chip. The layer is then doped over the transistor gate without doping the layer over the field oxide. A photoresist layer can be used as a barrier to implant doping, for example, to block N+ doping over the field oxide region. The entire layer is then doped, for example, with P type dopant after removal of the doping barrier. The second doping results in formation of a high resistivity resistor over the field oxide region, without affecting the transistor gate. Contact regions are then formed of a silicide, for example, for connecting the resistor to other devices.

Abstract: The present invention comprises an improved method of forming the source voltage lines, connection lines, and high load resistors for use in HLR SRAM devices. The source voltage lines, connection lines, and high load resistors are formed from a single polysilicon film that is selectively silicided to produce the low resistance structures while preserving the as-deposited polysilicon resistivity for formation of the high load resistor. The improved resistance control allows reduced feature size and increased pattern density.

Abstract: A thin film resistor fabrication method requires that an IC's active devices be fabricated on a substrate, and a dielectric layer be deposited over the devices to protect them from subsequent process steps. A layer of thin film material is deposited next, followed by a barrier layer and a first layer of metal. These three layers are patterned and etched to form isolated material stacks wherever a TFR is to be located, and a first level of metal interconnections. The first metal layer is removed from the TFR stacks, and the barrier layer is patterned and etched to provide respective openings which define the active areas of each TFR. In a preferred embodiment, a dielectric layer is deposited after the first metal layer is removed, to protect the interconnect metal from corrosion and as an adhesion layer for the patterning of the openings which define resistor length.

Abstract: A process for fabricating a buried stack capacitor structure, to be used in a one transistor, RAM cell, has been developed. The process features formation of a self-aligned, ring shaped storage node opening, formed in a top portion of an silicon oxide filled, shallow trench shape, via a selective dry etch procedure. The selective dry etch procedure in combination with subsequent selective wet etch procedures, create bare portions of semiconductor substrate at the junction of the ring shaped storage node opening and the adjacent top surface of semiconductor, allowing a heavily doped region to be created in this region. The presence of the heavily doped region reduces the node to substrate resistance encountered when a storage node structure is formed in the ring shaped storage node structure, as well as on the overlying the heavily doped region.

Abstract: The present invention is disclosed a microchannel array structure embedded in a silicon substrate and a fabrication method thereof. The microchannel array structure of the present invention is formed deep inside the substrate and has high-density microscopic micro-channels. Besides, going through surface micromachining, physical and chemical properties of the silicon substrate are hardly influenced by the fabrication procedures. With microchannels buried in the substrate, the top of a microchannel array structure becomes flat, minimizing the effect of step height. That way, additional devices such as passive components, micro sensors, micro actuators and electronic devices can be easily integrated onto the microchannel array structure.

Abstract: The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.

Abstract: A process for forming an electrical resistance in an integrated MOS transistor includes applying a first voltage to the source and gate of the MOS transistor, and applying a second voltage to the drain of the MOS transistor. A prebiasing voltage is applied to the substrate of the MOS transistor to make the base/emitter junction of a parasitic bipolar transistor of the MOS transistor conduct. The first and second voltages are capable of initiating a breakdown of the MOS transistor by an avalanche of the drain/substrate junction, an irreversible breakdown of the drain/substrate junction, and a short circuit between the drain and the source.

Abstract: A process for manufacturing a resistive structure that has a polysilicon strip laid above a semiconductor substrate is presented. The process begins by using a mask to cover the polysilicon strip. Then, several apertures are made in the mask until portions of the semiconductor strip are uncovered. Next, a dopant is implanted in the polysilicon semiconductor strip through the apertures. Finally, the resistive structure is subjected to a thermal process for diffusing the dopant in such a way to obtain a variable concentration profile in the semiconductor strip.

Abstract: A semiconductor fabrication method is provided for fabricating a resistor and a capacitor electrode in an integrated circuit, which can help enhance the quality of the resultant integrated circuit. In this method, the first step is to form a polysilicon layer. Then, optionally, a first oxide layer is formed over the polysilicon layer. Next, a first ion-implantation process is performed on the entire polysilicon layer so as to convert it into a lightly-doped polysilicon layer with a first predefined impurity concentration. After this, a second ion-implantation process is performed solely on the predefined electrode part of the polysilicon layer so as to convert this part into a heavily-doped polysilicon layer with a second predefined impurity concentration higher than the first impurity concentration. Subsequently, a selective removal process is performed to remove selected parts of the lightly-doped part and the heavily-doped part of the polysilicon layer.

Abstract: An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Abstract: The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.

Abstract: A metal oxide semiconductor (MOS) device (100) includes a plurality of resistive elements (108) positioned within, and surrounded by, a single active region (106). The resistive elements (108) are each formed within the single active region (106) using conductive film strips (110) as self-aligned masks, thus “bird's beak” is avoided and the accuracy of the resistive elements (108) is improved. The conductive film (110) is formed within the active region (106) directly over a thin gate oxide film (204), rather than a thick field oxide, thus essentially eliminating parasitic leakage between the resistive elements (108), and reducing the substrate area consumed by the device (100).

Abstract: A thin film resistor processing flow solves the problem of accurately incorporating the resistor (80) to be trimmed in an optimized multilayer stack (60,70). This is achieved by measuring the total thickness of the dielectric stack (60) between the silicon substrate and the top of the dielectric stack just prior to the formation of the thin film resistor (80). Then, the thickness of the dielectric stack (60) is adjusted (60+70) to be an odd integer number of laser quarter wavelengths. The thin film resistor (60) is then formed and overlying dielectric (120) is deposited. The thickness of the overlying dielectric (120) may likewise be adjusted (120+130) to be an odd integer number of laser quarter wavelengths.

Abstract: A resistor has a resistor body of polycrystalline silicon and electric terminals arranged on and/or in the resistor body. A resistor portion is thus formed between the terminals, which gives the resistor its resistance. The material in the resistor body is doped with for example boron. In order to block unsaturated silicon bonds in grain boundaries to a sufficient extent and thereby give the resistor a good long-time stability, fluorine atoms are added to the material. They are added in such a high concentration that all of the otherwise unsaturated bonds are coupled to fluorine atoms. Further, it is provided in the manufacture of the resistor that the concentration is maintained at the originally high value. When ion implanting dopants and fluorine atoms it can be accomplished by performing an annealing after implanting dopants at a high temperature and then a further annealing operation at a low temperature after the subsequent implantation of fluorine.

Abstract: The present invention relates to a method of manufacturing an avalanche diode of determined threshold in a substrate of a first conductivity type with a low doping level, including the steps of diffusing in the substrate at least one first region of the first conductivity type; diffusing in the substrate a second region of the second conductivity type protruding from the first region. The opening of a mask of definition of the first region has a lateral extent smaller than the diffusion depth of the first region in the substrate, this lateral extent being chosen all the smaller as the desired avalanche threshold is high.

Abstract: A patterned polysilicon film is formed over a silicon substrate with an interlayer insulating film therebetween. Then heavily doped regions as well as a lightly doped region are formed on the polysilicon film. The entire polysilicon film is covered with an SiO2 film. The polysilicon film is hydrogenated, while an SiNx film is formed over the entire SiO2 film, by LPCVD using a gas comprising nitrogen and hydrogen.

Abstract: A manufacturing process that includes, in succession: depositing a gate oxide layer on a silicon substrate defining a transistor area and a resistor area; depositing a multicrystal silicon layer on the gate oxide layer; removing selective portions of the multicrystal silicon layer to form a gate region over the transistor area and a protective region completely covering the resistor area; forming source and drain regions in the transistor area, laterally to the gate region; forming silicide regions on and in direct contact with the source and drain regions, the gate region and the protective region; removing selective portions of the protective region to form a delimitation ring; and implanting ionic dopants in the resistor area, inside the area defined by the protective ring, to form a lightly doped resistor which has no silicide regions directly on it.

Abstract: A method of forming a high polysilicon resistor over a dielectric layer, comprising the following steps. A polysilicon resistor over a semiconductor structure is provided. The polysilicon resistor has a doped polysilicon layer having a first voltage coefficient of resistance and grain boundaries having a first trapping density. A to a first level of DC current is provided for a predetermined duration through the doped polysilicon layer to stress the doped polysilicon layer to partially melt the doped polysilicon layer without causing breakdown of the doped polysilicon layer. The to a first level of DC current is removed to allow recrystallization of the melted doped polysilicon layer, whereby the recrystallized doped polysilicon layer has a second voltage coefficient of resistance less than the first voltage coefficient of resistance and grain boundaries having a second trapping density that is less than the first trapping density. This makes the Rs of the polysilicon to be stable and saturated.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: A new method of forming a polysilicon resistor having precisely controlled resistance by using a thin silicon nitride cap over the polysilicon resistor is described. A dielectric layer is provided on a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer and patterned to form a polysilicon resistor. A silicon nitride capping layer having a thickness of not more than 100 Angstroms is deposited overlying the polysilicon resistor and dielectric layer. An interlevel dielectric layer is deposited overlying the silicon nitride capping layer. The substrate is annealed thereby densifying the silicon nitride capping layer. A self-aligned contact opening may be made through the interlevel dielectric layer, the silicon nitride capping layer, and the dielectric layer to underlying device structures. The capping silicon nitride layer is thin enough not to act as an etch stop in the self-aligned contact etching. The contact opening is filled with a conducting layer.

Abstract: This method forms structures with different resistance values from a single polysilicon film formed on a substrate. Form a hard masking layer on the polysilicon film. Form a photoresist mask over the hard masking layer. Partially etch the hard masking layer through the photoresist mask to reduce the thickness of the polysilicon while leaving the remainder of the hard masking layer with the original thickness. The thickness is reduced in locations where a low resistance is to be located in the polysilicon film. Then dope the polysilicon layer through the hard masking layer with variable doping as a function of the reduced thickness and the original thickness of the hard masking layer.

Abstract: A MOS transistor with a self-aligned silicide and a lightly doped drain ballast resistor for ESD protection on a semiconductor substrate is formed with the method in the present invention. The ESD protection devices in a ESD protective region are formed at the same time with the forming of the NMOS, PMOS, or both in a functional region. The transistors with a lightly doped drain (LDD) structure and an ultra-shallow junction can be manufactured. The short channel effect and it's accompanying hot carrier effect is eliminated. ESD damage from external connections to the integrated circuits are kept from the densely packed devices. The self-aligned silicide (salicide) technology employed in the present invention for forming low resistance contacts provides high operation speed with low heat generation. Integrated circuits with ESD hardness and high circuit operation speed of the functional devices are provided by the semiconductor manufacturing process employing the method disclosed.

Abstract: A diffusion resistor is provided that utilizes the block mask to cover only the intrinsic polysilicon gate region. The n-type source/drain doping is implanted in the contact regions, but not in the intrinsic polysilicon gate region. A N-type (or P-type) diffusion resistor in P-well (or N-well) is provided that utilizes a block mask to cover only the intrinsic polysilicon gate region. The N-type (or P-type) source/drain doping is implanted in the contact regions but not in the intrinsic polysilicon gate region. The P-well (or N-well) block mask is used to keep the P-well (or N-well) from forming under the buried resistor. This makes the parasitic capacitance of the diffusion junction very low. Also provided is a buried capacitor and method of making both a buried resistor and a buried capacitor.

Abstract: A method of making an IGFET and a protected resistor includes providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the gate and the diffused resistor, forming a masking layer over the insulating layer that covers the resistor region and includes an opening above the active region, applying an etch using the masking layer as an etch mask so that unetched portions of the insulating layer over the active region form spacers in close proximity to opposing sidewalls of the gate and an unetched portion of the insulating layer over the resistor region forms a resistor-protect insulator, and forming a source and a drain in the active region. In this manner, a single insulating layer provides both sidewall spacers for the gate and a resistor-protect insulator for the diffused resistor.

Abstract: A method of making an IGFET with a selectively doped gate in combination with a protected resistor includes the steps of providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the active region and the resistor region, forming a masking layer over the insulating layer that includes an opening above a first portion of the gate and covers the resistor region and a second portion of the gate, applying an etch using the masking layer as an etch mask to remove the insulating layer above the first portion of the gate so that an unetched portion of the insulating layer forms a gate-protect insulator over the second portion of the gate and another unetched portion of the insulating layer forms a resistor-protect insulator over the diffused resistor, and forming a source and a drain in the active region including at least partially doping the source and the drain during

Abstract: FIG. 5b shows a first thin film resistor 14 formed by direct etching or lift off on a first dielectric layer 12 that covers an integrated circuit (not shown) in a silicon substrate 10. A patterned layer of photoresist covers a portion of the second thin film resistor material 30. The second thin film resistor material 30 is different from the first thin film resistor material 14. The exposed portion of the second thin film resistor material 30 is removed to leave first and second thin film resistors on the first dielectric layer 12.

Abstract: This invention provides a diffusion resistor structure including a resistor-shaped diffusion having electrically integrated at opposite ends a first silicided contact area and a second silicided contact area. Polysilicon and oxide layers, or only an oxide layer, reside above a body region of the diffusion. The method provides for formation of the diffusion resistor with silicided contacts by utilizing a diffusion barrier layer which prevents diffusion into an overlying polysilicon layer when a subsequent dopant out diffusion step is performed. Selective etching is then utilized to remove the undoped polysilicon layer, leaving a polysilicon cap over the body region of the diffusion. A second region of the diffusion comprises the first contact area and second contact area, which are silicided once the body region is protected.

Abstract: A low-concentration diffused region is created on a region of a semiconductor substrate reserved for the creation of a diffused-region resistor, and after a mask creation film has been created on the surface of the semiconductor substrate, a doping mask is created to cover part of the region reserved for the creation of a diffused-region resistor. Subsequently, a high-concentration diffused layer is created on the region reserved for the creation of a diffused-region resistor except the part covered by the doping mask by using an impurity doping technique. Then, after a silicide creating mask has been created from the mask creation film by means of an etching technique using the doping mask as an etching mask, the doping mask is removed. Later on, a silicide layer is created selectively on the high-concentration diffused layer. In addition, this method can be applied also to a method of creating a diffused layer in a CMOS process.