Abstract: A method of fabricating a gate electrode having dual gate insulating film includes the steps of sequentially providing a substrate having a first portion and a second portion, forming a first insulating film on the first portion of substrate, a first conductive film on the first insulating film and a second insulating film on the first conductive film, forming a third insulating film on the second portion of the substrate, forming a second conductive film on the second and the third insulating films, and patterning the first and the second conductive film to form a gate electrode.

Abstract: A method of forming a buried plate electrode for a trench capacitor of a semiconductor memory device is provided. Trenches are formed in a semiconductor substrate and a dopant source film is formed on the sidewalls and bottom walls of the trenches. A resist is formed on the dopant source film which fills in the trenches. The resist is recessed to remain in the trenches at a level which is below the surface of the semiconductor substrate. Impurities are implanted into the semiconductor substrate using the recessed resist as a block mask. The dopant source film is etched using the recessed resist as an etching mask and the recessed resist is then removed. The implanted impurities and dopants from the dopant source film are diffused into the semiconductor substrate to form a buried plate electrode.

Abstract: High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, depositing a cap layer of titanium or titanium nitride on the cobalt, depositing a doped film on the cap layer, and performing silicidation, as by rapid thermal annealing, to form a low-resistivity cobalt silicide and to diffuse impurities from the doped film through the cobalt silicide into the substrate to form a junction extending into the substrate a constant depth below the cobalt silicide interface. The formation of source/drain junctions self-aligned to the cobalt silicide/silicon interface prevents junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness, thereby facilitating reliable device scaling.

Abstract: The preferred embodiments of the present invention overcome the limitations of the prior art by providing a method for forming the source/drain diffusions in a vertical transistor structure that results in improved channel length uniformity. In one embodiment, the present invention is used to form source/drain and bitline diffusion structures for use in pillar memory cells. Additionally, in another embodiment, the present invention is used to form source/drain and plate diffusion structures in pillar memory cells. Both preferred embodiments deposit conformal photoresist on a pillar structure and use an off-axis exposure process to recess a dopant source layer to the proper depth along the pillar. The recessed dopant source layer can then be used to form the source/drain/bitlines diffusions or source/drain/plate diffusions in the pillar memory device.

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract: A DRAM cell capacitor is described. Capacitor formation and cell insolation methods are integrated by using existing isolation trench sidewalls to form DRAM capacitors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor.

Abstract: A method for forming a capacitor in a semiconductor body is provided. The method includes the step of forming a trench in a portion of a surface of the semiconductor body. The trench having sidewalls and a bottom. A doped film is deposited over the surface of the semiconductor body. Portions of the doped film are deposited over the sidewalls and bottom of the trench. The semiconductor body is heated and the doped film to produce a liquid phase interface region therebetween while diffusing dopant in the doped film into a region of the semiconductor body. The interface region is cooled to return such interface region to a solid phase. The doped film and the interface region are removed from the semiconductor body while leaving the doped region in the semiconductor body. A dielectric film is deposited over the doped region of the semiconductor body.

Abstract: The method sequence results in a conductive connection between two zones of a first conductivity type. In particular, one of the zones is a source/drain zone of a transistor. Instead of the conventional additional nitride layer, the connection is produced by implanting directly into the third insulation layer, which is present anyway, and by utilizing the fact that the third insulation layer forms the lateral spacers on the gatestack disposed on the region of the second conductivity type.

Abstract: A dynamic random access memory (DRAM) cell is formed with a buried strap which is routed through an isolation trench. This structure frees space in the transfer gate such that the location of the buried strap is not a limiting factor for decreasing the size of DRAM cells.

Abstract: Method for forming three-dimensional device structures comprising a second device having sub-groundrule features formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device. the sub-groundrule feature is formed using mandrel and spacers.

Abstract: A method for forming a contact is disclosed. A buried impurity region of a second conductivity type is formed in a semiconductor substrate of a first conductivity type. First and second well regions of a first and second conductivity types, respectively, are also formed in the semiconductor substrate. The second well region overlaps the first well region and contacts and surrounds the buried impurity region. A surface impurity concentration of the first well region is greater than a surface impurity concentration of the second well region. A contact to the second well region is formed.

Abstract: To produce a silicon capacitor, hole apertures at whose surface a conductive zone (40) is formed by doping and whose surface is provided with a dielectric layer (6) and a conductive layer (7) are generated in an n-doped silicon substrate (1). To compensate for mechanical strains in the silicon substrate (1) brought about by the doping of the conductive zone (40), the conductive zone (40) is additionally doped with germanium which is outdiffused from a germanium-doped layer.

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Abstract: A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell. The electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Abstract: A gate-drain overlapped device, comprising: a first conductive type substrate; a gate insulating film formed on the substrate; a gate comprising a gate conductive line patterned on the gate insulating film, and a conductive layer coated on the gate conductive line and extending to a predetermined length on the gate insulating film; and a drain/source region comprising a second conductive type low density diffusion region in the substrate below the extending area of the conductive layer and a second conductive type high density diffusion region in contact with the low density diffusion region in the substrate, which is significantly improved in the resistance of a polysilicon gate conductive line and in uniform electrical properties.

Abstract: A deep trench DRAM cell is formed on a silicon on isolator (SOI) substrate, with a buried strap formed by outdiffusion of dopant in associated trench node material, for providing an electrical connection between the trench node and the active area of a MOS transfer gate formed in the substrate adjacent the trench in an uppermost portion of the substrate.

Abstract: A trench capacitor with a buried plate is formed with a single etching process by the expedient of filling the trench so formed and lined with diffusion source material with resist by baking and reflowing the resist which also serves to adjust exposure sensitivity of the resist such that exposure and development of the resist removes the resist to a repeatable and uniform depth. Remaining resist allows etching of the diffusion source layer to a very accurate dimension. Thus only a readily formed oxide or TECS layer is needed to confine impurities during diffusion to form the buried plate. An isolation collar can be formed after recess of the fill to avoid formation of step corners and erosion of the isolation collar by repeated fill and etch back processes while permitting maximum capacitance to be achieved for a given trench "footprint".