Abstract: A mechanism is provided for a spin torque transfer random access memory device. A reference layer is disposed on a seed layer. A tunnel barrier is disposed on the reference layer. A free layer is disposed on the tunnel barrier. A cap layer is disposed on the free layer. The free layer includes a magnetic layer and a metal oxide layer, in which the magnetic layer is disposed on the tunnel barrier and the metal oxide layer is disposed on the magnetic layer. A metal material used in the metal oxide layer includes at least one of Ti, Ta, Ru, Hf, Al, La, and any combination thereof.

Abstract: A method of fabricating workpieces includes one or more layers on a substrate that are masked with an ion implantation mask comprising two or more layers. The mask layers include a first mask layer closer to the substrate, and a second mask layer on the first mask layer. The method also comprises ion implanting one or more of the layers on the substrate. Ion implantation may form portions with altered physical properties from the layers under the mask. The portions may form a plurality of non-magnetic regions corresponding to apertures in the mask.

Abstract: A lower electrode film is formed above a substrate. A ferroelectric film is formed above the lower electrode film. An amorphous intermediate film of a perovskite-type conductive oxide is formed above the ferroelectric film. A first upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the intermediate film. The intermediate film is crystallized by carrying out a first heat treatment in an atmosphere containing an oxidizing gas after the formation of the first upper electrode film. After the first heat treatment, a second upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the first upper electrode film, at a temperature lower than the growth temperature for the first upper electrode film.

Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

Abstract: Provided are magnetic memory devices with a perpendicular magnetic tunnel junction. The device includes a magnetic tunnel junction including a free layer structure, a pinned layer structure, and a tunnel barrier therebetween. The pinned layer structure may include a first magnetic layer having an intrinsic perpendicular magnetization property, a second magnetic layer having an intrinsic in-plane magnetization property, and an exchange coupling layer interposed between the first and second magnetic layers. The exchange coupling layer may have a thickness maximizing an antiferromagnetic exchange coupling between the first and second magnetic layers, and the second magnetic layer may exhibit a perpendicular magnetization direction, due at least in part to the antiferromagnetic exchange coupling with the first magnetic layer.

Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction.

Abstract: An all (111) MTJ stack is disclosed in which there are no transitions between different crystalline orientations when going from layer to layer. This is accomplished by providing strongly (111)-textured layers immediately below the MgO tunnel barrier to induce a (111) orientation therein.

Abstract: In one embodiment of the invention, there is provided a method for manufacturing a magnetic memory device, comprising: depositing a carbon layer comprising amorphous carbon on a substrate; annealing the carbon layer to activate dopants contained therein; and selectively etching portions of the carbon layer to forms lines of spaced apart carbon conductors.

Abstract: A semiconductor device includes: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member.

Abstract: The present invention relates to a magnetic tunnel junction device and a manufacturing method thereof. The magnetic tunnel junction device includes: i) a first magnetic layer including a compound having a chemical formula of (A100-xBx)100-yCy; ii) an insulating layer deposited on the first magnetic layer; and iii) a second magnetic layer deposited on the insulating layer and including a compound having a chemical formula of (A100-xBx)100-yCy. The first and second magnetic layers have perpendicular magnetic anisotropy, A and B are respectively metal elements, and C is at least one amorphizing element selected from a group consisting of boron (B), carbon (C), tantalum (Ta), and hafnium (Hf).

Abstract: A thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate, is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer on the CMOS substrate is patterned by either undercut trenches extending into its upper surface or by T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.

Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

Abstract: An integrated voltage regulator substrate or interposer system includes a control system and coupled-magnetic-core inductors. The control system is integrated within a package. The coupled-magnetic-core inductors are integrated in the package. The control system is configured to utilize the coupled-magnetic-core inductors to generate a selected regulated voltage for drastically electrical power consumption saving, especially advantageous for portable, mobile or cloud computing device packages relatively smaller form factor, shorter interconnect path, faster operation speed and broader frequency bandwidth.

Abstract: A method of manufacturing a semiconductor device may include forming a material layer on a substrate, performing a selective oxidation process to form a capping oxide layer on a first surface of the material layer, wherein a second surface of the material layer is not oxidized, and etching the material layer through the second surface to form a material pattern. An etch rate of the capping oxide layer is less than an etch rate of the material layer. A semiconductor device may include a lower electrode on a substrate, a data storage part on a top surface of the lower electrode, an upper electrode on the data storage part, and a capping oxide layer arranged on at least a portion of a top surface of the upper electrode. The capping oxide layer may include an oxide formed by oxidation of an upper surface of the upper electrode.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

Abstract: A ferroelectric capacitor provided with a ferroelectric film (10a) is formed above a semiconductor substrate, and thereafter a wiring (17) directly connected to electrodes (9a, 11a) of a ferroelectric capacitor is formed. Then, a silicon oxide film (18) covering the wiring (17) is formed. As the silicon oxide film (18), a film which has processability higher than that of an aluminum oxide film is formed. Besides, a degree of damage that occurs in the ferroelectric capacitor when the insulating film is formed is equal to or less than that when an aluminum oxide film is formed.

Abstract: A method of arranging a diamagnetic rod includes levitating a diamagnetic rod above a contact line at which a first magnet contacts a second magnet, the first magnet and the second magnet having diametric magnetization in a direction perpendicular to the contact line.

Abstract: A method for forming MRAM (magnetoresistive random access memory) devices is provided. A bottom electrode assembly is formed. A magnetic junction assembly is formed, comprising, depositing a magnetic junction assembly layer over the bottom electrode assembly, forming a patterned mask over the magnetic junction assembly layer, etching the magnetic junction assembly layer to form the magnetic junction assembly with gaps, gap filling the magnetic junction assembly, and planarizing the magnetic junction assembly. A top electrode assembly is formed.

Abstract: A magnetic memory device and method of manufacturing the same are provided. The magnetic memory device can include a first vertical magnetic pattern on a substrate, a second vertical magnetic pattern on the first vertical magnetic pattern, and a tunnel barrier pattern disposed between the first vertical magnetic pattern and the second vertical magnetic pattern. The first vertical magnetic pattern can include a first pattern on the substrate, a second pattern on the first pattern, and an exchange coupling pattern between the first pattern and the second pattern. The first pattern can comprise an amorphous magnetic substance and a component comprising at least one of platinum, palladium, and nickel.

Abstract: Provided is a heat treatment apparatus including a treatment chamber housing a silicon substrate, a heater being provided in the treatment chamber and heating the silicon substrate, and an atmosphere adjustment mechanism reducing a concentration of oxygen contained in an atmosphere inside the treatment chamber to less than an oxygen concentration in the air. The atmosphere adjustment mechanism is provided with an oxygen trap, for example.

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract: Embodiments are directed to providing a spin hall effect (SHE) assisted spin transfer torque magnetic random access memory (STT-MRAM) device by coupling a magnetic tunnel junction (MTJ) to a SHE material, and coupling the SHE material to a transistor. Embodiments are directed to a spin transfer torque magnetic random access memory (STT-MRAM) device comprising: a magnetic tunnel junction (MTJ) coupled to a spin hall effect (SHE) material, and a transistor coupled to the SHE material.

Abstract: Provided are a magneto resistive element and a method of manufacturing the same, and in particular, a magneto resistive element and a method of manufacturing the same that may be applied to a digitizer sensing panel. The magneto resistive element includes a substrate, a first electrode disposed on the substrate, a first hole transport layer disposed on the first electrode, a first magneto resistive layer disposed on the first hole transport layer, wherein the first magneto resistive layer comprises an organic material, a first transport layer disposed on the first magneto resistive layer, a second magneto resistive layer disposed on the first transport layer, wherein the second magneto resistive layer comprises an organic material, a first electron transport layer to disposed on the second magneto resistive layer, and a second electrode disposed on the first electron transport layer.

Abstract: A magnetoresistive structure includes a substrate and a patterned stack structure. The substrate has a back surface and a front surface having a step portion. The patterned stack structure is on the step portion of the front surface and comprises a magnetoresistive layer, a conductive cap layer and a dielectric hard mask layer. The step portion has a top surface parallel to the back surface, a bottom surface parallel to the back surface and a step height joining the top surface and bottom surface and being not parallel to the back surface.

Abstract: Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

Abstract: The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.

Abstract: A magnetic memory element includes: a first magnetization free layer configured to be composed of ferromagnetic material with perpendicular magnetic anisotropy; a reference layer configured to be provided near the first magnetization free layer; a non-magnetic layer configured to be provided adjacent to the reference layer; and a step formation layer configured to be provided under the first magnetization free layer. The first magnetization free layer includes: a first magnetization fixed region of which magnetization is fixed, a second magnetization fixed region of which magnetization is fixed, and a magnetization free region configured to be connected with the first magnetization fixed region and the second magnetization fixed region. The first magnetization free layer has at least one of a step, a groove and a protrusion inside.

Abstract: According to one embodiment, a magnetoresistive element comprises a first magnetic layer having a magnetization direction invariable and perpendicular to a film surface, a tunnel barrier layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel barrier layer and having a magnetization direction variable and perpendicular to the film surface. The first magnetic layer includes an interface layer formed on an upper side in contact with a lower portion of the tunnel barrier layer, and a main body layer formed on a lower side and serving as an origin of perpendicular magnetic anisotropy. The interface layer includes a first area provided on an inner side and having magnetization, and a second area provided on an outer side to surround the first area and having magnetization smaller than the magnetization of the first area or no magnetization.

Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

Abstract: Embodiments relate to xMR sensors, in particular AMR and/or TMR angle sensors with an angle range of 360 degrees. In embodiments, AMR angle sensors with a range of 360 degrees combine conventional, highly accurate AMR angle structures with structures in which an AMR layer is continuously magnetically biased by an exchange bias coupling effect. The equivalent bias field is lower than the external rotating magnetic field and is applied continuously to separate sensor structures. Thus, in contrast with conventional solutions, no temporary, auxiliary magnetic field need be generated, and embodiments are suitable for magnetic fields up to about 100 mT or more. Additional embodiments relate to combined TMR and AMR structures. In such embodiments, a TMR stack with a free layer functioning as an AMR structure is used. With a single such stack, contacted in different modes, a high-precision angle sensor with 360 degrees of uniqueness can be realized.

Abstract: A STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having a dielectric thermal buffer layer between a thin top electrode of the MTJ element and a bit line, and a bit-line VIA electrically connecting the top electrode and the bit line having a vertical distance away from the location of the MTJ stack. In a laser thermal annealing, a short wavelength of a laser has a shallow thermal penetration depth and a high thermal resistance from the bit line to the MTJ stack only causes a temperature rise of the MTJ stack being much smaller than that of the bit line. As the temperature of the MTJ element during the laser thermal annealing of bit line copper layer is controlled under 300-degree C., possible damages on MTJ and magnetic property can be avoided.

Abstract: A power module includes a first substrate having a metallized side, a second substrate spaced apart from the first substrate and having a metallized side facing the metallized side of the first substrate, and a semiconductor die interposed between the first and second substrates. The semiconductor die has a first side connected to the metallized side of the first substrate and an opposing second side connected to the metallized side of the second substrate. The power module further includes a sensor connected to the metallized side of the first substrate and galvanically isolated from the metallized side of the second substrate. The sensor is aligned with a first metal region of the metallized side of the second substrate so that the sensor can measure a magnetic field generated by the first metal region.

Abstract: A semiconductor structure for electromagnetic induction sensing and a method for manufacturing the same are provided: forming the Hall sensor in a first semiconductor fabrication; forming the passivation layer above the Hall sensor to cover the Hall sensor according to the first semiconductor fabrication; and forming the current-carrying layer above the passivation layer in a second semiconductor fabrication to form the semiconductor structure for electromagnetic induction sensing. The current-carrying layer carries the current to be sensed; and the Hall sensor senses the magnetic field generated. The Hall sensor generates a voltage or a current signal proportional to the strength of the current to be sensed.

Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

Abstract: A perpendicular STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having local magnetic shielding. As an external perpendicular magnetic field exists, the permeable dielectric layers, the permeable bit line and the permeable bottom electrode are surrounding and have capability to absorb and channel most magnetic flux surrounding the MTJ element instead of penetrate through the MTJ element. Thus, magnetization of a recording layer can be less affected by the stray field during either writing or reading, standby operation.

Abstract: A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer.

Abstract: A magnetic tunnel junction device includes a first electrode having a curved top surface, a magnetic tunnel junction layer formed along the top surface of the first electrode, and a second electrode formed on the magnetic tunnel junction layer.

Abstract: A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.

Abstract: A method for manufacturing a ferroelectric film including the steps of forming a burnable material film containing hydrogen of not less than 1% by weight on a substrate; forming an amorphous thin film including a ferroelectric material on the burnable material film; and oxidizing and crystallizing the amorphous thin film while supplying hydrogen to the amorphous thin film by burning the burnable material film through heating of the burnable material film and the amorphous thin film in an oxygen atmosphere, to thereby form a first ferroelectric film on the substrate.

Abstract: A semiconductor device includes a pinned layer having a magnetic direction permanently set to a first direction, a tunnel insulating layer arranged on the pinned layer, a free layer arranged on the tunnel insulating layer and having a changeable magnetic direction, and a magnetic induction layer formed to surround the pinned layer and have a magnetic direction permanently set to a second direction different from the first direction.

Abstract: The present application provides a method for packaging a display device and an apparatus therefor. The method includes: providing a display device, a platform, a laser beam and a magnetic mechanism; wherein the display device includes a light emitting element, the light emitting element includes at least one effective light emitting region thereon and is prepared on an upper surface of a glass substrate, the glass substrate is bonded to a glass cover plate via a sealing adhesive layer; the display device is placed on the platform; the laser beam penetrates the glass cover plate and focuses on the sealing adhesive layer to sinter the sealing adhesive layer; and the magnetic mechanism clamps the glass cover plate and the glass substrate from top to bottom and applies a uniform pressing force on the effective light emitting region of the display device.

Abstract: A perpendicular STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having permeable dielectric layer. As an external perpendicular magnetic field exists, the permeable dielectric layers have capability to absorb and channel most magnetic flux surrounding the MTJ element instead of penetrate through the MTJ element.

Abstract: A method for manufacturing a magnetoresistance component is provided. A substrate is provided. A circuit structure layer including an interconnect structure is formed on the substrate, wherein the interconnect structure comprises a metal pad. A dielectric layer is formed on the circuit structure. A metal damascene structure is formed in the dielectric layer. A patterned magnetoresistance component is formed above the metal damascene structure to electrically connect to the metal damascene structure.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: A thermally assisted magnetic memory cell device includes a substrate, a first electrode disposed on the substrate, a magnetic tunnel junction disposed on the first electrode, a second electrode disposed on the magnetic tunnel junction, a conductive hard mask disposed on the second electrode and a parallel shunt path coupled to the magnetic tunnel junction, thereby electrically coupling the first and second electrodes.

Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.

Abstract: According to one embodiment, a method for patterning a medium having a patterned hard mask applied thereon is disclosed herein. The patterned hard mark includes a plurality of apertures exposing portions of the medium. The method includes directing ions toward the medium, implanting a portion of the ions into the exposed portions of the medium, removing a layer of the patterned hard mask with another portion of the ions, and depositing hard mask material onto the patterned hard mask. Depositing hard mask material onto the exposed portions of the medium may follow implantation of the portion of the ions into the exposed portions of the medium.