Abstract: An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.

Abstract: Various embodiments provide an electronic device, wherein the electronic device comprises a mounting surface configured to mount the electronic device to an external structure and having a first size; a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode; wherein the first size is at least three times the second size.

Abstract: Devices, methods, and systems for sensing current are described herein. One device includes a first electrode, a second electrode, and a tunneling magnetoresistance material between the first and second electrodes.

Abstract: Manufacturing a MRAM device may include removing etch residues from a magnetic tunnel junction (MTJ) pattern in the presence of an atmosphere. The removing may include applying a cleaning solution to one or more surfaces of the MTJ pattern. Manufacturing the MRAM device may include removing an oxide layer based on sputter etching of the MTJ pattern. The etch residues may be removed such that the oxide layer is formed. Removing the etch residues may include applying a cleaning solution to the MTJ pattern. The etch residues may be removed in the presence of an atmosphere. The MTJ pattern may be formed based on patterning an MTJ layer in a vacuum state such that the etch residues are formed on a surface of the MTJ pattern.

Abstract: By manufacturing magnetoresistive devices using low-k dielectric materials as the inter-layer dielectrics and higher-k dielectric materials for hard masks and encapsulation, the overall dielectric constant characteristics of the magnetoresistive devices can be kept lower, thereby decreasing capacitance and allowing for higher speed operations. Elimination or reduction of residual higher-k dielectric material through stripping or other processes minimizes “islands” of higher-k dielectric material that can detract from overall dielectric constant performance. One or more masking and one or more etching steps can be used to form the devices either with or without the additional stripping of the higher-k material.

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

Abstract: Methods for creating barrier layers in a III-V electron channel to reduce band-to-band leakage current and the resulting devices are disclosed. Embodiments include forming a fin channel portion comprising a III-V material, on a barrier layer; forming undoped InP semiconductor spacers at opposite ends of the fin channel portion on the barrier layer; forming S/D regions adjacent the undoped InP semiconductor spacers on the barrier layer; and forming a high-k/metal gate over the fin channel portion and undoped InP semiconductor spacers.

Abstract: There is provided a method for manufacturing a niobate-system ferroelectric thin film device, including: a lower electrode film formation step of forming a lower electrode film on a substrate; a niobate-system ferroelectric thin film formation step of forming a niobate-system ferroelectric thin film on the lower electrode film; an etch mask formation step of forming a desired etch mask pattern on the niobate-system ferroelectric thin film; and a ferroelectric thin film etching step of forming a desired fine pattern of the niobate-system ferroelectric thin film by wet etching using an etchant including an aqueous alkaline solution of a chelating agent.

Abstract: In one embodiment of the invention, there is provided a method for manufacturing a magnetic memory device, comprising: depositing a carbon layer comprising amorphous carbon on a substrate; annealing the carbon layer to activate dopants contained therein; and selectively etching portions of the carbon layer to forms lines of spaced apart carbon conductors.

Abstract: In a plasma etching method of plasma-etching a sample which has a first magnetic film, a second magnetic film disposed above the first magnetic film, a metal oxide film disposed between the first magnetic film and the second magnetic film, a second metal film disposed over the second magnetic film and forming an upper electrode, and a first metal film disposed below the first magnetic film and forming a lower electrode, the plasma etching method includes the steps of: a first process for etching the first magnetic film, the metal oxide film, and the second magnetic film by using carbon monoxide gas; and a second process for etching the sample by using mixed gas of hydrogen gas and inactive gas after the first process. In this case, the first metal film is a film containing therein tantalum.

Abstract: Methods of manufacture of integrated multi-layer magnetic films for use in passive devices in microelectronic applications. Soft ferromagnetic materials exhibiting high permeability and low coercivity are laminated together with insulating layers interposed. Electrical conductors coupled to interconnects are magnetically coupled to magnetic film layers to engender an inductor (self and mutual). Soft ferromagnetic materials are provided in an alternating array of parallel plate capacitors. Each alternating magnetic film is electrically coupled to either a primary or secondary electrical conductor interconnects and separated by an electrically insulating dielectric material. Alternatively, each alternating magnetic layer comprises an induced anisotropy material, which can also be combined with coiled conductor giving rise to a hybrid inductive/capacitive device. Also, soft ferromagnetic material are also selected and tuned to provide for FMR notch filtering.

Abstract: A planar STT-MRAM includes apparatus, made by a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a ferromagnetic recording layer forming a flux closure with a self-aligned ferromagnetic soft adjacent layer which has an electric field enhanced perpendicular anisotropy through an interface interaction with a dielectric functional layer. The energy switch barrier of the soft adjacent layer is reduced under an electric field along a perpendicular direction with a proper voltage on a digital line from a control circuitry; accordingly, the in-plane magnetization of the recording layer is readily reversible in a low spin-transfer switching current.

Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.

Abstract: Integrated multi-layer magnetic films for use in passive devices in microelectronic applications and methods of manufacture thereof. Soft ferromagnetic materials exhibiting high permeability and low coercivity are laminated together with insulating layers interposed. Electrical conductors coupled to interconnects are magnetically coupled to magnetic film layers to engender an inductor (self and mutual). Soft ferromagnetic materials are provided in an alternating array of parallel plate capacitors. Each alternating magnetic film is electrically coupled to either a primary or secondary electrical conductor interconnects and separated by an electrically insulating dielectric material. Alternatively, each alternating magnetic layer comprises an induced anisotropy material, which can also be combined with coiled conductor giving rise to a hybrid inductive/capacitive device. Also, soft ferromagnetic material are also selected and tuned to provide for FMR notch filtering.

Abstract: Methods of manufacturing a magnetic memory device including forming a lower magnetic layer, a tunnel barrier layer, and an upper magnetic layer on a substrate, forming a magnetic tunnel junction (MTJ) pattern by patterning the lower magnetic layer, the tunnel barrier layer, and the upper magnetic layer, forming a first insulating layer exposing an upper surface of the MTJ pattern, forming a polymer pattern on the exposed upper surface of the MTJ pattern, forming a second insulating layer exposing an upper surface of the polymer pattern, removing the polymer pattern to form a cavity in the second insulating layer, the cavity exposing the upper surface of the MTJ pattern, and forming a metal line by filling the cavity with a conductive metal.

Abstract: A method of manufacturing a magnetic memory device may include forming a lower magnetic layer, a tunnel barrier layer, and an upper magnetic layer on a substrate, forming a magnetic tunnel junction pattern by etching a stacked structure including the lower magnetic layer, the tunnel barrier layer, and the upper magnetic layer, forming a boron-absorption layer covering the magnetic tunnel junction pattern, and performing a heat treatment process so that boron included in the upper and lower magnetic layers may be absorbed by the boron-absorption layer. The heat treatment process may be undertaken in a gaseous atmosphere including at least one of hydrogen, oxygen, and nitrogen.

Abstract: Direct growth of graphene on Co3O4(111) at 1000 K was achieved by molecular beam epitaxy from a graphite source. Auger spectroscopy shows a characteristic sp2 carbon lineshape, at average carbon coverages from 0.4-3 monolayers. Low energy electron diffraction (LEED) indicates (111) ordering of the sp2 carbon film with a lattice constant of 2.5 (±0.1) ? characteristic of graphene. Six-fold symmetry of the graphene diffraction spots is observed at 0.4, 1 and 3 monolayers. The LEED data also indicate an average domain size of ˜1800 ?, and show an incommensurate interface with the Co3O4(111) substrate, where the latter exhibits a lattice constant of 2.8 (±0.1) ?. Core level photoemission shows a characteristically asymmetric C(1s) feature, with the expected lr to lr* satellite feature, but with a binding energy for the three monolayer film of 284.9 (±0.1) eV, indicative of substantial graphene-to-oxide charge transfer.

Abstract: According to one embodiment, a magnetic memory device includes a stack structure including a first magnetic layer variable in magnetization direction, a second magnetic layer fixed in magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, the first magnetic layer including a first layer, a second layer, and a third layer between the first layer and the second layer and containing magnesium (Mg), iron (Fe), and oxygen (O), the second layer being between the nonmagnetic layer and the third layer, wherein a thickness of the second layer is greater than that of the first layer, and the thickness of the first layer is greater than that of the third layer.

Abstract: A device includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.

Abstract: A magnetic tunnel junction (MTJ) and methods for fabricating a MTJ are described. An MTJ includes a fixed layer and a barrier layer on the fixed layer. Such an MTJ also includes a free layer interfacing with the barrier layer. The free layer has a crystal structure in accordance with the barrier layer. The MTJ further includes an amorphous capping layer interfacing with the free layer.

Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.

Abstract: A semiconductor memory device includes a cell gate dielectric layer and a cell gate electrode disposed in a gate recess region crossing a cell active portion of a substrate, first and second doped regions disposed in the cell active portion at both sides of the gate recess region, respectively, at least one interlayer insulating layer covering the substrate, a data storage element electrically connected to the second doped region through a contact plug penetrating the at least one interlayer insulating layer, a mold layer covering the data storage element, and a bit line disposed in a cell groove formed in the mold layer. The bit line is in direct contact with a top surface of the data storage element.

Abstract: The present invention discloses highly sensitive magnetic heterojunction device consisting of a composite comprising ferromagnetic (La0.66Sr0.34MnO3) LSMO layer with ultra-thin ferrimagnetic CoFe2O4 (CFO) layer capable of giant resistive switching (RS) which can be tuned at micro tesla magnetic field at room temperature.

Abstract: According to one embodiment, a manufacturing method of a magnetoresistive memory device includes forming a first magnetic layer on a substrate, forming a magnetoresistive effect element on the first magnetic layer, forming a mask on a part of the magnetoresistive effect element, selectively etching the magnetoresistive effect element using the mask, forming a sidewall insulating film on a sidewall of the magnetoresistive effect element exposed by the etching, selectively etching the first magnetic layer using the mask and the sidewall insulating film and forming a deposition layer containing a magnetic material on a sidewall of the first magnetic layer and the sidewall insulating film, and introducing ions into the deposition layer.

Abstract: Provided are a magnetic memory device and a method of fabricating the same. The device may include a magnetic tunnel junction including a lower magnetic structure, an upper magnetic structure, and a tunnel barrier interposed therebetween. The tunnel barrier may have a width greater than that of the lower magnetic structure.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode.

Abstract: A magnetic tunnel junction (MTJ) device in a magnetoresistive random access memory (MRAM) and method of making the same are provided to achieve a high tunneling magnetoresistance (TMR), a high perpendicular magnetic anisotropy (PMA), good data retention, and a high level of thermal stability. The MTJ device includes a first free ferromagnetic layer, a synthetic antiferromagnetic (SAF) coupling layer, and a second free ferromagnetic layer, where the first and second free ferromagnetic layers have opposite magnetic moments.

Abstract: A solid state light (“SSL”), a solid state emitter (“SSE”), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging substrate having an electrical contact and a light emitting structure having a front side and a back side. The back side of the light emitting structure is superimposed with the electrical contact of the packaging substrate. The SSL can further include a temperature control element aligned with the light emitting structure and the electrical contact of the packaging substrate.

Abstract: A light-emitting device capable of suppressing variation in luminance among pixels is provided. A light-emitting device includes a pixel and first and second circuits. The first circuit has a function of generating a signal including a value of current extracted from the pixel. The second circuit has a function of correcting an image signal by the signal. The pixel includes at least a light-emitting element and first and second transistors. The first transistor has a function of controlling supply of the current to the light-emitting element by the image signal. The second transistor has a function of controlling extraction of the current from the pixel. A semiconductor film of each of the first and second transistors includes a first semiconductor region overlapping with a gate, a second semiconductor region in contact with a source or a drain, and a third semiconductor region between the first and second semiconductor regions.

Abstract: An integrated circuit containing hydrogen permeable dummy vias configured in a linear or rectangular array and symmetrically positioned over a component in the integrated circuit. An integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.

Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

Abstract: A non-volatile memory device structure. The non-volatile memory device structure comprises a first electrode formed from a first metal material, a resistive switching element overlying the first electrode. The resistive switching element comprises a metal oxide material characterized by one or more oxygen deficient sites. The device includes a second electrode overlying the resistive switching layer, the second electrode being formed from a second metal material. The second electrode is made from a noble metal. The one or more oxygen deficient sites are caused to migrate from one of the first electrode or the second electrode towards the other electrode upon a voltage applied to the first electrode or the second electrode. The device can have a continuous change in resistance upon applying a continuous voltage ramp, suitable for an analog device. Alternatively, the device can have a sharp change in resistance upon applying the continuous voltage ramp, suitable for a digital device.

Abstract: According to one embodiment, a magnetic memory device includes a first stack structure including a first magnetic layer, and a first nonmagnetic layer provided on the first magnetic layer, a second stack structure including a second magnetic layer provided on the first nonmagnetic layer, a second nonmagnetic layer provided on the second magnetic layer, and a top conductive layer provided on the second nonmagnetic layer, and a sidewall conductive layer provided on a sidewall of the second stack structure.

Abstract: Embodiments of the present disclosure generally provide a method and apparatus for forming an IGZO active layer within a thin film transistor (TFT) device. In one embodiment, a method is provided for forming an IGZO active layer on a dielectric surface using a PECVD deposition process. In one embodiment, a method is provided for pretreating and passivating the dielectric surface for receiving the PECVD formed IGZO layer. In another embodiment, a method is provided for treating a PECVD formed IGZO layer after depositing said layer. In another embodiment, a method is provided for forming a multi-layer or complex layering structure of IGZO, within a PECVD processing chamber, for optimizing TFT electrical characteristics such as carrier density, contact resistance, and gate dielectric interfacial properties. In yet another embodiment, a method is provided for forming integrated layers for a TFT including IGZO within an in-situ environment of a cluster tool.

Abstract: Provided is a semiconductor device having improved reliability. Over a semiconductor substrate, a first coil is formed via a first insulating film. A second insulating film is formed so as to cover the first insulating film and the first coil. Over the second insulating film, a pad is formed. Over the second insulating film, a multi-layer film having an opening exposing a part of the pad is formed. Over the multi-layer insulating film, a second coil is formed. The second coil is placed over the first coil. The second and first coils are magnetically coupled to each other. The multi-layer film includes a silicon dioxide film, a silicon nitride film over the silicon dioxide film, and a resin film over the silicon nitride film.

Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

Abstract: A resistive nonvolatile storage device includes a first interlayer insulating layer provided above a substrate, a contact hole penetrating through the first interlayer insulating layer, a contact layer wholly covering a bottom surface and a sidewall surface of the contact hole and extending to at least partially cover an upper surface of the first interlayer insulating layer, a contact plug filled in the contact hole, an upper surface of the contact plug being positioned below an upper surface of the contact layer, a lower electrode provided on both the contact plug and the contact layer that is provided on the part of the upper surface of the first interlayer insulating layer, and a resistance change layer provided on the lower electrode, and an upper electrode that is provided on the resistance change layer.

Abstract: CMP selectivity, removal rate, and uniformity are controlled both locally and globally by altering electric charge at the wafer surface. Surface charge characterization is performed by an on-board metrology module. Based on a charge profile map, the wafer can be treated in an immersion bath to impart a more positive or negative charge overall, or to neutralize the entire wafer before the CMP operation is performed. If charge hot spots are detected on the wafer, a charge pencil can be used to neutralize localized areas. One type of charge pencil bears a tapered porous polymer tip that is placed in close proximity to the wafer surface. Films present on the wafer absorb ions from, or surrender ions to, the charge pencil tip, by electrostatic forces. The charge pencil can be incorporated into a CMP system to provide an in-situ treatment prior to the planarization step or the slurry removal step.

Abstract: Segregants for magnetic recording layers and materials for intermediate layers underlying the magnetic recording layers are provided for improved heat assisted magnetic recording (HAMR) media. One such HAMR medium includes a substrate, a heat sink layer on the substrate, an underlayer on the heat sink layer, an intermediate layer of TiON, VON, CrON, TiOC, VOC, TiONC, and/or combinations thereof, on the underlayer, and a magnetic recording layer of FePt on the intermediate layer. The magnetic recording layer further includes three sublayers, each having a different segregant. The segregant of the first magnetic recording sublayer on the intermediate layer includes AgBN, AgCN, AgBNC, AgB2O3, AgMoO3, AgV2O5, B2O3, MoO3, V2O5, and/or combinations thereof.

Abstract: When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition. The process temperature of the deposition process may be chosen to perform—potentially in combination with further subsequently performed process steps—a sufficient diffusion of deuterium to the gate dielectrics.

Abstract: Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.

Abstract: A semiconductor device includes a substrate and a gate structure over the substrate. The gate structure includes a dielectric portion and an electrode portion that is disposed over the dielectric portion. The dielectric portion includes a carbon-doped high dielectric constant (high-k) dielectric layer over the substrate and a carbon-free high-k dielectric layer adjacent to the electrode portion.

Abstract: A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

Abstract: One method includes forming an anti-ferromagnetic layer on a substrate. A ferromagnetic layer may be formed on the anti-ferromagnetic layer. The ferromagnetic layer includes a first, second and third portions where the second portion is located between the first and third portions. A first ion irradiation is performed to only one portion of the ferromagnetic layer. A second ion irradiation is performed to another portion of the ferromagnetic layer.

Abstract: The embodiments herein relate to methods and apparatus for depositing an encapsulation layer over memory stacks in MRAM and PCRAM applications. The encapsulation layer is a titanium dioxide (TiO2) layer deposited through an atomic layer deposition reaction. In some embodiments, the encapsulation layer may be deposited as a bilayer, with an electrically favorable layer formed atop a protective layer. In certain implementations, gaps between neighboring memory stacks may be filled with titanium oxide, for example through an atomic layer deposition reaction or a chemical vapor deposition reaction.

Abstract: An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.

Abstract: A method of removing a damaged magnetic layer at the sidewall of MTJ edge is provided to form damage-free MRAM cell. In this method, the MTJ film stack outside the Ta hard mask protected area is first etched by high-power magnetic reactive ion etch (RIE) using methanol (CH3OH) or Co & NH3 as etchant gases. Then a very mild chemical vapor trimming (CVT) process is used to remove a damaged layer (by the high power RIE) from the MTJ sidewall followed by an in-situ edge passivation with Si nitride (SiN) layer formed by PECVD. The MRAM cell formed by such method will have higher magnetoresistance with good device performance and better reliability.

Abstract: A method for manufacturing a spin injector device, comprising the following steps of: a) forming a metal protection layer on a face of a substrate, so as to restrict or prevent oxidation and/or contamination of said face by its environment, the face being magnetic and electrically conductive, the protection layer being of a diamagnetic or paramagnetic nature; b) forming an upper layer onto the protection layer, able to promote a spin bias of electronics sates in the vicinity of the Fermi level of the interface between the protection layer and the upper layer according to an amplitude and a spin referential frame which are defined by the magnetism of the substrate and/or of the face of the substrate, the upper layer being an organic layer of which one or more molecular sites have, in contact with the protection layer, a paramagnetic moment.

Abstract: A piezoelectric thin film which is of a perovskite type having a tetragonal crystal structure, the tetragonal crystal having a degree of (100) orientation of 80% or higher. The piezoelectric thin film is constituted of a lead lanthanum zirconate titanate (PLZT) which is a lead zirconate titanate (PZT) in which some of the lead has been replaced with lanthanum.