Abstract: According to one embodiment, an alignment measurement system is configured to measure a position of a mark having the highest identifiability of a plurality of marks formed in a substrate. The plurality of marks are made of mutually different patterns. A device pattern is formed in the substrate using directed self-assembly after the plurality of marks is formed.

Abstract: Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

Abstract: An alignment mark is formed on a substrate including a first region and a second region. The alignment mark is formed in the second region. An etch target layer including a crystalline material is formed on the alignment mark and the substrate. The etch target layer in the first region is partially amorphized. The amorphized etch target layer is etched to form an opening.

Abstract: A method for forming a self-aligned overlay mark is disclosed. First, a first region, a second region and a main feature which is disposed between the first region and the second region all disposed on the substrate are provided. The first region defines a first edge and the second region defines a second edge. Second, a cut mask layer is formed to respectively cover the first region and the second region to expose the main feature. Next, the cut mask layer is determined if it is self-aligned with the second edge or the first edge, and creates a self-aligned overlay mark. Later, a main feature etching step is carried out to transfer the main feature into the substrate when the cut mask layer is determined to be self-aligned with the second edge or the first edge.

Abstract: A method of back-side patterning of a silicon wafer is disclosed, which includes: depositing a protective layer on a front side of a silicon wafer; forming one or more deep trenches through the protective layer and extending into the silicon wafer by a depth greater than a target thickness of the silicon wafer; flipping over the silicon wafer and bonding the front side of the silicon wafer with a carrier wafer; polishing a back side of the silicon wafer; performing alignment by using the one or more deep trench alignment marks and performing back-side patterning process on the back side of the silicon wafer; and de-bonding the silicon wafer with the carrier wafer.

Abstract: A semiconductor pressure sensor includes a first substrate having a concave portion and an alignment mark at a main surface thereof, and a second substrate formed on the main surface of the first substrate and having a diaphragm provided to cover a space inside the concave portion of the first substrate and a gauge resistor provided on the diaphragm. The alignment mark is provided to be exposed from the second substrate. Accordingly, it is possible to obtain a semiconductor pressure sensor and a method of manufacturing the same with reduced production costs and with improved pressure measuring accuracy.

Abstract: A method of fabricating a semiconductor device includes providing a substrate that is divided into a first region on which a pattern layer is formed and a second region on which a photo key is formed. A silicon layer is formed on the first region and second region of the substrate. The silicon layer is patterned to form a hole exposing a photo key portion of the second region on which the photo key is formed. A buried oxide layer is formed to fill the hole exposing the photo key portion. The silicon layer is patterned by using the photo key formed under the buried oxide layer to form a silicon pattern layer.

Abstract: A method of fabricating a semiconductor device includes forming an etch-target layer on a substrate having an alignment key, forming a transparent first pattern on the etch-target layer to face the alignment key, forming an opaque second pattern on the etch-target layer to be adjacent to the first pattern, and etching the etch-target layer using the first pattern and the second pattern as an etch mask.

Abstract: A fabrication method of a package structure having MEMS elements includes: disposing a plate on top of a wafer having MEMS elements and second alignment keys; cutting the plate to form therein a plurality of openings exposing the second alignment keys; performing a wire bonding process and disposing block bodies corresponding to the second alignment keys, respectively; forming an encapsulant and partially removing the encapsulant and the block bodies from the top of the encapsulant; and aligning through the second alignment keys so as to form on the encapsulant a plurality of metal traces. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce the fabrication costs. Further, since the plate only covers the MEMS elements and the encapsulant is partially removed, the overall thickness and size of the package structure are reduced.

Abstract: A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.

Abstract: A semiconductor wafer is aligned using a double patterning process. A first resist layer having a first optical characteristic is deposited and foams at least one alignment mark. The first resist layer is developed. A second resist layer having a second optical characteristic is deposited over the first resist layer. The combination of first and second resist layers and alignment mark has a characteristic such that radiation of a pre-determined wavelength incident on the alignment mark produces a first or higher order diffraction as a function of the first and second optical characteristics.

Abstract: A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel.

Abstract: In one embodiment, a semiconductor target for detecting overlay error between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The target comprises at least a plurality of a plurality of first grating structures having a course pitch that is resolvable by an inspection tool and a plurality of second grating structures positioned relative to the first grating structures. The second grating structures have a fine pitch that is smaller than the course pitch, and the first and second grating structures are both formed in two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate. The first and second gratings have feature dimensions that all comply with a predefined design rules specification.

Abstract: A manufacturing method, for a liquid discharge head substrate that includes a silicon substrate in which a liquid supply port is formed, includes the steps of: preparing the silicon substrate, on one face of which a mask layer, in which an opening has been formed, is deposited; forming a first recessed portion in the silicon substrate, so that the recessed portion is extended through the opening from the one face of the silicon substrate to the other, reverse face of the silicon substrate; forming a second recessed portion by performing wet etching for the substrate, via the first recessed portion, using the mask layer; and performing dry etching for the silicon substrate in a direction from the second recessed portion to the other face.

Abstract: A substrate comprises a first mark and a second mark. The first mark comprises a first pattern with at least one mark feature formed by a first material and at least one region formed by a second material. The first and second materials have different material characteristics with respect to a substrate treatment process such that a step height in a direction substantially perpendicular to the surface of the substrate may be created by applying the substrate treatment process. The second mark can be provided with a second step height by applying the substrate treatment process. The second step height is substantially different from the first step height.

Abstract: Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.

Abstract: A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Abstract: A semiconductor device includes an alignment mark formed over a semiconductor substrate and an inhibition pattern arranged over the alignment mark with a pattern edge of the inhibition pattern located in a mark functional region of the alignment mark in order to inhibit the alignment mark being recognized as such by an image detector of an exposure device.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values.

Abstract: A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark.

Abstract: A method of manufacturing a semiconductor device includes: forming a recessed portion in a semiconductor substrate; forming an insulating film in the recessed portion; after forming the insulating film, forming a silicide layer on the semiconductor substrate in contact with the insulating film; and performing alignment between an electron beam exposure apparatus and the semiconductor substrate by using the insulating film and the silicide layer as an alignment mark.

Abstract: A method for manufacturing a semiconductor device which prevents damage to alignment marks used for alignment between a superjunction structure and process layers at subsequent steps. In the related art, recesses are made in a semiconductor substrate before the formation of the superjunction structure and used as alignment marks and in order to prevent damage to the alignment marks, the alignment marks are covered by an insulating film such as a silicon oxide film during the subsequent process of forming the superjunction structure, but the inventors have found that damage may penetrate the cover film, reach the semiconductor substrate and destroy the marks. In the method according to the invention, alignment marks for alignment between the superjunction structure and process layers at subsequent steps are formed after the formation of the superjunction structure.

Abstract: An overlay mark is described, including N (N?2) groups of first x-directional linear patterns each defined from a different one of N pre-layers, N groups of second x-directional linear patterns of a current layer, N groups of first y-directional linear patterns each defined from a different one of the N pre-layers, and N groups of second y-directional linear patterns of the current layer. Each group of second x-directional linear patterns is disposed together with one group of first x-directional linear patterns, wherein the second linear patterns and the x-directional linear patterns are arranged alternately. Each group of second y-directional linear patterns is disposed together with one group of first y-directional linear patterns, wherein the second linear patterns and the first linear patterns are arranged alternately.

Abstract: Disclosed herein are methods of patterning features in a structure, such as a layer of material used in forming integrated circuit devices or in a semiconducting substrate, using a multiple sidewall image transfer technique. In one example, the method includes forming a first mandrel above a structure, forming a plurality of first spacers adjacent the first mandrel, forming a plurality of second mandrels adjacent one of the first spacers, and forming a plurality of second spacers adjacent one of the second mandrels. The method also includes performing at least one etching process to selectively remove the first mandrel and the second mandrels relative to the first spacers and the second spacers and thereby define an etch mask comprised of the first spacers and the second spacer and performing at least one etching process through the etch mask on the structure to define a plurality of features in the structure.

Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Abstract: A method for making a laminated chip includes: (a) forming a first conductive layer on a substrate; (b) forming an insulating layer on the first conductive layer opposite to the substrate; (c) bombarding the insulating layer using an electron beam to form a plurality of holes that expose the first conductive layer; and (d) forming a second conductive layer on the insulating layer such that a part of the second conductive layer extends into the holes to electrically connect to the first conductive layer.

Abstract: The present invention relates to a photomask and a method for forming an overlay mark in a substrate using the same. The photomask comprises a plurality of patterns. At least one of the patterns comprises a plurality of ring areas and a plurality of inner areas enclosed by the ring areas, wherein the light transmittancy of the ring areas is different from that of the inner areas. When the photomask is applied in a photolithography process, the formed overlay mark has a large thickness. Therefore, the contrast is high when a metrology process is performed, and it is easy to find the overlay mark.

Abstract: An alignment layer is formed by forming an alignment solution on a base substrate, baking the alignment solution to form an alignment layer, and irradiating light having a wavelength of about 280 nanometers to about 340 nanometers to the alignment layer, thereby aligning the alignment layer. A liquid crystal display is manufactured using the method of forming the alignment layer.

Abstract: A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.

Abstract: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined.

Abstract: A method for manufacturing a semiconductor integrated circuit device includes the step of forming an SOI device region and a bulk device region on an SOI type semiconductor wafer. The method includes: removing a BOX layer and an SOI layer in a bulk device region; and thereafter forming an STI region in both the SOI device region and the bulk device region. In the method, the STI region in the SOI device region is formed to extend through the BOX layer.

Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.

Abstract: Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer. The mark for alignment is formed so as to extend from the first main surface toward the second main surface and have a protruding portion protruding from the second main surface in a direction toward where the light receiving lens is disposed.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Abstract: A method for generating reticle data for forming a reticle. The method includes recognizing a non-layout region free from main chips in a process pattern, dividing the non-layout region into a plurality of rectangular non-layout regions, generating scribe data using the plurality of divided rectangular non-layout region as a plurality of dummy chips, and generating a dummy pattern for each of the dummy chips.

Abstract: A method of manufacturing a display device is disclosed. In one embodiment, the method includes: i) forming a semiconductor layer where a plurality of crystallized areas and a plurality of noncrystallized areas are alternately arranged on a substrate, ii) aligning the substrate based on a difference in contrast ratio between the crystallized and noncrystallized areas and iii) performing a photo process or a photolithography process.

Abstract: A method for forming a self-aligned overlay mark is disclosed. First, a first region, a second region and a main feature which is disposed between the first region and the second region all disposed on the substrate are provided. The first region defines a first edge and the second region defines a second edge. Second, a cut mask layer is formed to respectively cover the first region and the second region to expose the main feature. Next, the cut mask layer is determined if it is self-aligned with the second edge or the first edge, and creates a self-aligned overlay mark. Later, a main feature etching step is carried out to transfer the main feature into the substrate when the cut mask layer is determined to be self-aligned with the second edge or the first edge.

Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density.

Abstract: The invention relates to a solar-cell marking method comprising the steps of: providing a substrate with a substrate surface for producing a solar cell (1) that comprises an active zone (5); and producing at least one indentation (21, 31) in the substrate surface with the use of laser irradiation, wherein the at least one indentation (21, 31) forms a marking (2, 3) for marking the solar cell (1), and producing the indentation (21, 31) is carried out prior to carrying out a solar-cell manufacturing process or during carrying out a solar-cell manufacturing process. According to the invention the substrate is designed as a semiconductor wafer with a wafer surface, and the marking (2, 3) is positioned on the wafer surface such that the marking (2, 3) is in the active zone (5) of the solar cell (1) formed by the semiconductor wafer.

Abstract: A method is provided for assembling a stack of surface-mount devices (SMDs) on a substrate. The method provides a substrate, die, or printed circuit board (PCB) with a top surface having a landing pad and a first reference feature. An alignment jig is placed overlying the substrate top surface. The alignment jig second reference feature is aligned with respect to the substrate first reference feature. A first SMD is placed overlying the substrate landing pad. The first SMD third reference feature is aligned with respect to the alignment jig second reference feature. A second SMD is placed overlying the substrate top surface. Then, the alignment jig first boundary feature is mated with the second SMD second boundary feature. In response to the mating, the second SMD first interface is aligned over an underlying SMD active element.

Abstract: A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof.

Abstract: A manufacturing method for a TFT array substrate includes providing a substrate; defining a plurality of normal alignment regions and a plurality of abnormal alignment regions on the substrate; forming an insulating layer and a transparent conductive layer on the substrate; performing a patterning process to at least one of the insulating layer and the transparent conductive layer to form a plurality of alignment structures in each abnormal alignment region; forming an alignment material layer on the substrate, the alignment material layer having a plurality of first alignment slits formed along the alignment structures in each of the abnormal alignment regions; and performing a rubbing alignment process to form a plurality of second alignment slits on the alignment material layer in each of the normal alignment regions along a alignment direction.

Abstract: In one embodiment, a semiconductor target for determining overlay error, if any, between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The target comprises at least a plurality of first structures that are invariant for a plurality of first rotation angles with respect to a first center of symmetry (COS) of the first structures and a plurality of second structures that are invariant for a plurality of second rotation angles with respect to a second COS of the second structures. The first rotation angles differ from the second rotation angles, and first structures and second structures are formed on different layers of the substrate or separately generated patterns on a same layer of the substrate.

Abstract: A method of double-sided patterning including positioning a first silicon wafer with its back side facing upwards and forming one or more deep trenches serving as alignment marks on the back side of the first silicon wafer; performing alignment with respect to the alignment marks and forming a back-side pattern on the first silicon wafer; depositing a polishing stop layer on the back side of the first silicon wafer; flipping over the first silicon wafer and bonding its back side with the front side of a second silicon wafer; polishing the front side of the first silicon wafer to expose the alignment marks from the front side; performing alignment with respect to the alignment marks and forming a front-side pattern on the first silicon wafer; removing the second silicon wafer and the polishing stop layer to obtain a double-sided patterned structure on the first silicon wafer.

Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Abstract: System and method for automated semiconductor manufacturing is provided. In accordance with one aspect of the present invention, a system for automated semiconductor wafer manufacturing includes a smart overlay control (SOC) database having empirical alignment data related to overlay alignment, and a simulation module communicatively coupled to the SOC database, the simulation module determining a simulated overlay alignment of a wafer on the plurality of photolithography tools in a tool bank based on the empirical alignment data stored in the SOC database. The system also includes a dispatch module communicatively coupled to the SOC database and the simulation module, the dispatch module controlling the dispatch of a wafer to one of a plurality of photolithography tools in a tool bank based at least in part on the simulated overlay alignment.

Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: There is provided a semiconductor device including: an insulating layer provided on a substrate and formed with plural cavities; wiring lines provided on the insulating layer; plural branched wiring lines that branch from the wiring lines so as to respectively overlap with the plural cavities when seen in plan view; a conductive portion formed on the wiring lines; an external terminal formed on the conductive portion; and a sealing resin layer that seals the wiring lines and the conductive portion.