Abstract: The present invention provides a material for forming an organic film, containing a compound shown by the following general formula (1), and an organic solvent, where X represents an organic group having a valency of n1 and 2 to 50 carbon atoms, n1 represents an integer of 1 to 10, and R1 represents at least one or more of the following general formulae (2) to (4). This aims to provide an organic film material for forming an organic film that has all of high filling property, high planarizing property, and excellent adhesive force to a substrate.

Abstract: A physical quantity sensor includes a plurality of diaphragm portions which are bent and deformed due to pressure reception, and a plurality of piezoresistive elements which are disposed in the diaphragm portions at different locations from each other and are electrically connected to each other in series. The plurality of piezoresistive elements constitute a bridge circuit.

Abstract: A method of manufacturing a nano-rod and a method of manufacturing a display substrate in which a seed including a metal oxide is formed. A nano-rod is formed by reacting the seed with a metal precursor in an organic solvent. Therefore, the nano-rod may be easily formed, and a manufacturing reliability of the nano-rod and a display substrate using the nano-rod may be improved.

Abstract: A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices.

Abstract: A method and system are provided for manufacturing a base substrate that is used in manufacturing a semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.

Abstract: Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.

Abstract: An optically active material is used to create power devices and circuits having significant performance advantages over conventional methods for affecting optical control of power electronics devices and circuits. A silicon-carbide optically active material is formed by compensating shallow donors with the boron related D-center. The resulting material can be n-type or p-type but it is distinguished from other materials by the ability to induce persistent photoconductivity in it when illuminated by electromagnetic radiation with a photon energy in excess of the threshold energy required to photoexcite electrons from the D-center to allowed states close to the conduction band edge, which varies from polytype to polytype.

Abstract: Graded core/shell semiconductor nanorods and shapped nanorods are disclosed comprising Group II-VI, Group III-V and Group IV semiconductors and methods of making the same. Also disclosed are nanorod barcodes using core/shell nanorods where the core is a semiconductor or metal material, and with or without a shell. Methods of labeling analytes using the nanorod barcodes are also disclosed.

Abstract: Novel conjugates of nanoparticles are provided and have particular utility in the detection of latent fingerprints by their ability to bind to a fingerprint residue. The conjugate comprises a nanoparticle attached to a linker group having a terminal reactive moiety, wherein said nanoparticle comprises a core of a first semiconductor material having a first luminescence and a shell of a second material which at least partially surrounds the core. The conjugated nanoparticle can bind to the fingerprint residue and can be detected using fluorescence.

Abstract: A thin film transistor, a method of fabricating the same, and an OLED display device having the same. The thin film transistor includes a substrate, a semiconductor layer disposed on the substrate and having a channel region, source and drain regions, and a body contact region, a gate insulating layer disposed on the semiconductor layer to expose the body contact region, a silicon layer disposed on the gate insulating layer and contacting the body contact region exposed by the gate insulating layer, a gate electrode disposed on the silicon layer, an interlayer insulating layer disposed on the gate electrode, and source and drain electrodes disposed on the interlayer insulating layer and electrically connected with the source and drain regions, wherein the body contact region is formed in an edge region of the semiconductor layer.

Abstract: Method of producing a partly or completely semi-insulating or p-type doped ZnO substrate from an n-type doped ZnO substrate, in which the n-type doped ZnO substrate is brought into contact with an anhydrous molten salt chosen from anhydrous molten sodium nitrate, lithium nitrate, potassium nitrate and rubidium nitrate. Partly or completely semi-insulating or p-type doped ZnO substrate, said substrate being in particular in the form of a thin layer, film or in the form of nanowires; and said substrate being doped at the same time by an element chosen from Na, Li, K and Rb; by N; and by O; it being furthermore possible for ZnO or GaN to be epitaxially grown on this substrate. Electronic, optoelectronic or electro-optic device such as a light-emitting diode (LED) comprising this substrate.

Abstract: An optically active material is used to create power devices and circuits having significant performance advantages over conventional methods for affecting optical control of power electronics devices and circuits. A silicon-carbide optically active material is formed by compensating shallow donors with the boron related D-center. The resulting material can be n-type or p-type but it is distinguished from other materials by the ability to induce persistent photoconductivity in it when illuminated by electromagnetic radiation with a photon energy in excess of the threshold energy required to photoexcite electrons from the D-center to allowed states close to the conduction band edge, which varies from polytype to polytype.

Abstract: A CMOS image sensor and a method of fabricating the same. The CMOS image sensor may minimize disappearance of electrons generated by light without transmission of electrons to a transfer gate. A method of manufacturing a CMOS image sensor may include forming a trench over an isolation region of a semiconductor substrate to define an active region including a photodiode region and a transistor region. The method may include forming first conductivity-type ion implanted regions over a trench side wall of a photodiode region and over a region adjacent to the transistor region. The method may include forming second conductivity-type ion implanted regions between a first conductivity-type ion implanted region and a trench, and between a lower part of a transistor region and a first conductivity-type ion implanted region. The method may include forming an isolation layer, forming a gate electrode and a spacer, and/or forming a photodiode.

Abstract: Light emitting diode (LED) dies are fabricated by forming LED layers including a first conductivity type layer, a light-emitting layer, and a second conductivity type layer. Trenches are formed in the LED layers that reach at least partially into the first conductivity type layer. Electrically insulation regions are formed in or next to at least portions of the first conductivity type layer along the die edges. A first conductivity bond pad layer is formed to electrically contact the first conductivity type layer and extend over the singulation streets between the LED dies. A second conductivity bond pad layer is formed to electrically contact the second conductivity type layer, and extend over the singulation streets between the LED dies and the electrically insulated portions of the first conductivity type layer. The LED dies are mounted to submounts and the LED dies are singulated along the singulation streets between the LED dies.

Abstract: Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.

Abstract: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source.

Abstract: A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.

Abstract: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source.

Abstract: Disclosed is a light emitting device having a plurality of light emitting cells. The light emitting device comprises a thermally conductive substrate, such as a SiC substrate, having a thermal conductivity higher than that of a sapphire substrate. The plurality of light emitting cells are connected in series on the thermally conductive substrate. Meanwhile, a semi-insulating buffer layer is interposed between the thermally conductive substrate and the light emitting cells. For example, the semi-insulating buffer layer may be formed of AlN or semi-insulating GaN. Since the thermally conductive substrate having a thermal conductivity higher than that of a sapphire substrate is employed, heat-dissipating performance can be enhanced as compared with a conventional sapphire substrate, thereby increasing the maximum light output of a light emitting device that is driven under a high voltage AC power source.

Abstract: Provided is a method for producing an SOI substrate comprising a transparent insulating substrate and a silicon film formed on a first major surface of the insulating substrate wherein a second major surface of the insulating substrate which is opposite to the major surface is roughened, the method suppressing the generation of metal impurities and particles in a simple and easy way.

Abstract: There is a method of forming a contact post and surrounding isolation trench in a semiconductor-on-insulator (SOI) substrate. The method comprises etching a contact hole and surrounding isolation trench from an active layer of the substrate to the insulating layer, masking the trench and further etching the contact hole to the base substrate layer, filling the trench and contact hole with undoped intrinsic polysilicon and then performing a doping process in respect of the polysilicon material filling the contact hole so as to form in situ a highly doped contact post, while the material filling the isolation trench remains non-conductive. The isolation trench and contact post are formed substantially simultaneously so as to avoid undue interference with the device fabrication process.

Abstract: According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device having active regions including a SONOS device region, a high voltage device region, and a logic device region, includes defining the active regions by forming a device isolation region on a semiconductor substrate; performing ion-implantation in the SONOS device region to control a threshold voltage of a SONOS device; performing ion-implantation in the high voltage device region to form a well; performing ion-implantation in the SONOS device region and the logic device region to form a well; and forming an ONO pattern on the SONOS device region, generally by performing a photolithography and etching process on the ONO layer.

Abstract: A layer structure comprising a smoothed interlayer and an overlying layer applied on the interlayer, wherein the interlayer is treated with a gaseous etchant containing hydrogen fluoride, a material removal being obtained thereby and the interlayer being smoothed.

Abstract: An integrated device includes two sections (A, B), such as a DFB laser (A) and an EAM modulator (B), having a semi-insulating (SI) separation region therebetween. The separation region (24) is of a material acting as a trap on electrons and configured to impede current flow between the two sections (A, B) due to holes. The separation region (24) may be of a material acting as a trap both on electrons and holes. Alternatively, the separation region (24) is of a material that acts as a trap on electrons and is provided over a p-type substrate (20) common to the two sections (A, B).

Abstract: In a layout method for a semiconductor integrated circuit by using cell library data, a plurality of cell patterns are arranged in a first direction. One of gate patterns in one of the plurality of cell patterns is specified as a reference gate pattern. An additional cell pattern is arranged in a second direction orthogonal to the first direction such that a number of gate patterns within a predetermined area containing the reference gate pattern satisfies a constraint condition.

Abstract: This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of oxygen ions so as to form an amorphous layer; and subjecting the silicon wafer to a heat-treating in a mixed gas atmosphere containing oxygen so as to form a buried oxide layer. In the forming of the buried oxide layer, a starting temperature is less than 1350° C. and a maximum temperature is 1350° C. or more. This SIMOX wafer is manufactured by the above method and includes a BOX layer and a SOI layer on the BOX layer. The BOX layer has a thickness of 1300 ? or more and a breakdown voltage of 7 MV/cm or more, and the surface of the SOI layer and the interface between the SOI layer and the BOX layer have a roughness over a 10-?m square area of 4 ? rms or less.

Abstract: A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.

Abstract: Disclosed is a method for manufacturing a semiconductor optical device for flip-chip bonding. The method includes the steps of: etching an active layer and clad which are sequentially stacked on a semiconductor substrate into first and second alignment keys and an optical area, which has a mesa structure; growing at least two insulating layers at mesa-etched portions between the first and second alignment keys and the optical areas; and forming protection masks on the first and second alignment keys, growing an electrode on the optical area and the insulating layer except for the protection masks, and removing the protection masks.

Abstract: Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N- and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.

Abstract: In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor substrate with an opening that exposes a portion of the defined region of the semiconductor substrate having the single crystalline structure. A first non-single crystalline film is formed on the exposed portion of the semiconductor substrate and that at least substantially fills the opening in the first insulating film. A laser beam is generated that heats the first non-single crystalline film to change the first non-single crystalline film into a first single crystalline film having substantially the same single crystalline structure as the defined region of the semiconductor substrate.

Abstract: A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.

Abstract: Dendron ligands or other branched ligands with cross-linkable groups were coordinated to colloidal inorganic nanoparticles, including nanocrystals, and substantially globally cross-linked through different strategies, such as ring-closing metathesis (RCM), dendrimer-bridging methods, and the like. This global cross-linking reaction sealed each nanocrystal within a dendron box to yield box-nanocrystals which showed dramatically enhanced stability against chemical, photochemical and thermal treatments in comparison to the non-cross-linked dendron-nanocrystals. Empty dendron boxes possessing a very narrow size distribution were formed by the dissolution of the inorganic nanocrystals contained therein upon acid or other etching treatments.

Abstract: The present invention provides a holder (20) for wafers (14) which makes it possible to more easily manipulate the wafer (14) and makes it more suitable than prior art devices for to liquid handling, wafer handling and on-wafer manipulation of substances, while it also makes it possible to align the wafer (14) accurately and furthermore allows to create a well controlled ambient in the neighbourhood of the wafer (14).

Abstract: A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.

Abstract: The silicon wires formed around metal particles by crystal growth have the problem of metal pollution. For its solution, in the present invention, a silicon bridge is formed through standard silicon processes such as the lithography and the wet etching using hydrofluoric acid performed to an SOI substrate. Thereafter, a thermal oxide film is desirably formed at a high temperature to form a high-quality gate insulating film. It is also desirable to form a coaxial gate electrode. Then, after burying the bridge sections of the silicon bridge in a resist film, the silicon on the bridge girders is removed, and thereafter, the silicon wires buried in the resist film are collected. In this manner, the silicon wires can be collected without dispersing into the hydrofluoric acid solution. Then, a transistor using the silicon wires as a channel is formed.

Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.

Abstract: A method for forming a semiconductor on insulator structure includes forming a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semiconductor layer. The semiconductor layer can also be formed having a thickness such that, it does not yield due to temperature-induced strain at device processing temperatures. A silicon layer bonded to a silicon oxycarbide glass substrate provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

Abstract: A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried electrode pad formed of an conductive material on one side of the glass substrate where the back bias voltage is applied, a buffer layer formed of an insulation material on the whole surface of the glass substrate, and a poly-Si TFT formed on the upper portion of the buffer layer. A method of fabricating the TFT is also provided.

Abstract: Provided is a manufacturing method of a buried insulating layer type semiconductor silicon carbide substrate excellent in flatness of an interfaces in contact the insulating layer and a manufacturing device thereof. In the manufacturing device, an SOI substrate having a buried insulating layer positioned on a silicon substrate and a surface silicon layer formed on this buried insulating layer is placed in this film formation chamber. The manufacturing device includes: the film formation chamber in which the SOI substrate is placed; a gas supplying unit for supplying various types of gasses required for the manufacturing of a buried insulating layer type semiconductor silicon carbide substrate into the film formation chamber; an infrared ray irradiating unit for irradiating the surface silicon layer of the SOI substrate with infrared rays; and a control part for controlling the gas supplying unit and the infrared ray irradiating unit.

Abstract: Semiconductor devices useful in high temperature sensing applications include a silicon carbide substrate, a silicon dioxide layer, and an outer layer of crystalline doped silicon carbide. The device is a 3C—SiC/SiO2/SiC structure. This structure can be employed to fabricate high temperature devices such as piezoresistive sensors, minority carrier devices and so on. The crystalline doped silicon carbide is dielectrically isolated from the substrate. The devices are formed by processes that include bonding a pattern wafer to a substrate wafer, selective oxidation and removal of undoped silicon, and conversion of doped silicon to crystalline silicon carbide. The level of doping and the crystalline structure of the silicon carbide can be selected according to desired properties for particular applications.

Abstract: A silicon-on-insulator substrate comprises a first silicon substrate having a first crystal orientation, said first substrate having a first polished surface and a first wafer notch; a second silicon substrate having a second crystal orientation different from the first crystal orientation of the first silicon substrate, said second substrate having a second polished surface and a second wafer notch; and the first polished surface of the first silicon substrate being bonded to the second polished surface of the second silicon substrates.

Abstract: A method for processing an SOI substrate composed of a backing layer comprising a semiconductor substrate, an insulating layer laminated on the upper surface of the backing layer, a thin semiconductor film layer laminated on the upper surface of the insulating layer, and circuits formed on the face of the thin semiconductor film layer, the method including: a grinding step of grinding the backing layer so as to remain with a predetermined thickness; and an etching step of removing the backing layer, which has been formed to the predetermined thickness by the grinding step, by chemical etching to expose the insulating layer.

Abstract: The present invention relates to a multi-layer dopant barrier and its method of fabrication for use in semiconductor structures. In an illustrative embodiment, the multi-layer dopant barrier is disposed between a first doped layer and a second doped layer. The multi-layer dopant barrier further includes a first dopant blocking layer adjacent the first doped layer and a second dopant blocking layer adjacent the second doped layer. A technique for fabricating the multi layer dopant barrier is disclosed. A first dopant blocking layer is formed at a first temperature, and a second dopant blocking layer is formed at a second temperature over the first barrier layer.

Abstract: Indium phosphor (InP) Gunn diode that realizes improvements in thermal characteristics, yield factor of good products and easy assembly to planar circuits is provided. In a Gunn diode of the present invention, contact layers are interposing an active layer. An anode electrode and a cathode electrode are formed on the uppermost contact layer. A high resistance region around the cathode electrode is formed at least in an uppermost contact layer by ion implantation using the cathode and anode electrode as a mask. A region under the cathode electrode functions as a Gunn diode and a region under the anode electrode function as a conductive path from the anode electrode to the active layer. These two regions are defined by the high resistance region.

Abstract: An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14 is used to provide a cohesive bond with a buried insulator layer 18. The semiconductor device layer 20 is formed on the outer surface of buried insulator layer 18. An inductive well 22 can be formed to provide a platform for the formation of inductive devices 34 within an inductive region 26.

Abstract: A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried electrode pad formed of an conductive material on one side of the glass substrate where the back bias voltage is applied, a buffer layer formed of an insulation material on the whole surface of the glass substrate, and a poly-Si TFT formed on the upper portion of the buffer layer. A method of fabricating the TFT is also provided.

Abstract: A method for fabricating a semiconductor memory device is provided to increase the etch selectivity of photoresist by changing the matter properties thereof in forming a trench isolation region. The method includes the steps of: depositing first and second insulating layers on a semiconductor substrate where a shallow trench isolation (STI) region and a deep trench isolation (DTI) region are defined; forming the STI region by selectively etching the second and first insulating layers and the semiconductor substrate; forming a photoresist to cover the STI region and curing the surface of the photoresist; and forming the DTI region by using the cured photoresist and the second insulating layer as a mask.

Abstract: A silicon-on-insulator (SOI) substrate having a grid-line region and a circuit region, and including a silicon substrate having an upper surface, a first insulating layer having an upper surface and a silicon layer, and which has a grid-line region zoning a circuit region. An element isolation region is formed in the silicon layer of the circuit region of the SOI substrate, and an insulating region is formed in the silicon layer of the grid-line region of the SOI substrate. The insulating region and a portion of the first insulating layer located under the insulating region are removed to define a recess in the grid-line region.

Abstract: An integrated circuit, such as a DRAM circuit, having a plurality of cells is formed in containers formed an isolation layer positioned on an first surface of a semiconductor substrate. The containers have a first region located proximal the first surface of the semiconductor substrate that has a first cross-sectional area and a second region located distal from the first surface of the semiconductor substrate that has a second cross-sectional area that is less than the first cross-sectional area. Cells, such as capacitors, are formed in the containers and the isolation material positioned between adjacent cells is removed so that a generally horizontal surface is formed. The horizontal surface is located closer to the first surface of the substrate than the transition between the first region and the second region of the container so that substantially vertical surfaces are formed in the isolation region linking the cells to the horizontal surface of the isolation layer.