Abstract: The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

Abstract: A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the LIM exposing the top surface of the substrate. Form an epitaxial silicon layer over the top surface of the substrate burying the LIR. Form a trench mask over the epitaxial layer. Etch a trench reaching through the epitaxial layer and the LIR. Form oxidized trench sidewalls, an oxidized trench bottom and oxidized sidewalls of the LIR. Etch the oxidized sidewalls of the LIR until the LIR is exposed. Form laterally extending trenches by etching away the LIR.

Abstract: A semiconductor light-emitting device has a semiconductor layer containing Al between a substrate and an active layer containing nitrogen, wherein Al and oxygen are removed from a growth chamber before growing said active layer and a concentration of oxygen incorporated into said active layer together with Al is set to a level such that said semiconductor light-emitting device can perform a continuous laser oscillation at room temperature.

Abstract: An SOI wafer including an active semiconductor material layer on an insulating layer is processed to form thereon first and second active semiconductor regions that respectively have different thicknesses and that are vertically and laterally insulated. In the process, a trench is etched into the SOI wafer, seed openings are formed in the bottom of the trench to reach the underlying active material layer, the trench is filled with epitaxially grown semiconductor material progressing from the seed openings, some of the epitaxially grown material is removed to form the second active regions, and oxide layers are provided so that the second active regions are laterally and vertically insulated from the first active regions formed by remaining portions of the active semiconductor material layer.

Abstract: A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.

Abstract: A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support. A substrate of a relatively thicker layer of a third material is grown, by epitaxy on the nucleation layer, to form a second assembly with the substrate attaining a sufficient thickness to be free-standing. The third material is preferably a monocrystalline material. Also, the removable character of the bonding interface is preserved with at least the substrate being heated to an epitaxial growth temperature.

Abstract: A method for forming a semiconductor device having isolation structures decreases leakage current. A channel isolation structure decreases leakage current through a channel structure. In addition, current electrode dielectric insulation structures are formed under current electrode regions to prevent leakage between the current electrodes.

Abstract: There is provided a method of manufacturing a substrate having a partial insulating layer under a semiconductor layer. A partial SOI substrate (40) is obtained by performing steps of forming the first substrate which has a separation layer, the first semiconductor layer (13) on the separation layer, a partial insulating layer (14a) on the first semiconductor layer (13), and second semiconductor layers (15b, 16b) on the first semiconductor layer (13) exposed in the partial insulating layer (14a) and partial insulating layer (14a), bonding the second substrate (20) to the second semiconductor layers (15b, 16b) on the first substrate to form a bonded substrate stack, and splitting the bonded substrate stack at the separation layer.

Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

Abstract: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.

Abstract: A method of forming a semiconductor device so as to provide the device inverted isolation trenches with convex sidewalls. Initially, a plurality of composite isolation posts (50, 51) are formed on a substrate (40) through successive deposition, lithography, and etching steps. The posts comprise a bottom layer (501, 502) of silicon dioxide and an overlying etch-stop layer of silicon nitride (502, 512). An insulating material (60) is then deposited over the isolation posts and areas of the substrate. Isolation structures (70,71) are established by etching the insulating material to form convex sidewall spacers (701,702, 711, 712) at the vertical walls of the isolation posts. Active areas (80) between spacers are filled with semiconductor material. In an embodiment, a strained cap layer (101) may be imposed on the active areas. The strained cap layer has a lattice constant that is different from the lattice constant of the semiconductor material.

Abstract: A multi-pattern shadow mask, shadow mask laser annealing system, and a multi-pattern shadow mask method for laser annealing are provided. The method comprises: supplying a silicon substrate; supplying a multi-pattern shadow mask with a plurality of aperture patterns; creating substrate alignment marks; with respect to the alignment marks, laser annealing a substrate region in a plurality of aperture patterns; forming a corresponding plurality of polysilicon regions; and, forming a corresponding plurality of transistor channel regions in the plurality of polysilicon regions. In some aspects of the method laser annealing in a plurality of aperture patterns includes: laser annealing a first area in a substrate region with a first aperture pattern; and, stepping and repeating the laser annealing in a second area, adjacent the first area, in the substrate region.

Abstract: A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A gate structure is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post, and a capacitor formed on an exposed surface of the epitaxial post.

Abstract: A method for forming an active area in a substrate includes the steps of growing an isolation oxide on a silicon substrate, providing a photresist mask to define the active areas on the substrate, performing etching and stripping processes, removing the residual oxide from the active areas and selectively growing an epitaxial silicon layer.

Abstract: In a method of forming a contact, a liner reactive ion etch is affected on a substrate to remove silicon nitride and silicon oxide. An oxygen plasma ex-situ clean, a Huang AB clean, and a dilute hydrofluric acid (DHF) clean are affected. Amorphous silicon is deposited and an anneal is performed to regrow and recrystallize amorphous silicon.

Abstract: A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.

Abstract: A method for conductively bonding a printed circuit board to a metal back plate is provided. The method includes the steps of providing a dielectric substrate that is metallized on its two faces; providing a metallic back plate; and bonding the metallic back plate to one of the metallized faces of the substrate using an electrically conductive adhesive that includes an adhesive polymer and at least one conductive metal having an electromagnetic force (EMF) that is equal to or less than one volt. The present invention also relates to a printed circuit board assembly which includes printed circuit board which includes a dielectric substrate having a first circuitized metallic layer disposed on one opposing face of the substrate and a second metallic layer disposed on the other opposing face of said substrate; a metal back plate; and an electrically conductive bonding layer disposed between the plate and the second metallic layer of the printed circuit board.

Abstract: A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium prior to formation of the strained silicon layer. The two silicon germanium layers effectively provide dual substrates at both surfaces of the strained silicon layer that serve to maintain the tensile strain of the strained silicon layer and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers.

Abstract: A multi-pattern shadow mask, shadow mask laser annealing system, and a multi-pattern shadow mask method for laser annealing are provided. The method comprises: supplying a silicon substrate; supplying a multi-pattern shadow mask with a plurality of aperture patterns; creating substrate alignment marks; with respect to the alignment marks, laser annealing a substrate region in a plurality of aperture patterns; forming a corresponding plurality of polysilicon regions; and, forming a corresponding plurality of transistor channel regions in the plurality of polysilicon regions. Typically, the shadow mask includes a plurality of sections, with each section having at least one aperture pattern. A shadow mask section can be selected to create a corresponding aperture pattern. If the mask section includes a plurality of aperture patterns, the selection of a section creates all the corresponding aperture patterns in the selected section.

Abstract: Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrystalline silicon. A dielectric material is formed on the sidewalls of the trench. Epitaxial monocrystalline silicon is grown from the base of the trench and over at least a portion of the dielectric material. An insulating layer is formed over the epitaxial monocrystalline silicon. According to one implementation, the invention includes a field isolation structure formed within a monocrystalline silicon comprising substrate. The field isolation structure includes a trench having sidewalls. A dielectric material is received on the sidewalls within the trench. Monocrystalline silicon is received within the trench between the dielectric material of the sidewalls. An insulating layer is received over the monocrystalline silicon within the trench.

Abstract: Compound semiconductor structures and devices can be grown on patterned oxide layers deposited on silicon. The deposition of Group II-VI and Group II-V compound semiconductors on patterned wafers results in an increase in the critical thickness for lattice mismatched layers and the relief of strain energy through side walls. As a result, high crystalline quality compound semiconductor material can be grown on less expensive and more accessible substrate to more cost effectively produce semiconductor components and devices having enhanced reliability.

Abstract: A Silicon On Insulator (SOI) structure and method of producing an SOI structure that can prevent a short circuit between a Local Inter-Connect (LIC) and a well in the SOI structure is disclosed. The SOI structure includes a BOX layer of insulation material formed on a silicon substrate; an SOI layer formed on the BOX layer; a well formed within a device isolation area of the SOI layer such that its lower surface is in contact with the BOX layer; a field oxide film formed on a surface side within the well; a gate line formed across an active area on the SOI layer and a portion on the field oxide film; an N+ type source/drain area formed within the active area along both sides of the gate line to contact its lower surface with the BOX layer; an insulation layer formed on such resultant structure; and an opening part that is formed within the insulation layer.

Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.

Abstract: A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semiconductor source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor material. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by patterning the first dielectric layer to selectively cover a portion of the substrate and leave an exposed portion of the substrate.

Abstract: A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.

Abstract: A buried layer of a collector region and a buried layer of a collector taking-out region are formed at the same time at each epitaxial layer when the collector region and the collector taking-out region of the semiconductor integrated circuit device according to the invention. Each buried layer is diffused to connect, and etched in V-groove. By that, the collector region and collector taking-out region made thick in film are formed at the same time so as to realize the semiconductor integrated circuit device of high withstanding voltage.

Abstract: When producing an SOS substrate by growing a silicon layer on a sapphire substrate, or when producing an SOI substrate by depositing an oxide layer or a fluoride layer, as an intermediate layer, on a silicon substrate, and growing a silicon layer on the deposited layer, (A) after growth of the silicon layer, heat treatment is performed in an oxidizing atmosphere to oxidize a part of a surface side of the silicon layer, and the resulting silicon oxide layer is removed by etching with hydrofluoric acid. (B) With this silicon layer as a seed layer, a silicon layer is regrown homoepitaxially thereon.

Abstract: A process that includes the steps of forming, in a wafer of monocrystalline silicon, first trenches extending between portions of the wafer; etching the substrate to remove the silicon around the first trenches and forming cavities in the substrate; covering the walls of the cavities with an epitaxial growth inhibiting layer; growing a monocrystalline epitaxial layer on top of the substrate and the cavities so as to obtain a monocrystalline wafer embedding buried cavities completely surrounded by silicon; forming second trenches extending in the epitaxial layer as far as the cavities; removing the epitaxial growth inhibiting layer; oxidizing the cavities, forming at least one continuous region of buried oxide; depositing a polysilicon layer on the entire surface of the wafer and inside the second trenches; removing the polysilicon layer on the surface and leaving filling regions inside the second trenches; and oxidizing, on the top, portions of said filling regions so as to form field oxide regions.

Abstract: In accordance with the objectives of the invention a new method is provided for the definition and delineation of active regions in the surface of a semiconductor substrate. A layer of pad oxide is grown on the surface of the substrate, the layer of pad oxide is patterned and etched whereby the pad oxide remains in place over areas where the isolation regions are to be created. The underlying silicon substrate is in this manner exposed; the regions of the silicon substrate that are exposed are the regions of the substrate where active devices are to be created. The exposed surface of the substrate is cleaned; the openings in the layer of pad oxide are selectively filled with a deposition of epitaxial silicon. The created structure is heat treated to improve the interface between the patterned and etched layer of pad oxide and the deposited epitaxial silicon. The created pattern of pad oxide can now be used as regions of field isolation over the surface of the substrate.

Abstract: The semiconductor device comprises a semiconductor substrate (SB) having locally at least one zone (ZL) terminating in the surface of the substrate and entirely bordered, along its lateral edges and its bottom, by an insulating material so as to be completely isolated from the rest of the substrate. The horizontal isolating layer may be a layer of constant thickness or a crenellated layer.

Abstract: A process for producing a semiconductor device module comprises the steps of forming a first substrate having a separation layer having thereon a plurality of independent semiconductor layers and semiconductor devices individually formed on the plurality of semiconductor layers, electrically connecting the semiconductor devices one another on the first substrate, and separating the plurality of semiconductor layers from the first substrate at the separation layer to transfer the semiconductor layers to a second substrate.

Abstract: A trench is formed in a silicon substrate, and an epitaxial film is formed on the substrate and in the trench. After a part of the epitaxial film formed around an opening portion of the trench is etched, another epitaxial film is formed on the substrate and in the trench. Accordingly, the trench can be filled with the epitaxial films completely. Then, the surface of the substrate is flattened.

Abstract: P-type LDMOS devices have been difficult to integrate with N-type LDMOS devices without adding an extra mask because the former have been unable to achieve the same breakdown voltage as the latter due to early punch-through. This problem has been overcome by preceding the epitaxial deposition of N− silicon onto the P− substrate with an additional process step in which a buried N+ layer is formed at the surface of the substrate by ion implantation. This N+ buried layer significantly reduces the width of the depletion layer that extends outwards from the P− well when voltage is applied to the drain thus substantially raising the punch-through voltage.

Abstract: A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

Abstract: A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

Abstract: A method of manufacturing a semiconductor article comprises forming a doped layer containing an element capable of controlling the conductivity type at least on one of the surfaces of a semiconductor substrate, modifying the surface of the doped layer into a porous state to obtain a porous layer thinner than the doped layer, forming a non-porous layer on the porous layer to prepare a first article, bonding the first article and a second article so as to produce a multilayer structure having the porous layer in the inside thereof, and separating the multilayer structure along the porous layer.

Abstract: A wafer cap protects micro electromechanical system (“MEMS”) structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.

Abstract: A method comprises steps of forming a doped layer containing an element capable of controlling the conductivity type at least on one of the surfaces of a semiconductor substrate, modifying the surface of the doped layer into a porous state to obtain a porous layer thinner than the doped layer, forming a non-porous layer on the porous layer to prepare a first article, bonding said first article and a second article so as to produce a multilayer structure having said porous layer in the inside thereof, and separating said multilayer structure along said porous layer.

Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.

Abstract: A method for producing an insulating or barrier layer, useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on said silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on said deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite. Semiconductor devices are disclosed which comprise said barrier composite.

Abstract: A process for manufacturing a SOI wafer with buried oxide regions without cusps that includes forming, in a wafer of monocrystalline semiconductor material, trenches extending between, and delimiting laterally, protruding regions; forming masking regions, implanted with nitrogen ions, the masking regions surrounding completely the tips of the protruding regions; and forming retarding regions on the bottom of the trenches, wherein nitrogen is implanted at a lower dose than the masking regions. A thermal oxidation is then carried out and starts at the bottom portion of the protruding regions and then proceeds downwards; thereby, a continuous region of buried oxide is formed and is overlaid by non-oxidized regions corresponding to the tips of the protruding regions and forming nucleus regions for a subsequent epitaxial growth.

Abstract: A method for forming a crystal layer including the steps of (1) supplying first impurity atoms onto a surface of a crystal substrate to form a surfactant layer adsorbed on the surface, (2) supplying nucleus atoms which bond with the first impurity atoms, (3) repeating step (2) until second impurity atoms are supplied in step (4), and (4) supplying second impurity atoms which bond with the first impurity atoms and the nucleus atoms to epitaxially grow a crystal layer including the nucleus atoms as a crystal nucleus material doped with the first and second impurity atoms. A co-dopant having a three-atom composite formed by supplying the atoms on the surface of the crystal enables smooth doping thereof to produce the crystal having the high density dopant or a low resistance.

Abstract: A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and then removed, so as to form a cavity that extends in depth as far as the buried oxide layer. Subsequently, the cavity is filled with epitaxial or polycrystalline silicon, so as to form a power region extending between the top surface and the bottom surface of the wafer; then lateral insulation regions are formed that insulate the power region from the circuitry region.

Abstract: Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (202) on silicon oxide (201) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate.

Abstract: A method of manufacturing a semiconductor article comprises forming a doped layer containing an element capable of controlling the conductivity type at least on one of the surfaces of a semiconductor substrate, modifying the surface of the doped layer into a porous state to obtain a porous layer thinner than the doped layer, forming a non-porous layer on the porous layer to prepare a first article, bonding the first article and a second article so as to produce a multilayer structure having the porous layer in the inside thereof, and separating the multilayer structure along the porous layer.

Abstract: The present invention relates to a method of manufacturing an avalanche diode of determined threshold in a substrate of a first conductivity type with a low doping level, including the steps of diffusing in the substrate at least one first region of the first conductivity type; diffusing in the substrate a second region of the second conductivity type protruding from the first region. The opening of a mask of definition of the first region has a lateral extent smaller than the diffusion depth of the first region in the substrate, this lateral extent being chosen all the smaller as the desired avalanche threshold is high.

Abstract: A SOI device, comprising: a SOI wafer having a stack structure of a silicon substrate, a buried oxide layer having a first and a second contact holes and a silicon layer; an isolation layer formed in the silicon layer to define a device formation region; a transistor including a gate formed over the device formation region of the silicon layer defined by the isolation layer, source and drain regions formed at the both side of the gate in the device formation region, and a channel region which is a portion of the device formation region between the source and drain region; a conduction layer being contacted with the buried oxide layer; an impurity region for well pick-up formed in the silicon layer to be contacted with the buried oxide layer; a first contact layer formed within the first contact hole of the buried oxide layer to electrically connect the channel region of the transistor and the conduction layer; and a second contact layer formed with the second contact hole of the buried oxide layer to electri

Abstract: Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on transmutation doping in which naturally occurring isotopes present in the silicon are converted to phosphorus. Several methods for bringing about the transmutation doping are available including neutron, proton, and deuteron bombardment. By using suitable masking, the bombardment effects can be confined to specific areas which then become the isolation moats. Four different embodiments of the invention are described together with processes for manufacturing them.

Abstract: An integrated circuit fabrication process is provided for incorporating barrier atoms, preferably nitrogen atoms, within a barrier layer. The barrier layer is interposed between the gate dielectric and the semiconductor substrate. The barrier layer serves to inhibit the passage of dopants from the gate conductor into the channel area. The barrier layer is preferably a nitrogen doped silicon epitaxial layer. The barrier layer may be composed of two layers, a silicon epitaxial layer and a nitrogen doped epitaxial layer formed upon the silicon epitaxial layer.