Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is

Abstract: A method for manufacturing a semiconductor device includes: forming a groove in a semiconductor substrate and embedding an element isolation film made of a silicon oxide film in the groove; forming a silicon nitride film on the element isolation film; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and removing the silicon nitride film.

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.

Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

Abstract: A semiconductor process and apparatus provides an encapsulated shallow trench isolation region by forming a silicon nitride layer (96) to cover a shallow trench isolation region (95), depositing a protective dielectric layer (97, 98) over the silicon nitride layer (96), and polishing and densifying the protective dielectric layer (97, 98) to thereby form a densified silicon nitride encapsulation layer (99) over the shallow trench isolation region (95).

Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

Abstract: The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same.

Abstract: Field effect devices and ICs (80, 82, 84) with very low gate-drain capacitance Cgd are provided by forming a substantially empty void (70, 100) between the gate (60?) and the drain (27) regions. For vertical FETS a cavity (70, 100) is etched in the semiconductor (SC) (40) and provided with a gate dielectric liner (54, 92). A poly-SC gate (60?) deposited in the cavity (50) has a central fissure (empty pipe) (63) extending through to the underlying SC (40). This fissure (63) is used to etch the void (70, 100) in the SC (40) beneath the poly-gate (60?). The fissure (63) is then closed by a dielectric plug (74, 84, 102) formed by deposition or oxidation without significantly filling the etched void (70, 100). Conventional process steps are used to provide the source (24) and body regions (25) around the cavity (50) containing the gate (60?), and to provide a drift space (26) and drain region (27) below the body region (25).

Abstract: A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the device isolation area of the substrate, the first-conductivity-type doping area surrounding the isolation area and a dielectric layer formed between the isolation layer and the first-conductivity-type doping area, wherein the first-conductivity-type doping area and the dielectric layer are located between the isolation layer and a second-conductivity-type diffusion area.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.

Abstract: By forming a non-oxidizable liner in an isolation trench and selectively modifying the liner within the isolation trench, the stress characteristics of the isolation trench may be adjusted. In one embodiment, a high compressive stress may be obtained by treating the liner with an ion bombardment and subsequently exposing the device to an oxidizing ambient at elevated temperatures, thereby incorporating silicon dioxide into the non-oxidizable material. Hence, an increased compressive stress may be generated within the non-oxidizable layer.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region, a gate electrode of a memory cell transistor formed by depositing an electrical charge storage layer formed on an upper surface of the gate insulating film, a second gate insulating film and a control gate insulating film sequentially, an element isolation insulating film buried in each trench and formed from a coating type oxide film, and an insulating film formed inside each trench on a boundary between the semiconductor substrate and the element isolation insulating film, the insulating film containing nontransition metal atoms and having a film thickness not more than 5 ?.

Abstract: Methods of curing a silicon oxide layer on a substrate are provided. The methods may include the processes of providing a semiconductor processing chamber and a substrate and forming an silicon oxide layer filling a portion of a trench on the substrate, the silicon oxide layer including carbon species as a byproduct of formation. The methods also include introducing an acidic vapor into the semiconductor processing chamber, the acidic vapor reacting with the silicon oxide layer to remove the carbon species from the silicon oxide layer. The methods may further include depositing additional silicon oxide over the cured silicon oxide to fill the trench. The methods may also include removing the acidic vapor from the semiconductor processing chamber.

Abstract: The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

Abstract: A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the method includes applying a recess region and a bulb-type recess region to the above-extended active region so as to prevent generation of horns in the active regions. This structure results in improvement in effective channel length and area.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming an opening extending from the top surface into the semiconductor substrate; and performing a first deposition step to fill a first dielectric material into the opening. The first dielectric material is then recessed. A second deposition step is performed to fill a remaining portion of the opening with a second dielectric material. The second dielectric material is denser than the first dielectric material. The second dielectric material is recessed until a top surface of the second dielectric material is lower than the top surface of the semiconductor substrate.

Abstract: A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.

Abstract: A manufacturing method for a semiconductor device includes generating on a substrate liquid-phase silanol having fluidity by causing a source gas made of a material containing silicon to react with a source gas made of a material containing oxygen, introducing the silanol into a first recess having an aspect ratio of a predetermined value wholly, and introducing the silanol into a space from a bottom to an intermediate portion in a second recess having an aspect ratio lower than the predetermined value, the first and second recesses are provided in the substrate, burying a silicon oxide film in the first recess and providing the silicon oxide film in the second recess by converting the silanol into the silicon oxide film by dehydrating condensation, and providing a dielectric film having film density higher than that of the silicon oxide film on the silicon oxide film.

Abstract: Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.

Abstract: A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher than that in the bottom sidewall of the trench, forming a spin-on dielectric layer filling the trench and covering the surface of the semiconductor substrate, performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall. Since the nitrogen-containing dopants can inhibit the oxidation rate and the concentration of the nitrogen-containing dopants in the upper inner sidewall is higher than that in the bottom inner sidewall of the trench, the thickness of the silicon oxide layer formed by the thermal oxidation process is larger at the bottom portion than at the upper portion of the trench.

Abstract: An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.

Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.

Abstract: A method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN) is provided. The method includes providing a substrate having a trench in a reaction chamber. Next, a first deposition step is performed to partially fill a dielectric material in the trench. Then, an etch step is performed to partially remove the dielectric material in the trench. Thereafter, a second deposition step is performed to partially fill the dielectric material in the trench. A reaction gas used in the second deposition step includes a carrier gas, an oxygen-containing gas, a silicon-containing gas, and a hydrogen-containing gas. After the carrier gas and oxygen-containing gas are introduced into the reaction chamber and a radio frequency (RF) power is turned on for a period of time, the silicon-containing gas and hydrogen-containing gas are introduced into the reaction chamber.

Abstract: A method for forming an isolation structure in a semiconductor device including a substrate having a first region and a second region, the second region having an isolation structure formed to a larger width than a plurality of isolation structures formed in the first region, is provided. The method includes etching portions of the first and second regions of the substrate to form first and second trenches, wherein a width of the second trench is larger than that of the first trench, forming a first insulation layer to fill a portion of the first and second trenches, forming a barrier layer to fill the first and second trenches, etching portions of the first insulation layer and the barrier layer in the first region, removing the barrier layer, and forming a second insulation layer over the first insulation layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device can include a semiconductor substrate including a trench, a first oxide layer in the trench, a second oxide layer filled in the trench to form an insulating layer, and a silicon nitride layer interposed between the first and second oxide layers. The silicon nitride layer can be etched such that the silicon nitride layer is recessed from top surfaces of the semiconductor substrate and the second oxide layer, thereby forming a divot at a top corner of the trench.

Abstract: A method of manufacturing a semiconductor device begins when a first dielectric pattern is formed on and/or over a substrate, and a first etching process is performed to form a trench in the substrate. An edge portion of the first trench is exposed. An oxidation process is performed on and/or over the substrate rounding the edge portion of the trench. A second dielectric is formed on and/or over the substrate including the trench, and a planarization process is performed on the second dielectric. A photoresist pattern is formed on and/or over the second dielectric corresponding to the trench, and a second etching process is performed to form a second dielectric pattern filling the trench. The photoresist pattern is removed. A second cleaning process is performed on the substrate including the trench to form a device isolation layer, which is formed by removing a portion of the second dielectric pattern.

Abstract: A method of fabricating a semiconductor device includes forming trench-like recesses in a semiconductor substrate, the recesses including one or more recesses each of which has an opening width of not more than a predetermined value, forming a first insulating film above the substrate after the recesses have been formed, so that one or a plurality of voids are formed in the one or more recesses whose opening widths are not more than the predetermined value, removing part of the first insulating film so that a beam is left which spans the openings so that the beam passes over upper surfaces of the one or more recesses and so that at least the voids are exposed in a portion of the substrate except the beam, and filling the voids in the recesses with a material with fluidity, thereby forming second insulating films in the recesses.

Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is

Abstract: A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.

Abstract: Methods of fabricating a semiconductor device that is capable of reducing and/or maintaining a proper divot depth at the corners of a device isolation layer. The method includes forming a pad oxide layer and a pad nitride layer sequentially on a semiconductor substrate, forming a trench by selectively etching the pad oxide layer, the pad nitride layer and the semiconductor substrate, depositing an insulating layer in the trench, selectively etching the pad nitride layer and the insulating layer by performing a first etching process, removing the pad nitride layer by performing a second etching process, and forming a gate polysilicon layer over the entire surface of the semiconductor substrate.

Abstract: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.

Abstract: A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, forming a first liner nitride layer on an exposed surface of the trench, forming a first high density plasma (HDP) oxide layer such that the first HDP oxide layer partially fills the trench to cover a bottom surface and a side surface of the trench and an upper surface of the first liner nitride layer, etching overhangs generated during the forming of the first HDP oxide layer by introducing a hydrofluoric acid (HF) solution into the semiconductor substrate, forming a second liner nitride layer over the first HDP oxide layer, removing the second liner nitride layer formed on the first HDP oxide layer while forming a second HDP oxide layer to fill the trench, and subjecting the second HDP oxide layer to planarization, so as to form a trench isolation layer.

Abstract: Provided may be a method of manufacturing a semiconductor device. The method may include forming a plurality of isolation patterns including conductive patterns on a semiconductor substrate and forming gaps between the isolation patterns, forming active patterns filling the gaps on the semiconductor substrate, forming a gate insulation layer on the isolation patterns and the active patterns, and forming gate patterns on the gate insulation layer.

Abstract: A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench.

Abstract: A method for forming an isolation structure in a semiconductor device includes preparing a semi-finished substrate including a trench. An oxide layer is formed over sidewalls of the trench. A multiple layer structure of liner layers is formed over the oxide layer. An insulation layer is formed over the multiple layer structure such that the insulation layer fills an inside of the trench. The insulation layer is planarized.

Abstract: A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS·FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.

Abstract: An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes forming a hard mask pattern on a semiconductor substrate, wherein the hard mask pattern covers active regions; forming a trench in the semiconductor substrate within an opening defined by the hard mask pattern; filling the trench with a dielectric material, resulting in a trench isolation feature; performing an ion implantation to the trench isolation feature using the hard mask pattern to protect active regions of the semiconductor substrate; and removing the hard mask pattern after the performing of the ion implantation.

Abstract: According to a fabrication method for an element isolation structure section, that is, STI, of the present invention, by differing the etching rate of material to be embedded in a narrow-width, that is, a small area trench section (first trench section) formed in a small isolation area, from the etching rate of a material to be embedded in a wide-width (plane shape of larger area) trench section (second trench section) formed in a large isolation area, in the etching step, dishing (recessing) that inevitably occurs in a CMP step can be reduced. Therefore, a STI having a higher level of flatness can be formed. As a result, by simple steps, deterioration of the electrical characteristics of elements that are element-isolated by STI can be reduced. That is to say, not only STI having excellent electrical characteristics, but also a semiconductor device provided with such STI, can be provided at a good level of production yield.

Abstract: A deposition method for releasing a stress buildup of a feature over a semiconductor substrate with dielectric material is provided. The feature includes lines separated by a gap. The method includes forming a liner layer over the feature on the semiconductor substrate in a chamber. A stress of the liner layer over the feature is released to substantially reduce bending of the lines of the feature. A dielectric film is deposited over the stress-released liner layer to substantially fill the gap of the feature.

Abstract: Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.

Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

Abstract: A method of forming an insulating layer of a semiconductor device, the method including preparing a semiconductor substrate having a plurality of structures and gaps between adjacent structures, forming an insulating layer for oxygen supply on the semiconductor substrate, forming an SOG (spin-on-glass) layer on the insulating layer for oxygen supply to fill the gaps, and curing the SOG layer, wherein the insulating layer for oxygen supply supplies oxygen to the SOG layer during curing of the SOG layer.

Abstract: A method for forming shallow trench isolation in a semiconductor device. The method includes forming a trench in a predetermined depth on a semiconductor substrate, filling the trench with a first filing oxide, injecting an impurity into a portion of the first filling oxide inside the trench, removing the portion of the first filling oxide by wet etching, and filling the trench with a second filling oxide.

Abstract: A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.

Abstract: A method of forming a device isolation film of a semiconductor device is provided. The method of forming a device isolation film of a semiconductor device according to an embodiment includes forming the device isolation film by ion-implanting insulation materials inside of a trench formed on a semiconductor substrate.

Abstract: A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the method includes applying a recess region and a bulb-type recess region to the above-extended active region so as to prevent generation of horns in the active regions. This structure results in improvement in effective channel length and area.

Abstract: The present invention provides a semiconductor device that reduces the junction leak current and achieves an improvement in the reliability of the gate oxide film by minimizing divot formation and the occurrence of a kink and a method of manufacturing such a semiconductor device. A pad oxide film and a silicon nitride film are formed on an Si substrate and a groove-like trench is formed through photolithography and etching. The liner oxide of the trench are oxidized through oxidizing/nitriding. Then, the trench is filled with an insulating film, the insulating film is planarized and the silicon nitride film and the pad oxide film are removed. Next, a field area is formed and a transistor is formed by following specific steps. By forming a trench liner oxide film containing nitrogen, stress is reduced.