Abstract: A new method is provided for the creation of a Shallow Trench Isolation region. A layer of pad oxide is deposited on the surface of a substrate; a layer of nitride is deposited over the layer of pad oxide. The layers of pad oxide and nitride are patterned and etched over the region where the STI is to be formed, a trench is etched in the silicon for the STI region. A layer of TEOS, that serves as a buffer spacer oxide, is deposited over the surface of the layer of nitride thereby including the inside of the created trench. The layer of TEOS is etched removing the TEOS from the surface of the nitride and from the bottom of the trench but leaving a layer of TEOS in place along the sidewalls of the trench. The bottom of the trench is next etched after which the TEOS spacer buffer is removed from the sidewalls of the trench. The sidewalls of the trench now have a non-linear profile.

Abstract: A separating region and a method of forming a separating region of a semiconductor device is provided that increases reliability of the device by isolating respective gate electrodes. The separating region and method prevent voids from being formed within a trench of the separating region. The method of forming the separating region includes forming patterns of first insulating layers on a semiconductor substrate by selectively etching the first insulating layers to have at least one opening disposed in a defined region of the semiconductor substrate, forming side walls of a second insulating layer on both lateral sides of the patterns of the first insulating layers, and etching the side walls of the second insulating layer and the exposed semiconductor substrate using the patterns of the first insulating layers as a mask to form trenches in the semiconductor substrate. Since a selectively ratio of the sidewalls and the semiconductor substrate is preferably 1:1, the trenches have a prescribed shape and depth.

Abstract: A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.

Abstract: An isolation method in the fabrication process of a semiconductor device is provided. The method forms an oxide layer as a buffer layer for reducing stress through chemical vapor deposition (CVD). By the method, a first pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate, and then an silicon nitride layer pattern is formed by patterning, and undercuts are formed in the first pad oxide layer pattern. Subsequently, a second pad oxide layer is formed on the entire surface of the semiconductor substrate through CVD, and then spacers are formed on the sidewalls of both the patterned first pad oxide layer and silicon nitride layer and a field oxide layer is formed through thermal oxidation. Alternatively, a silicon layer is deposited without the spacers to form the field oxide layer. The second pad oxide layer is a buffer layer for buffering stress during formation of the field oxide layer.

Abstract: A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges and protects the field oxide from gouging during post-gate processing, such as during the local interconnect etch, thereby allowing the formation of high-quality implanted junctions. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited in the trench on the oxide liner and on the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench is anisotropically etched, to remove the polish stop at the bottom of the trenches leaving a portion overlying the side surfaces and edges of the trench on the oxide liner.

Abstract: A method for forming an element isolating film of a semiconductor device, which is capable of achieving a reduction in topology and a reduction in the occurrence of a bird's beak phenomenon, so that subsequent processes can be easily carried out to fabricate highly integrated semiconductor devices.

Abstract: The method in the present invention is proposed for forming trench isolation in a semiconductor substrate. The method includes the steps as follows. At first, a pad layer is formed over the substrate. A first stacked layer is then formed over the pad layer. Next, a second stacked layer is formed over the first stacked layer. An opening is defined in the second stacked layer, the first stacked layer, and the pad layer. The opening extends down to the substrate. A portion of the substrate is then removed for forming an upper-half portion of a trench by using the second stacked layer as a mask. A sidewall structure is formed on the opening. Next, a portion of the substrate is removed for forming a lower-half portion of the trench by using the sidewall structure as a mask. The sidewall structure and the second stacked layer are removed. Following with the formation of a first insulating layer over the trench, a second insulating layer is formed over the first insulating layer and over the first stacked layer.

Abstract: A method for forming a field oxide film of a highly integrated semiconductor device, in which an annealing step is carried out during a field oxide film formation step for growing the field oxide film adapted to isolate elements of the semiconductor device. By the annealing step, it is possible to prevent a stress concentration phenomenon from occurring in a semiconductor substrate on which the field oxide film is formed, thereby reducing or eliminating a field oxide thinning phenomenon.

Abstract: A method for forming a shallow trench isolation structure in a substrate includes the steps of forming a doped region around the future top corner regions of a trench. The concentration of dopants inside the doped region increases towards the substrate surface. Thereafter, a trench is formed in the substrate, and then a thermal oxidation operation is carried out. Utilizing the higher oxidizing rate for doped substrate relative to an undoped region, the upper corners of the trench become rounded corners. Subsequently, a liner oxide layer is formed over the substrate surface inside the trench using conventional methods. Finally, insulating material is deposited into the trench to form a trench isolation structure.

Abstract: Field isolation regions are formed using oxidation-resistant spacers or plugs that completely fill trenches within a semiconductor substrate prior to forming the field isolation regions. The spacers or plugs help to reduce encroachment of the field isolation regions under the spacers or plugs. The structure used as an oxidation mask for the field isolation process may include a silicon-containing member that is thicker than an overlying oxidation-resistant member. The thicker silicon-containing member may be capable of tolerating higher stress before defects in an underlying pad layer or substrate are formed.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: The preferred embodiment of the present invention overcomes the disadvantages of the prior art by using hybrid resist to define a sidewall spacer region and form a new type of sidewall spacer. The preferred method allows for more controlled doping at the gate-source and gate-drain junctions by defining sidewall spacer troughs using hybrid resist. Implants can then be made through the troughs to precisely control the doping at the gate junctions. Additionally, sidewall spacers can then be formed in the sidewall spacer troughs. The dimensions of the sidewall spacers is determined by the hybrid resist and can thus be made smaller than traditional resist processes. Additionally, forming the sidewall spacers using hybrid resist allows for their width to be determined independent of the depth of the gate material.

Abstract: A novel semiconductor fabrication process having the advantages of conventional LOCOS (process simplicity and reduced defects) while providing a scaleable, planar isolation region between active regions formed in a semiconductor substrate. The preferred process includes formation of a barrier layer and a masking layer over the substrate. An active region mask defines an exposure region of the masking layer. The exposure region is etched to form an opening, exposing a portion of barrier layer in the opening. A spacer is added inside the opening, around a perimeter of the opening to define a second exposure region. The barrier layer, and substrate, under the second exposure region, but not under the spacer, are etched to form an isolation region opening. The isolation region opening may have a suitable isolating material, such as silicon oxide, grown, filled, or some combination of both, in the isolation region opening.

Abstract: A method is provided for forming isolated regions of oxide of an integrate circuit, and an integrated circuit formed according to the same. A plurality of active areas is formed in an upper surface of a portion of a substrate body. A field oxide region is formed which separates at least two of the plurality of the active areas, wherein an upper surface of the field oxide region is substantially planar with an upper surface of the substrate body. Nitride spots are formed in the bulk of the field oxide region and not in the active area which do not need to be removed since they do not effect device integrity.

Abstract: A method for forming an isolation region in an integrated circuit is disclosed. The method includes forming a pad layer on a semiconductor substrate, and forming an oxidation masking layer on the pad layer, wherein the pad layer relieves stress from the oxidation masking layer. Next, portions of the oxidation masking layer and the pad layer are patterned and etched. A first oxide layer is thermally grown on the substrate, and a second oxide spacer is formed on a sidewall of the pad layer and the oxidation masking layer. After forming a nitride spacer on a surface of the second oxide spacer, the substrate is thermally oxidized to form the isolation region in the substrate.

Abstract: A method for forming a semiconductor device comprises the steps of forming an oxide over a silicon layer, forming a blanket first nitride layer over the oxide layer and the silicon layer, and etching the first nitride layer and the oxide layer to form a sidewall from at least the oxide layer and the first nitride layer. Next, a second nitride layer is formed over the sidewall and an oxidizable layer is formed over the second nitride layer. The oxidizable and the second nitride layers are etched to form a spacer from the oxidizable layer from and the second nitride layer, and the oxidizable and the silicon layers are oxidized.

Abstract: A method of forming an isolation layer of a semiconductor device including active regions on a substrate and device isolation regions for isolating the active regions from one another includes the steps of forming a nitride layer on the active region of a semiconductor substrate, forming trenches of a predetermined depth in the semiconductor substrate at peripheral portions of the device isolation regions, and filling the trenches with a nitride material and performing a field oxidation process.

Abstract: A method for forming an element isolating film of a semiconductor device, which is capable of achieving a reduction in topology and a reduction in the occurrence of a bird's beak phenomenon, so that subsequent processes can be easily carried out to fabricate highly integrated semiconductor devices.

Abstract: A method for fabricating a semiconductor device including a silicon substrate and plural silicon stacks thereon includes forming a nitride shield layer on the substrate and stacks to cover the stacks, such that the stacks are protected from loss of critical dimension during subsequent isolation trench formation and oxidation. In other words, the edge of each stack, and thus the critical dimension of the silicon layers of the stack, is protected from oxidation by the nitride shield layer.

Abstract: Oxide isolation regions are fabricated for integrated circuit substrates by forming a pad layer on an integrated circuit substrate and forming a silicon nitride mask on the pad layer. The mask exposes a portion of the pad layer. The exposed portion of the pad layer is thinned to thereby define a pad layer sidewall. A silicon nitride layer is formed on the silicon nitride mask, on the thinned pad layer and on the pad layer sidewall. The silicon nitride layer is selectively etched to form a silicon nitride spacer on the pad layer sidewall. The integrated circuit substrate is then oxidized, using the silicon nitride mask and the silicon nitride spacer as an oxidation mask, to thereby form an oxide isolation region in the thinned portion of the pad layer and in the integrated circuit substrate beneath the pad layer.

Abstract: A method and structure are provided for a spacer shell structure which is formed of dielectric materials seletive to one another. The dielectric materials can be configured into a chosen geometric arrangement. The isolation properties of the spacer shell can be scaled to meet a given set of isolation requirements as determined by the size and density of the IGFET devices being isolated. The method to fabricate the novel spacer shell maintains costly fabrication steps at a minimum. The isolation ability of the novel spacer shell preserves the operation integrity of neighboring IGFET devices. Electrical shorts between adjacent devices are prevented. Capacitive coupling between neighboring IGFET structures is likewise minimized.

Abstract: Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxi

Abstract: A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces.

Abstract: A method for forming an isolation region in a semiconductor substrate is disclosed. The present invention includes forming an insulating layer on the semiconductor substrate, and then forming a dielectric layer on the insulating layer. After patterning to etch portions of the dielectric layer, the insulating layer and the semiconductor substrate are etched using the patterned dielectric layer as a mask, thereby forming a trench in the semiconductor substrate. Next, a first silicon oxide layer is formed over the semiconductor substrate, and the first silicon oxide layer is then anisotropically etched to form a spacer on the sidewalls of the trench. Thereafter, the semiconductor substrate is thermally oxidized to form a field oxide region over the semiconductor substrate, and a second silicon oxide layer is then formed over the field oxide region. Finally, the second silicon oxide layer is etched back until surface of the dielectric layer is exposed.

Abstract: An integrated circuit device is isolated by forming a pad oxide layer on an integrated circuit substrate. A mask pattern is formed on the pad layer. The mask pattern includes sidewalls which selectively expose the pad oxide layer between the sidewalls. A silicon spacer is formed on the sidewalls. An oxidation barrier film is formed on the silicon spacer and on the exposed pad oxide layer. The integrated circuit substrate is then oxidized through the oxidation barrier film to form a device isolating layer. The oxidation barrier film on the exposed pad oxide layer is thinner than the oxidation barrier film on the sidewalls. Thus, oxidation of the silicon spacer is delayed relative to the substrate.

Abstract: Formation of parasitic edge transistors at upper edges of trenches formed on a substrate of an integrated circuit is suppressed by implanting dopants into trench regions of the IC substrate before the trenches are formed in the trench regions by reactive ion etching. The widths of the trenches formed in the trench regions are narrower than the widths of the doped regions of the trench regions. The doped regions of the trench regions are formed by first implanting dopants into the trench regions and then heat treating the implanted regions to activate the dopants and to diffuse the dopants laterally from the implanted regions.

Abstract: A method for fabricating an isolation layer of a semiconductor device defines an active region and an isolation region on a semiconductor substrate. An active pattern is formed on the active region of the semiconductor substrate and the active pattern includes a first insulating layer and a first oxidation stop layer formed on the first insulating layer. A first isolation layer is grown over the substrate corresponding to the isolation region and the first isolation layer is selectively etched by using the first oxidation stop layer as a mask. A sidewall spacer is formed adjacent to the active pattern including a remaining portion of the first isolation layer, and the sidewall spacer includes a second insulating layer and a second oxidation stop layer formed on the second insulating layer. A second isolation layer is grown over the substrate.

Abstract: The invention is a process for filling narrow isolation trenches with thermal oxide using a nitride spacer and a second trench etch. The method begins by providing forming a pad oxide layer 20 and a first nitride layer 30 over a substrate. A first opening is formed in the pad oxide layer 20 and first nitride layer 30. The substrate is then etched through the first opening forming a first trench 40 in the substrate. A thin oxide film 50 is then grown over the substrate in the bottom and sidewalls of the first trench 40. Nitride spacers 60 are grown over the sidewalls of the first trench and over the thin oxide layer 40 on the sidewalls of the trench. A portion of the thin oxide film 50 on the bottom of the trench is etched. The substrate in the bottom of the first trench is etched forming a second trench 70. The etch exposes portions of the substrate on the bottom of the deeper second trench.

Abstract: A method for isolating the elements of semiconductor devices, in which bird's beak can be restrained by accumulating nitrogen atoms between a pad oxide film and a silicon substrate and the etch depth of a silicon substrate can be controlled by use of wet etch to remove the oxide which is grown on the silicon substrate at a low temperature after formation of nitride spacer, thereby reproducing good profiles of the field oxide film.