Plural Oxidation Steps To Form Recessed Oxide Patents (Class 438/452)
  • Patent number: 6444539
    Abstract: A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: September 3, 2002
    Assignees: Advanced Micro Devices, Inc., Fujitsu Limited
    Inventors: Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark Chang, Chi Chang, Hung-Sheng Chen
  • Patent number: 6420241
    Abstract: A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad insulator pattern. After an insulator spacer is formed at the side wall of the pad insulator pattern, the exposed region of the semiconductor substrate is thermally oxidized to grow an oxide which is, then, removed to form a recess. An element isolation film is formed in the recess by break-through field oxidation and high temperature field oxidation. The element isolation film thus obtained can prevent the field oxide “ungrowth” phenomenon and at the same time mitigate the field oxide thinning effect as well as improve the properties of the gate oxide.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: July 16, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Se Aug Jang, Young Bog Kim, In Seok Yeo, Jong Choul Kim
  • Patent number: 6333243
    Abstract: A method for forming field oxide isolation regions using oxygen implantation is described. An oxidation resistant layer such as silicon nitride is formed on a silicon substrate, and acts as an oxidation mask. An opening is then formed in the nitride layer, where field oxide is desired. In one embodiment of the invention, oxygen is implanted into this opening, followed by thermal oxidation. In a second embodiment of the invention, the opening is thermally oxidized, followed by a deep oxygen implant and anneal. Encroachment of the field oxide under the nitride layer is decreased, resulting in a minimum “birds' beak” length.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: December 25, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Michael Nuttall, Pai-Hung Pan
  • Patent number: 6326284
    Abstract: A semiconductor device produced by forming an oxide film on a substrate, heat treating the oxide film at a temperature of 800° C. or higher in an inert atmosphere, followed by conventional steps for formation of a transistor, is improved in electrical reliability due to relaxation of stress generated in the oxide film or in the surface of substrate.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: December 4, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasuhide Hagiwara, Hiroyuki Ohta, Asao Nishimura
  • Publication number: 20010029085
    Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material.
    Type: Application
    Filed: May 14, 2001
    Publication date: October 11, 2001
    Inventor: Viju K. Mathews
  • Publication number: 20010014506
    Abstract: A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad insulator pattern. After an insulator spacer is formed at the side wall of the pad insulator pattern, the exposed region of the semiconductor substrate is thermally oxidized to grow an oxide which is, then, removed to form a recess. An element isolation film is formed in the recess by break-through field oxidation and high temperature field oxidation. The element isolation film thus obtained can prevent the field oxide “ungrowth” phenomenon and at the same time mitigate the field oxide thinning effect as well as improve the properties of the gate oxide.
    Type: Application
    Filed: April 17, 1998
    Publication date: August 16, 2001
    Inventors: SE AUG JANG, YOUNG BOG KIM, IN SEOK YEO, JONG CHOUL KIM
  • Patent number: 6265286
    Abstract: A method of fabricating a semiconductor device which includes providing a silicon substrate having a patterned mask thereover to expose a portion of the surface of the substrate. The exposed surface portion is oxidized to form a sacrificial silicon oxide region to a predetermined depth in the substrate at the exposed portions of the substrate. The sacrificial silicon oxide is then removed by a HF etch and a second region of silicon oxide is formed in the substrate in the region from which the sacrificial silicon oxide was removed. The step of removing the silicon oxide also includes removing a portion of the pad oxide. The sacrificial silicon oxide has a thickness less than the second region of silicon oxide which is from about 10 percent to about 30 percent of the thickness of the second region of silicon oxide. The oxidation steps are thermal oxidation steps in an oxygen-containing ambient.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: July 24, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Michelle A. Boyer, Sarma Gunturi, Catherine M. Huber
  • Patent number: 6261926
    Abstract: The present invention provides a method for fabricating a field oxide on a semiconductor substrate. A first pad layer and a first mask layer is formed successively on the semiconductor substrate. An opening is formed in the first mask layer to define a region for forming the field oxide. A first field oxide is formed in the opening, which is then removed to form a concave portion. The first pad layer exposed by the concave portion is removed to form a cavity. A second pad layer having a smaller thickness than the first pad layer is formed on the semiconductor substrate. A mask portion is formed in the sidewall of the patterned first mask layer and the cavity. The mask portion in the sidewall of the patterned first mask layer has a thickness less than 300 Å. Finally, thermal oxidation is carried out to form a second field oxide in the concave portion.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: July 17, 2001
    Assignee: Mosel Vitelic, Inc.
    Inventor: Wei-Shang King
  • Patent number: 6245644
    Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: June 12, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Viju K. Mathews
  • Patent number: 6221732
    Abstract: A method of producing a semiconductor device comprising the steps of: (a) forming partially an SOI structure portion comprising an insulation layer and a semiconductor layer on a semiconductor substrate; (b) forming selectively a first oxidation-resistant film on a region other than device isolation region-forming portions of the SOI structure portion and of an exposed portion of the semiconductor substrate; (c) forming an oxide film in the device isolation region-forming portions of the semiconductor substrate and of the SOI structure portion under such condition that the semiconductor layer of the SOI structure portion is oxidized up to the bottom of the semiconductor layer; (d) depositing a second oxidation-resistant film over the entire surface of the resultant obtained by the above steps (a) to (c); (e) etching away selectively the second oxidation-resistant film on the exposed portion of the semiconductor substrate using a resist mask so patterned as to cover the SOI structure portion; (f1) implanting a
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: April 24, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Seiji Kaneko
  • Patent number: 6187640
    Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below t
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: February 13, 2001
    Assignees: Fujitsu Limited, Advanced Micro Devices, Inc., Fujitsu Amd Semiconductor Limited
    Inventors: Hiroyuki Shimada, Masaaki Higashitani, Hideo Kurihara, Hideki Komori, Satoshi Takahashi
  • Patent number: 6133115
    Abstract: The invention relates to an improvement in formation of a gate electrode. In the invention, there are formed first and second oxides on a surface of a substrate. The second oxides have a top surface higher by a height H than top surfaces of the first oxides. A gate electrode composed of a polysilicon film and a silicide film deposited on the polysilicon film is formed so that the polysilicon film is planarized at a level higher than top surfaces of the first oxides but lower than top surfaces of the second oxides. The invention prevents excessive etching of the polysilicon film without fabrication steps being increased, and thus makes it possible to form a gate electrode having a dimension defined by a mask.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: October 17, 2000
    Assignee: NEC Corporation
    Inventor: Tadashi Fukase
  • Patent number: 6133087
    Abstract: A semiconductor device having two or more types of separation oxide film are formed on the substrate of the semiconductor device by different methods so as to correspond with element types formed on the same semiconductor substrate. The method for producing the semiconductor device comprises a first separation oxide film formation process, and a second separation oxide film formation process. In the first separation oxide film formation process, a first mask layer is formed on the semiconductor substrate, the first mask layer of the element separation region of the logic element is selectively removed and the semiconductor substrate in the region area selectively oxidized. In second separation oxide film formation process, the remaining first mask layer is removed, a second mask layer is formed, the second mask layer of the element separation region of DRAM elements is then selectively removed, and the semiconductor substrate of the region is selectively oxidized.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: October 17, 2000
    Assignee: NEC Corporation
    Inventor: Iwao Shirakawa
  • Patent number: 6127247
    Abstract: The present invention proposes a method for forming vertically modulated wells in a semiconductor substrate. The method can include the steps as follows. At first, isolation regions are formed over the substrate. A pad layer is then formed over the substrate and a photoresist layer is formed over the pad layer. Then, p-well regions are defined by removing portions of the photoresist layer. Next, first p-wells are formed in the substrate under the p-well regions. After forming a masking layer over the p-well regions, the photoresist layer is removed. A first thermal process is then performed. Second p-wells are formed in the substrate at a level below the first p-wells. Next, n-wells are formed in the substrate under regions uncovered by the masking layer and above the second p-wells. The masking layer and the pad layer are then removed. Finally, a second thermal process is performed to finish the formation of vertically modulated wells.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: October 3, 2000
    Assignee: Texas Instruments - Acer Incorporated
    Inventor: Shye-Lin Wu
  • Patent number: 6121116
    Abstract: The present invention provides novel isolation regions (501, 215) in a flash memory integrated circuit device. The isolation regions (501, 215) are formed on a silicon substrate (201), which has a core memory region (e.g., flash memory cell region) and a high voltage region (e.g., high voltage MOS device region). A silicon dioxide layer (e.g., silicon dioxide, silicon oxynitride) (203) is defined overlying the substrate including both of the regions. A nitride mask layer (205) is formed overlying the silicon dioxide layer in the core memory region and the high voltage region. This nitride mask layer exposes (207) a first isolation region coupled to the high voltage region. The first isolation region includes a first isolation structure having a first thickness of silicon dioxide. A step of oxidizing an exposed second isolation region to form the second isolation structure (215) and simultaneously oxidizing the first isolation structure to a second thickness is included.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: September 19, 2000
    Assignee: Mosel Vitelic, Inc.
    Inventor: Kuo-Tung Sung
  • Patent number: 6096583
    Abstract: In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: August 1, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Yasuo Inoue
  • Patent number: 6074933
    Abstract: Undesirable birds beak pull back due to ion implant damage is alleviated by additional oxide growth.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: June 13, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Yi Ma, Pradip Kumar Roy
  • Patent number: 6054368
    Abstract: A method and structure for forming a modified field oxide region having increased field oxide threshold voltages (V.sub.th) and/or reduced leakage currents between adjacent device areas is achieved. The method involves forming a field oxide using the conventional local oxidation of silicon (LOCOS) using a patterned silicon nitride layer as a barrier to oxidation. After forming the LOCOS field oxide by thermal oxidation and removing the silicon nitride, a conformal insulating layer composed of silicon oxide is deposited and anisotropically etched back to form sidewall insulating portions over the bird's beak on the edge of the LOCOS field oxide, thereby forming a new modified field oxide. P-channel implants are formed in the device areas. Then a second implant is used to implant through the modified field oxide to provide channel-stop regions with modified profiles that increase the field oxide V.sub.th and/or reduce leakage current between device areas.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: April 25, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chue-San Yoo, Cheng-Yeh Shih
  • Patent number: 6027984
    Abstract: A method for forming field oxide isolation regions using oxygen implantation is described. An oxidation resistant layer such as silicon nitride is formed on a silicon substrate, and acts as an oxidation mask. An opening is then formed in the nitride layer, where field oxide is desired. In one embodiment of the invention, oxygen is implanted into this opening, followed by thermal oxidation. In a second embodiment of the invention, the opening is thermally oxidized, followed by a deep oxygen implant and anneal. Encroachment of the field oxide under the nitride layer is decreased, resulting in a minimum "birds' beak" length.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: February 22, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Michael Nuttall, Pai-Hung Pan
  • Patent number: 6013561
    Abstract: A method for forming a field oxide film of a highly integrated semiconductor device, in which an annealing step is carried out during a field oxide film formation step for growing the field oxide film adapted to isolate elements of the semiconductor device. By the annealing step, it is possible to prevent a stress concentration phenomenon from occurring in a semiconductor substrate on which the field oxide film is formed, thereby reducing or eliminating a field oxide thinning phenomenon.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: January 11, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Se Aug Jang, Byung Jin Cho, Jong Choul Kim
  • Patent number: 5989980
    Abstract: A semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate includes providing a semiconductor substrate having field and active area regions; forming masking material over the active area region and leaving the field region exposed, the masking material comprising first, second and third layers, and having a sidewall; exposing the semiconductor substrate to first oxidation conditions effective to form field isolation oxide of a first thickness over the exposed field region; forming an etch stop material layer over the sidewall; removing at least a portion of the third layer selectively relative to the etch stop material layer; and subjecting the semiconductor substrate to second oxidation conditions effective to grow the field isolation oxide to a second thickness on the exposed field region of the semiconductor substrate.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: November 23, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Roger R. Lee, Fernando Gonzalez
  • Patent number: 5985738
    Abstract: A method for forming a field oxide of a semiconductor device is disclosed, which takes advantage of wet oxidation at an early stage of field oxidation to prevent the ungrowth of field oxide and dry oxidation at a later stage of field oxidation to make the slope of field oxide positive, thereby improving the production yield and the reliability of semiconductor device.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: November 16, 1999
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Se Aug Jang, Young Bog Kim, Moon Sig Joo, Byung Jin Cho, Jong Choul Kim
  • Patent number: 5972779
    Abstract: A field oxide formation method involving a primary field oxidation, which is carried out at a predetermined low temperature to form a field oxide film having a thickness smaller than a target thickness, and a secondary field oxidation, which is carried out at a higher temperature capable of relatively reducing the occurrence of a field thinning phenomenon, to form the remaining thickness portion of the target field oxide film. The field thinning phenomenon involved in a field oxidation is reduced. The characteristics of a finally produced gate oxide film is also improved. Consequently, the throughput and reliability of semiconductor devices having gate oxide films are improved.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: October 26, 1999
    Assignee: Hyundai Electronics Industries
    Inventor: Se Aug Jang
  • Patent number: 5970364
    Abstract: A method for forming an isolation region in an integrated circuit is disclosed. The method includes forming a pad layer on a semiconductor substrate, and forming an oxidation masking layer on the pad layer, wherein the pad layer relieves stress from the oxidation masking layer. Next, portions of the oxidation masking layer and the pad layer are patterned and etched. A first oxide layer is thermally grown on the substrate, and a second oxide spacer is formed on a sidewall of the pad layer and the oxidation masking layer. After forming a nitride spacer on a surface of the second oxide spacer, the substrate is thermally oxidized to form the isolation region in the substrate.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: October 19, 1999
    Assignee: United Semiconductor Circuit Corp.
    Inventors: Hsiu-Wen Huang, Gary Hong
  • Patent number: 5966618
    Abstract: A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: October 12, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yu Sun, Tuan D. Pham, Mark T. Ramsbey, Chi Chang
  • Patent number: 5966621
    Abstract: A semiconductor processing method of forming field isolation oxide relative to a silicon substrate includes, i) rapid thermal nitridizing an exposed silicon substrate surface to form a base silicon nitride layer on the silicon substrate; ii) providing a silicon nitride masking layer over the nitride base layer, the base and masking silicon nitride layers comprising a composite of said layers of a combined thickness effective to restrict appreciable oxidation of silicon substrate thereunder when the substrate is exposed to LOCOS conditions; and iii) exposing the substrate to oxidizing conditions effective to form field isolation oxide on substrate areas not masked by the base and masking silicon nitride layers composite.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: October 12, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Hiang C. Chan
  • Patent number: 5930647
    Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: July 27, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Viju K. Mathews
  • Patent number: 5923994
    Abstract: A selective oxidation process includes conducting a former phase of an oxidation process employing a thick mask layer to produce an oxide layer having a thickness less than the finished thickness of a desired semiconductor device isolation insulator. Then the thickness of the mask layer is reduced and a latter phase of the oxidation process using the reducing thickness mask layer is performed to produce the desired semiconductor device isolation insulator having the ultimate thickness. The use of both a thick mask layer and a reduced thickness mask layer for various phases of the oxidation process limits both the growth of the bird's beak and the growth of crystalline defects in the bird's beak.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: July 13, 1999
    Assignee: Oki Electric Co., Ltd.
    Inventor: Yoshikazu Motoyama
  • Patent number: 5909629
    Abstract: A semiconductor processing method of forming field oxide regions on a semiconductor substrate includes, i) providing an oxidation resistant mask over a layer of oxide over a desired active area region on a semiconductor substrate, the mask having a central region and opposed sidewall edges, the oxide layer being thinner in the central region than at the sidewall edges; and ii) oxidizing portions of the substrate unmasked by the mask to form field oxide regions on the substrate. The oxidation resistant mask can be provided by depositing and patterning a nitride layer atop a pad oxide layer. Substrate area not covered the mask is oxidized to produce an oxide layer outside of the mask which is thicker than the pad oxide layer. A thin layer of nitride can then be deposited, and anisotropically etched to produce masking spacers which cover the thicker oxide adjacent the original mask. Mask lifting during subsequent oxidation is restricted, thus minimizing bird's beak encroachment and substrate defects.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: June 1, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Monte Manning
  • Patent number: 5909630
    Abstract: A field isolation process utilizes two or more isolation formation steps to form active areas on a semiconductor substrate. Each field isolation step forms a portion of the field isolation in a manner which reduces field oxide encroachment, in particular, by forming field oxide islands. The superposition of field isolation configurations define the desired active areas. A presently preferred dual-mask process may be carried out using a single masking stack, or more preferably using a masking stack for each isolation mask. The present isolation process further allows isolation features to be optimized for a variety of isolation requirements on the same integrated circuit.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: June 1, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Ceredig Roberts, Werner Juengling
  • Patent number: 5888871
    Abstract: Methods of forming EEPROM memory cells having uniformly thick tunnelling oxide layers include the steps of forming a preliminary field oxide isolation region of first thickness at a face of a semiconductor substrate of first conductivity type (e.g., P-type) and then forming a tunneling oxide layer on the face, adjacent the preliminary field oxide isolation region. The memory cell's drain region dopants are then implanted through the preliminary field oxide isolation region and into the substrate to form a preliminary drain region of second conductivity type. The preliminary field oxide isolation region is then grown to a second thickness greater than the first thickness by oxidizing the portion of the substrate containing the implanted dopants, to form a final field oxide isolation region which may have a thickness of about 2000 .ANG..
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: March 30, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-Kwan Cho, Keon-Soo Kim
  • Patent number: 5880009
    Abstract: A method for forming oxides on buried N.sup.+ -type regions in a memory cell fabrication process, suitable for forming oxides on the bury N.sup.+ -type regions before self-aligned MOS device etching, comprises: (1) implanting a high concentration of impurity into the buried N.sup.+ -type regions; (2) annealing the chip; and (3) executing a dry oxide process and then a wet oxidation process to the chip, thereby preventing damage to the edges of buried N.sup.+ -type regions caused by non-uniform thickness of oxides on buried regions during self-aligned MOS etching and resolving the problem of non-uniform oxides on buried N.sup.+ -type regions.
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: March 9, 1999
    Assignee: Winbond Electronics Corp.
    Inventor: Lin-Song Wang
  • Patent number: 5861339
    Abstract: A method provides a recessed isolation is provided in a semiconductor substrate by (a) growing a first field oxide, (b) selectively removing portions of the first field oxide to leave recessed areas in the semiconductor substrate, and (c) growing a second field oxide from the recessed areas in a controlled manner, so that the surface of the semiconductor substrate is substantially planar. In one embodiment, nitride spacers are provided to limit lateral encroachment by the second field oxide from encroaching the active areas of the semiconductor substrate.
    Type: Grant
    Filed: October 27, 1995
    Date of Patent: January 19, 1999
    Assignee: Integrated Device Technology, Inc.
    Inventor: Chuen-Der Lien
  • Patent number: 5851901
    Abstract: A semiconductor device manufacturing method of forming an isolation region of a semiconductor device with high planarization is provided. A semiconductor device is formed by forming a mask over a portion of a semiconductor substrate, the mask defining an exposed portion of the substrate. A first oxide region is grown in the exposed portion of the substrate and a second oxide region is formed over the first oxide region to form a composite oxide region. The mask is removed while leaving the composite oxide region. Spacers may be formed on sidewalls of the mask and removed after growing the first oxide region. The composite oxide region may, for example, form a field oxide region.
    Type: Grant
    Filed: April 11, 1997
    Date of Patent: December 22, 1998
    Assignee: Advanced Micro Devices
    Inventors: Mark I. Gardner, Mark C. Gilmer
  • Patent number: 5846596
    Abstract: Methods of forming field oxide isolation regions having sloped edges which facilitate uniform step coverage of subsequently patterned metallization, etc. but do not encroach upon semiconductor active regions, include the steps of patterning a first mask on a face of a semiconductor substrate to define an active region thereunder and then forming a pad insulation layer on the face of the substrate and in abutting relation to edges of the first mask. Oxidation resistant spacers are then formed on the edges of the first mask and on the pad insulation layer so that field oxide isolation regions having sloped edges can be formed by growing the pad insulation layer through oxidation so that it extends away from the edges of the first mask and does not undercut the first mask to form parasitic bird's beak oxide extensions.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: December 8, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-seob Shim, Hun-chul Shin
  • Patent number: 5789306
    Abstract: A field isolation process utilizes two or more isolation formation steps to form active areas on a semiconductor substrate. Each field isolation step forms a portion of the field isolation in a manner which reduces field oxide encroachment, in particular, by forming field oxide islands. The superposition of field isolation configurations define the desired active areas. A presently preferred dual-mask process may be carried out using a single masking stack, or more preferably using a masking stack for each isolation mask. The present isolation process further allows isolation features to be optimized for a variety of isolation requirements on the same integrated circuit.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: August 4, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Ceredig Roberts, Werner Juengling
  • Patent number: 5789305
    Abstract: The present invention provides a method of fabricating a field oxide layer having a reduced bird's beak using a nitride foot 70 and a first field oxide region 80A as a N.sub.2 implant mask. The N.sub.2 implant suppresses oxide growth around the perimeter of the field oxide and reduces the bird's beak. A pad oxide layer 20 and a first nitride layer 30 are formed over a substrate. The first nitride layer is partially etched back forming a residual first nitride layer in the areas where the field oxide will be formed. A polysilicon spacer is formed on the sidewalls of the first nitride layer and over a portion of the residual first nitride layer. The residual first nitride layer 31 is etched using the spacer 60 as an etch mask forming a nitride foot 70. The substrate is thermally oxidized in the field oxide area using the first nitride layer and the foot 60 as an oxidation barrier forming a first field oxide layer 80A having a bird's beak 85.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: August 4, 1998
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Igor V. Peidous
  • Patent number: 5786264
    Abstract: A method of forming an isolation layer of a semiconductor device, comprising the steps of defining a semiconductor substrate with a cell region and a peripheral region; forming a first buffer layer on the peripheral region of the semiconductor substrate; forming a second buffer layer on the cell region of the semiconductor substrate and on the first buffer layer; forming an anti-oxidation layer on the second buffer layer to define an active region; and forming a field insulation layer in the cell and peripheral regions of the substrate by oxidation.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: July 28, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Hyon-Sang Hwang
  • Patent number: 5747376
    Abstract: A method for fabricating an isolation layer of a semiconductor device defines an active region and an isolation region on a semiconductor substrate. An active pattern is formed on the active region of the semiconductor substrate and the active pattern includes a first insulating layer and a first oxidation stop layer formed on the first insulating layer. A first isolation layer is grown over the substrate corresponding to the isolation region and the first isolation layer is selectively etched by using the first oxidation stop layer as a mask. A sidewall spacer is formed adjacent to the active pattern including a remaining portion of the first isolation layer, and the sidewall spacer includes a second insulating layer and a second oxidation stop layer formed on the second insulating layer. A second isolation layer is grown over the substrate.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: May 5, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Sang-Don Lee
  • Patent number: 5739063
    Abstract: Field oxide regions are formed in a dry oxygen environment containing controlled amounts of HCl at elevated temperatures to reduce edge defects of narrow source/drain regions.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 14, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yowjuang W. Liu, Yu Sun
  • Patent number: 5728622
    Abstract: A process for forming a narrow field oxide layer with a greater thickness. A silicon substrate is provided on which a layer of pad oxide and a layer of nitride are formed. Then, at least a wide area and a narrow area are defined on the silicon substrate through openings on the nitride layer. A thermal oxidation process is performed so as to grow a first oxide layer on the wide area and a second oxide layer on the narrow area. A polysilicon layer is then deposited over the entire surface. After that, chemical-mechanical polish (CMP) is applied so as to rub away part of the polysilicon layer that is lying above a plane coincident with the topmost surface of the nitride layer, thereby leaving a first polysilicon layer on the first oxide layer and a second polysilicon layer on the second oxide layer. A thermal oxidation process is performed so as to oxidize the first polysilicon layer and the second polysilicon layer, thereby increasing the thickness of the first oxide layer and the second oxide layer.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: March 17, 1998
    Assignee: Winbond Electronics Corporation
    Inventor: Tzu-Chiang Yu
  • Patent number: 5726093
    Abstract: A method for the fabrication of semicondictor devices is disclosed, having a field oxide isolation which is co-planar with the adjacent silicon surface and which introduces lower mechanical stresses in the adjacent silicon than prior methods which seek co-planarity by removal of silicon by anisotropic etching methods. Instead, the excess silicon is removed by oxidation followed by selective oxide removal. A silicon substrate is provided and a multilayer oxidation mask is formed on it's surface consisting of a thin thermal oxide and a thicker film of silicon nitride. the mask is patterned by standard photolithographic methods and the field oxide region is pieced by selective reactive-ion-etching. The silicon is not penetrated in this step as it is in prior art. Instead a layer of silicon oxide it thermally grown to a thickness dependent upon the final field oxide thickness. This oxide is then unidirectionally etched to the silicon interface, leaving side pockets.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: March 10, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventor: Chue-san Yoo
  • Patent number: 5721174
    Abstract: The invention is a process for filling narrow isolation trenches with thermal oxide using a nitride spacer and a second trench etch. The method begins by providing forming a pad oxide layer 20 and a first nitride layer 30 over a substrate. A first opening is formed in the pad oxide layer 20 and first nitride layer 30. The substrate is then etched through the first opening forming a first trench 40 in the substrate. A thin oxide film 50 is then grown over the substrate in the bottom and sidewalls of the first trench 40. Nitride spacers 60 are grown over the sidewalls of the first trench and over the thin oxide layer 40 on the sidewalls of the trench. A portion of the thin oxide film 50 on the bottom of the trench is etched. The substrate in the bottom of the first trench is etched forming a second trench 70. The etch exposes portions of the substrate on the bottom of the deeper second trench.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: February 24, 1998
    Assignee: Chartered Semiconductor Manufacturing Pte Ltd
    Inventor: Igor V. Peidous
  • Patent number: 5719086
    Abstract: A method for isolating the elements of semiconductor devices, in which bird's beak can be restrained by accumulating nitrogen atoms between a pad oxide film and a silicon substrate and the etch depth of a silicon substrate can be controlled by use of wet etch to remove the oxide which is grown on the silicon substrate at a low temperature after formation of nitride spacer, thereby reproducing good profiles of the field oxide film.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: February 17, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Young Bog Kim, Sung Ku Kwon, Byung Jin Cho, Jong Choul Kim
  • Patent number: 5714414
    Abstract: A semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate includes providing a semiconductor substrate having field and active area regions; forming masking material over the active area region and leaving the field region exposed, the masking material comprising first, second and third layers, and having a sidewall; exposing the semiconductor substrate to first oxidation conditions effective to form field isolation oxide of a first thickness over the exposed field region; forming an etch stop material layer over the sidewall; removing at least a portion of the third layer selectively relative to the etch stop material layer; and subjecting the semiconductor substrate to second oxidation conditions effective to grow the field isolation oxide to a second thickness on the exposed field region of the semiconductor substrate.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: February 3, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Roger R. Lee, Fernando Gonzalez
  • Patent number: 5700733
    Abstract: A semiconductor processing method of forming field oxide regions on a semiconductor substrate includes, i) providing an oxidation resistant mask over a layer of oxide over a desired active area region on a semiconductor substrate, the mask having a central region and opposed sidewall edges, the oxide layer being thinner in the central region than at the sidewall edges; and ii) oxidizing portions of the substrate unmasked by the mask to form field oxide regions on the substrate. The oxidation resistant mask can be provided by depositing and patterning a nitride layer atop a pad oxide layer. Substrate area not covered the mask is oxidized to produce an oxide layer outside of the mask which is thicker than the pad oxide layer. A thin layer of nitride can then be deposited, and anisotropically etched to produce masking spacers which cover the thicker oxide adjacent the original mask. Mask lifting during subsequent oxidation is restricted, thus minimizing bird's beak encroachment and substrate defects.
    Type: Grant
    Filed: June 27, 1995
    Date of Patent: December 23, 1997
    Assignee: Micron Technology, Inc.
    Inventor: Monte Manning
  • Patent number: 5641705
    Abstract: In a device isolation method for a semiconductor device, after a pad oxide layer and a nitride layer are formed on a semiconductor substrate, the nitride layer located above the device isolation region is removed. An undercut is formed under the nitride by partially etching the pad oxide layer. After a first oxide layer is formed on the exposed substrate and a polysilicon spacer is formed on the sidewalls of the nitride layer, a void is formed in the oxide layer under the nitride layer which is formed on the active region by oxidizing the resultant structure in which the polysilicon spacer is formed at a temperature above 950.degree. C. Thus, good cell definition and stable device isolation can be realized, while solving the typical problem of conventional LOCOS methods by forming the void intentionally in the pad oxide layer thickened by bird's beak punch through.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 24, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-ho Ahn, Seong-joon Ahn, Yu-gyun Shin, Yun-gi Kim
  • Patent number: 5637528
    Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming a mask layer of a desired pattern on a silicon substrate surface or on an SiO.sub.2 strain absorbing layer formed on the silicon substrate surface; (b) selectively oxidizing the silicon substrate in a dry oxygen atmosphere by using the mask layer as an oxidation mask; and (c) selectively oxidizing the silicon substrate in an atmosphere of dry oxygen mixed with gas containing halogen element, wherein a field oxide film having a thickness of 100 nm or more is formed. The first and second oxidizing steps (b) and (c) are preferably performed at temperatures between 950.degree. C. and 1200.degree. C. A field oxide film with a short bird's beak can be formed while maintaining a relatively high oxidation speed and preventing generation of a white ribbon.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: June 10, 1997
    Assignee: Fujitsu Limited
    Inventors: Masaaki Higashitani, Kenichi Hikazutani
  • Patent number: 5627099
    Abstract: In a method of manufacturing a semiconductor device, after forming a poly silicon film 54 on a surface of a silicon substrate 51, a silicon nitride film 55 is formed in accordance with a desired pattern and a local oxidation process is carried out to form a field oxide film 56 having a large thickness. Then, after removing the silicon nitride film 55, the poly silicon film 54 is fully converted in to a silicon oxide film 58 and then the thus converted silicon oxide film is removed by wet etching to expose a clean surface of the silicon substrate 51. The poly silicon film does not constitute an oxygen source, so that during the local oxidation, a lateral diffusion of oxygen is prevented and a generation of bird's beak can be suppressed. Further, the poly silicon film serves as a buffer, no stress remains in the surface of the silicon substrate.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: May 6, 1997
    Assignee: LSI Logic Japan Semiconductor, Inc.
    Inventor: Yoshitaka Sasaki