Abstract: A method (70) of forming sensor packages (20) entails providing a sensor wafer (74) having sensors (30) formed on a side (26) positioned within areas (34) delineated by bonding perimeters (36), and providing a controller wafer (82) having control circuitry (42) at one side (38) and bonding perimeters (46) on an opposing side (40). The bonding perimeters (46) of the controller wafer (82) are bonded to corresponding bonding perimeters (36) of the sensor wafer (74) to form a stacked wafer structure (48) in which the control circuitry (42) faces outwardly. The controller wafer (82) is sawn to reveal bond pads (32) on the sensor wafer (74) which are wire bonded to corresponding bond pads (44) formed on the same side (38) of the wafer (82) as the control circuitry (42). The structure (48) is encapsulated in packaging material (62) and is singulated to produce the sensor packages (20).

Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Abstract: The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.

Abstract: A method for manufacturing a semiconductor device is provided, the method comprising: fabricating a semiconductor element on a semiconductor substrate; joining a surface of the semiconductor substrate to a support member, the surface being on a side where the semiconductor element is fabricated; and polishing a surface on an opposite side of the surface of the semiconductor substrate where the semiconductor element is fabricated and reducing a thickness of the semiconductor substrate, in a state where the semiconductor substrate and the support member are joined.

Abstract: To provide a resource-saving photoelectric conversion device with excellent photoelectric conversion characteristics. Thin part of a single crystal semiconductor substrate, typically a single crystal silicon substrate, is detached to structure a photoelectric conversion device using a thin single crystal semiconductor layer, which is the detached thin part of the single crystal semiconductor substrate. The thin part of the single crystal semiconductor substrate is detached by a method in which a substrate is irradiated with ions accelerated by voltage, or a method in which a substrate is irradiated with a laser beam which makes multiphoton absorption occur. A so-called tandem-type photoelectric conversion device is obtained by stacking a unit cell including a non-single-crystal semiconductor layer over the detached thin part of the single crystal semiconductor substrate.

Abstract: A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallization layer is formed on the second surface of the semiconductor substrate. The metallization layer has a thickness which is greater than the device thickness.

Abstract: A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.

Abstract: A single crystal silicon layer is formed on a principal surface of a first wafer by epitaxial growth. A silicon oxide layer is formed on the single crystal silicon layer. Next, a defect layer is formed inside the single crystal silicon layer by ion implantation, and then, the second wafer is bonded to the silicon oxide layer on the first wafer. After that, an SOI wafer including the silicon oxide layer formed on the second wafer and the single crystal silicon layer formed on the silicon oxide layer is formed by separating the first wafer including the single crystal silicon layer from the second wafer including the single crystal silicon layer in the defect layer. Then, a photodiode is formed in the single crystal silicon layer. An interconnect layer is formed on a surface of the single crystal silicon layer which is opposite to the silicon oxide layer.

Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.

Abstract: The present invention relates to a heat dissipation substrate, which is a composite substrate composed of two layers, and which is characterized in that a surface layer (first layer) (1) is configured of single crystal silicon and a handle substrate (second layer) (2) is configured of a material that has a higher thermal conductivity than the first layer. A heat dissipation substrate of the present invention has high heat dissipation properties.

Abstract: A method for handling and supporting a device wafer during a wafer thinning process and the resulting device are provided. Embodiments include forming a plurality of solder bumps on a first surface of a substrate having a first and a second surface; removing a portion from a periphery of the first surface of the substrate; forming a temporary bonding material on a first carrier; bonding the first surface of the substrate with the temporary bonding material of the first carrier; affixing the second surface of the substrate to a second carrier; and removing the temporary bonding material.

Abstract: A support disk fixing apparatus which includes an upper surface to which a wafer is bonded, a lower surface, a cylindrical side surface between the upper surface and the lower surface, and a chamfered portion between the upper surface and the side surface, includes a base upon which the support disk is placed; and a fixture that is provided on the base, and that has a first surface that abuts against the side surface of the support disk and covers the side surface of the support disk, and a second surface that abuts against the chamfered portion of the support disk and covers the chamfered portion of the support disk.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: providing a first wafer having a first active surface and a first rear surface opposite to the first active surface, the first wafer comprising a first circuit formed therein; providing a second wafer having a second active surface and a second rear surface opposite to the second active surface, the second wafer comprising a second circuit formed therein; bonding the first active surface of the first wafer with the second active surface of the second wafer so as to electrically connecting the first circuit and the second circuit; thinning the second wafer from the second rear surface; and forming at least a conductive through via in the second wafer, wherein the conductive through via is electrically connected to the first circuit through the second circuit.

Abstract: A wafer processing method including a fixing step of providing a wafer on a protective member so that a device area of the wafer faces an unevenness absorbing member provided in a recess of the protective member and providing an adhesive outside the device area to thereby fix the protective member and the wafer, a grinding step of holding the protective member on a holding table in the condition where the back side of the wafer is exposed and next grinding the back side of the wafer by using a grinding unit to thereby reduce the thickness of the wafer to a predetermined thickness, and a removing step of removing the protective member from the wafer. The adhesive is locally provided outside of the device area, so that the protective member can be easily removed from the wafer without leaving the adhesive on the front side of each device.

Abstract: Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force.

Abstract: According to an embodiment of the present disclosure, a substrate inverting device for inverting front and rear surfaces of a substrate is provided. The substrate includes a first holding unit configured to hold one surface of the substrate and a second holding unit disposed to face the first holding unit and configured to hold one surface of the substrate. Further, the substrate includes a moving mechanism configured to relatively move at least one of the first holding unit and the second holding unit to approach each other and stay spaced apart from each other, and a transfer mechanism configured to hold the one surface of the substrate. In this case, a support of the substrate in the first holding unit, the second holding unit and the transfer mechanism is performed by a Bernoulli chuck.

Abstract: A semiconductor device fabricating method includes forming device chip regions and a monitor chip region for processing management, on a substrate surface layer on one main surface side of a semiconductor substrate wafer, each device chip region having an active region and an edge region; after forming metal films on front surface of the device chip regions and the monitor chip region by vapor deposition and photolithography, forming protective films on the front surfaces of the device chip regions and monitor chip region; and grinding and polishing another main surface side of the semiconductor substrate wafer to thin the semiconductor substrate wafer. A difference between an area of one chip occupied by the protective film of the monitor chip region and an area of one chip occupied by the protective film of the device chip region is 20% or less.

Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.

Abstract: A wafer processing method, by which a device wafer may be aligned and bonded to a carrier wafer to perform a back grinding process for the device wafer and may be separated from the carrier wafer after performing the back grinding process, and a method of manufacturing a semiconductor device by using the wafer processing method are provided. The wafer processing method includes: disposing a first magnetic material on a front side of a wafer and disposing a second magnetic material on a carrier wafer, wherein a surface of the first magnetic material and a surface of the second magnetic material, which face each other, have opposite polarities; aligning and bonding the wafer to the carrier wafer by magnetic attraction between the first magnetic material and the second magnetic material; grinding a back side of the wafer to make the wafer thin; and separating the wafer from the carrier wafer.

Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.

Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.

Abstract: A method for manufacturing a bonded wafer includes: an ion implantation step of using a batch type ion implanter; a bonding step of bonding an ion implanted surface of a bond wafer to a surface of a base wafer directly or through an insulator film; and a delamination step of delaminating the bond wafer at an ion implanted layer, thereby manufacturing a bonded wafer having a thin film on the base wafer, wherein the ion implantation into the bond wafer carried out at the ion implantation step is divided into a plurality of processes, the bond wafer is rotated on its own axis a predetermined rotation angle after each ion implantation, and the next ion implantation is carried out at an arrangement position obtained by the rotation.

Abstract: A composite wafer 10 includes a supporting substrate 12 and a semiconductor substrate 14 which are bonded to each other by direct bonding. The supporting substrate 12 is a translucent alumina substrate with an alumina purity of 99% or more. The linear transmittance of the supporting substrate 12 at the visible light range is 40% or less. Furthermore, the total light transmittance from the front at a wavelength of 200 to 250 nm of the supporting substrate 12 is 60% or more. The average crystal grain size of the supporting substrate 12 is 10 to 35 ?m. The semiconductor substrate 14 is a single crystal silicon substrate. Such a composite wafer 10 has insulation performance and thermal conduction comparable to those of a SOS wafer, can be manufactured at low cost, and can be easily made to have a large diameter.

Abstract: A deformable focal plane array (DFPA) for imaging systems is disclosed. In one embodiment, the DFPA includes a detection circuitry on one side. For example, the thickness of the DFPA is in a range of about 5 to 40 microns. In one exemplary embodiment, the DFPA when warped to a desired shape provides a substantially wider field of view (FOV) than a flat focal plane array (FPA).

Abstract: A manufacturing method of a semiconductor device according to embodiments includes forming a photodiode layer, which is an active region including a photodiode, on a main surface of a first substrate, forming a wiring layer, which includes a wire and a dielectric layer covering the wire, on the photodiode layer, and forming a dielectric film on the wiring layer. The manufacturing method of the semiconductor device according to the embodiments further includes bonding a second substrate to the dielectric film of the first substrate so that a crystal orientation of the photodiode layer matches a crystal orientation of the second substrate.

Abstract: Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.

Abstract: According to one embodiment, a first adhesive layer is formed on one major surface of a first substrate. The first substrate and a second substrate are adhered using a second adhesive layer that has thermosetting properties and covers the first adhesive layer, wherein a bonding strength between the second substrate is greater than a bonding strength between the second substrate and the first adhesive layer. The other major surface of the first substrate is polished, and the first substrate is thinned. A physical force is then applied to peripheral parts of the second adhesive layer, and a circular notched part is formed along the outer perimeter of the second adhesive layer to separate the first substrate and the second substrate at the interface between the first adhesive layer and the second adhesive layer.

Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive, and a first isolation coating is disposed between the first adhesive and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.

Abstract: A method for forming a semiconductor structure. A semiconductor substrate including a plurality of dies mounted thereon is provided. The substrate includes a first portion proximate to the dies and a second portion distal to the dies. In some embodiments, the first portion may include front side metallization. The second portion of the substrate is thinned and a plurality of conductive through substrate vias (TSVs) is formed in the second portion of the substrate after the thinning operation. Prior to thinning, the second portion may not contain metallization. In one embodiment, the substrate may be a silicon interposer. Further back side metallization may be formed to electrically connect the TSVs to other packaging substrates or printed circuit boards.

Abstract: A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate. The method comprises: forming at least one reservoir in at least one reservoir formation layer on the first substrate and/or the second substrate, the reservoir comprised of an amorphous material, at least partial filling of the reservoir/reservoirs with a first educt or a first group of educts, forming or applying a reaction layer which contains a second educt or a second group of educts to the reservoir and/or the reservoir, the first contact surface making contact with the second contact surface for formation of a prebond connection, and forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt or the first group with the second educt or the second group.

Abstract: A plasma etching method is provided for forming a hole using a first processing gas to etch a silicon layer of a substrate to be processed including a silicon oxide film that is formed into a predetermined pattern. The method includes a first depositing step (S11) of depositing a protective film on a surface of the silicon oxide film using a second processing gas containing carbon monoxide gas, a first etching step (S12) of etching the silicon layer using the first processing gas, a second depositing step (S13) of depositing the protective film on a side wall of a hole etched by the first etching step using the second processing gas, and a second etching step (S14) of further etching the silicon layer using the first processing gas. The second depositing step (S13) and the second etching step (S14) are alternately repeated at least two times each.

Abstract: A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.

Abstract: A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment.

Abstract: A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.

Abstract: A method of fabricating an optoelectronic integrated circuit substrate includes defining a photonic device region on a first substrate, the photonic device region having a photonic device formed thereon, forming a trench in the photonic device region on a top surface of the first substrate, the trench having a first depth, filling the trench with a dielectric, bonding a second substrate on the first substrate to cover the trench, and thinning the second substrate to a first thickness.

Abstract: A method for mechanically separating a laminar structure from a first carrier assembly, comprising or consisting of a first carrier, wherein the laminar structure comprises a wafer and a second, stretchable carrier is disclosed. Also disclosed are the use of a particular separating aid for separating a laminar structure and a device for carrying out the method.

Abstract: A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision. This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the HC modified region 73 is formed at a position between the segmented modified region 72 closest to the rear face 21 and the rear face 21, so as to generate a fracture 24 extending along a line to cut from the HC modified region 73 to the rear face 21.

Abstract: There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.

Abstract: It is an object to provide a method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even when a single crystal semiconductor substrate in which crystal defects exist is used. Such an SOI substrate can be manufactured through the steps of forming a single crystal semiconductor layer which has an extremely small number of defects over a single crystal semiconductor substrate by an epitaxial growth method; forming an oxide film on the single crystal semiconductor substrate by thermal oxidation treatment; introducing ions into the single crystal semiconductor substrate through the oxide film; bonding the single crystal semiconductor substrate into which the ions are introduced and a semiconductor substrate to each other; causing separation by heat treatment; and performing planarization treatment on the single crystal semiconductor layer provided over the semiconductor substrate.

Abstract: Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.

Abstract: A method is disclosed that includes the steps outlined below. A first oxide layer is formed to divide a first semiconductor substrate into a first part and a second part. A second oxide layer is formed on the first part of the first semiconductor substrate. The first oxide layer is bonded to a third oxide layer of a second semiconductor substrate. The second part of first semiconductor substrate and the first oxide layer are removed to expose the first part of the first semiconductor substrate.

Abstract: Embodiments of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a first polymer material and a second conductive material embedded in a second polymer material. The first conductive material is bonded to the second conductive material and the first polymer material is bonded to the second polymer material. The semiconductor device also includes at least one through silicon via (TSV) extending from a bottom surface of the first semiconductor wafer to a metallization structure of the first semiconductor wafer. The semiconductor device structure also includes an interconnect structure formed over the bottom surface of the first semiconductor wafer, and the interconnect structure is electrically connected to the metallization structure via the TSV.

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a first transistor formed in a front-side of the first semiconductor wafer, and the second semiconductor wafer includes a second transistor formed in a front-side of the second semiconductor wafer. A backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device structure further includes an interconnect structure formed over the front-side of the second semiconductor wafer, and at least one first through substrate via (TSV) directly contacts a conductive feature of the first semiconductor wafer and the interconnect structure.

Abstract: An SOI substrate including a semiconductor layer whose thickness is even is provided. According to a method for manufacturing the SOI substrate, the semiconductor layer is formed over a base substrate. In the method, a first surface of a semiconductor substrate is polished to be planarized; a second surface of the semiconductor substrate which is opposite to the first surface is irradiated with ions, so that an embrittled region is formed in the semiconductor substrate; the second surface is attached to the base substrate, so that the semiconductor substrate is attached to the base substrate; and separation in the embrittled region is performed. The value of 3? (? denotes a standard deviation of thickness of the semiconductor layer) is less than or equal to 1.5 nm.

Abstract: A light emitting device includes a light emitting element that emits light having a wavelength of 250 nm to 500 nm and a fluorescent layer that is disposed on the light emitting element. The fluorescent layer includes a phosphor having a composition expressed by the equation, ((M1?x1Eux1)3?ySi13?zAl3+zO2+uN21?w), and an average particle diameter of 12 ?m or more, wherein in the equation, M is an element that is selected from IA group elements, IIA group elements, IIIA group elements, IIIB group elements except Al, rare-earth elements, and IVB group elements, and x1, y, z, u, and w satisfy each of the inequalities simultaneously, that is to say each of the following inequalities is satisfied by the choice of values of the identified paramaters within the noted ranges of 0<x1<1, ?0.1<y<0.3, ?3<z?1, ?3<u?w?1.5, 2<u, w<21.

Abstract: A method of producing a composite structure comprises a step of producing a first layer of microcomponents on one face of a first substrate, the first substrate being held flush against a holding surface of a first support during production of the microcomponents, and a step of bonding the face of the first substrate comprising the layer of microcomponents onto a second substrate. During the bonding step, the first substrate is held flush against a second support, the holding surface of which has a flatness that is less than or equal to that of the first support used during production of the first layer of microcomponents.

Abstract: The invention relates to a method for producing chip stacks with the following method sequence: applying an especially dielectric and/or photostructurable base layer to one carrier side of a carrier which on its carrier side is provided with an adhesively acting adhesion zone and a less adhesively acting support zone, the base layer being applied largely over the entire surface at least to the support zone, building up the chip stacks on the base layer, potting of the chip stacks, detaching the carrier from the base layer. Moreover the invention relates to a carrier for executing this method.

Abstract: A method of bonding by molecular bonding between at least one lower wafer and an upper wafer comprises positioning the upper wafer on the lower wafer. In accordance with the invention, a contact force is applied to a peripheral side of at least one of the two wafers in order to initiate a bonding wave between the two wafers.

Abstract: Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.

Abstract: A method for forming a semiconductor device includes providing a substrate having a first major surface and a second major surface, removing a first portion of the substrate to form a cavity at the first major surface of the substrate, bonding the first major surface of the substrate to a carrier substrate after forming the cavity, and reducing a thickness of the substrate. The method further includes forming a first accelerometer device at the second major surface such that at least a portion of the first accelerometer device is over the cavity and forming a second accelerometer device at the second major surface such that the second accelerometer device is not disposed over the cavity.