Abstract: A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a first dielectric layer on the bottom electrode, forming a sacrificial layer on the first dielectric layer, forming an isolation layer on the sacrificial layer, and forming a second dielectric layer on the isolation layer. The method further includes forming a via overlying the bottom electrode, the via extending to the sacrificial layer, etching through the sacrificial layer to the first dielectric layer to form a pore defined extending through the sacrificial layer and the first dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.

Abstract: Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.

Abstract: A semiconductor device may include a composite represented by Formula 1 below as an active layer. x(Ga2O3)·y(In2O3)·z(ZnO)??Formula 1 wherein, about 0.75?x/z? about 3.15, and about 0.55?y/z? about 1.70. Switching characteristics of displays and driving characteristics of driving transistors may be improved by adjusting the amounts of a gallium (Ga) oxide and an indium (In) oxide mixed with a zinc (Zn) oxide and improving optical sensitivity.

Abstract: A method for etching quartz is provided herein. In one embodiment, a method of etching quartz includes providing a filmstack in an etching chamber, the filmstack having a quartz layer partially exposed through a patterned layer, providing at least one fluorocarbon process gas to a processing chamber, biasing a quartz layer disposed on a substrate support in the processing chamber with a plurality of power pulses less than 600 Watts and etching the quartz layer through a patterned mask. The method for etching quartz described herein is particularly suitable for fabricating photomasks having etched quartz portions.

Abstract: A method, apparatus and material produced thereby in an amorphous or crystalline form having multiple elements with a uniform molecular distribution of elements at the molecular level.

Abstract: A memory cell as described herein includes a conductive contact and a memory element comprising programmable resistance memory material overlying the conductive contact. An insulator element extends from the conductive contact into the memory element, the insulator element having proximal and distal ends and an inside surface defining an interior. The proximal end is adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end. The memory element is within the interior extending downwardly from the distal end to contact a top surface of the bottom electrode at a first contact surface. A top electrode can be separated from the distal end of the insulator element by the memory element and contact the memory element at a second contact surface having a surface area greater than that of the first contact surface.

Abstract: A plasma doping method and a plasma doping apparatus, having a superior in-plane uniformity of an amorphous layer formed on a sample surface, are provided. In the plasma doping method by which plasma is generated within a vacuum chamber, and impurity ions contained in the plasma are caused to collide with the surface of the sample so as to quality-change the surface of the sample into an amorphous state thereof, a plasma irradiation time is adjusted in order to improve an in-plane uniformity. If the plasma irradiation time becomes excessively short, then a fluctuation of the plasma is transferred to depths of an amorphous layer formed on a silicon substrate, so that the in-plane uniformity is deteriorated. On the other hand, if the irradiation time becomes excessively long, then an effect for sputtering the surface of the silicon substrate by using the plasma becomes dominant, then the in-plane uniformity is deteriorated.

Abstract: A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first and second side walls near the respective top sides. A bridge of memory material crosses the insulating wall, and defines an inter-electrode path between the first and second electrodes across the insulating wall. An array of such memory cells is provided. The bridges of memory material have sub-lithographic dimensions.

Abstract: Semiconductor wafer of monocrystalline silicon contain fluorine, the fluorine concentration being 1·1010 to 1·1016 atoms/cm3, and is free of agglomerated intrinsic point defects whose diameter is greater than or equal to a critical diameter. The semiconductor wafers are produced by providing a melt of silicon which is doped with fluorine, and crystallizing the melt to form a single crystal which contains fluorine within the range of 1·1010 to 1·1016 atoms/cm3, at a growth rate at which agglomerated intrinsic point defects having a critical diameter or larger would arise if fluorine were not present or present in too small an amount, and separating semiconductor wafers from the single crystal.

Abstract: A thin film transistor includes a semiconductor layer formed on a polycrystalline silicon layer crystallized by a super grain silicon (SGS) crystallization method. The thin film transistor is patterned such that the semiconductor layer does not include a seed or a grain boundary created when forming the semiconductor layer on the polycrystalline silicon layer.

Abstract: A phase-change memory element includes a perovskite layer formed by a material having a perovskite structure, and a phase-change recording material layer which is formed on the perovskite layer, and changes the phase to a crystal state or amorphous state when supplied with an electric current via the perovskite layer.

Abstract: A phase change memory apparatus is provided that includes a first electrode of a bar type having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.

Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer

Abstract: Embodiments of the present invention provide a method for forming an emitter region in a crystalline silicon substrate and passivating the surface thereof by depositing a doped amorphous silicon layer onto the crystalline silicon substrate and thermally annealing the crystalline silicon substrate while oxidizing the surface thereof. In one embodiment, the deposited film is completely converted to oxide. In another embodiment, the doped amorphous silicon layer deposited onto the crystalline silicon substrate is converted into crystalline silicon having the same grain structure and crystal orientation as the underlying crystalline silicon substrate upon which the amorphous silicon was initially deposited during emitter formation. In one embodiment, at least a portion of the converted crystalline silicon is further converted into silicon dioxide during the emitter surface passivation.

Abstract: Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.

Abstract: Exact alignment of a recrystallized region, which is to be formed in an amorphous or polycrystalline film, is facilitated. An alignment mark is formed, which is usable in a step of forming an electronic device, such as a thin-film transistor, in the recrystallized region. In addition, in a step of obtaining a large-grain-sized crystal-phase semiconductor from a semiconductor film, a mark structure that is usable as an alignment mark in a subsequent step is formed on the semiconductor film in the same exposure step. Thus, the invention includes a light intensity modulation structure that modulates light and forms a light intensity distribution for crystallization, and a mark forming structure that modulates light and forms a light intensity distribution including a pattern with a predetermined shape, and also forms a mark indicative of a predetermined position on a crystallized region.

Abstract: A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.

Abstract: A thin film device includes: a substrate; an electric field shielding plate formed above the substrate, the electric filed shielding plate having a conductive material; and a thin film element formed on the electric field shielding plate, the, the electric field shielding plate being connected to a potential of any electrode of the thin film element or a ground potential.

Abstract: As an electrode area of a plasma CVD apparatus is enlarged, influence of the surface standing wave remarkably appears, and there is a problem in that in-plane uniformity of quality and a thickness of a thin film formed over a glass substrate is degraded. Two or more high-frequency electric powers with different frequencies are supplied to an electrode for producing glow discharge plasma in a reaction chamber. With glow discharge plasma produced by supplying the high-frequency electric powers with different frequencies, a semiconductor thin film or an insulating thin film is formed. High-frequency electric powers with different frequencies (different wavelengths), which are superimposed on each other, are applied to an electrode in a plasma CVD apparatus, so that increase in plasma density and uniformity for preventing effect of surface standing wave of plasma are attained.

Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

Abstract: A semiconductor memory device includes: a lower electrode including a plurality of projections formed on a top surface thereof; an oxide film covering the top surface and made of an oxide of a same metal as a metal contained in the lower electrode; and a resistance variable film provided on the oxide film and being in contact with the oxide film, the projections being buried in the oxide film, and a lower layer portion of the resistance variable film having an oxygen concentration lower than an oxygen concentration of a portion other than the lower layer portion of the resistance variable film.

Abstract: A phase change random access memory for actively removing residual heat and a method of manufacturing the same are presented. The phase change random access memory includes a semiconductor substrate, a phase change pattern, a heating electrode and a cooling electrode. The phase change pattern is on the semiconductor substrate. The heating electrode is electrically coupled to the phase change pattern for heating the phase change pattern. The cooling electrode is electrically coupled to the phase change pattern for removing residual heat from the phase change pattern.

Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas greater than about 100:1, wherein a volumetric flow ratio of the argon gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 5 percent and about 40 percent, and maintaining a process pressure of the gas mixture within the processing chamber at greater than about 3 Torr while depositing a microcrystalline silicon layer on the substrate.

Abstract: A memory includes multiple layers of deposited memory material. An etch is performed on at least one layer of deposited memory material prior to the deposition of a subsequent layer of memory material.

Abstract: Provided is a novel method for manufacturing a field effect transistor. Prior to forming an amorphous oxide layer on a substrate, ultraviolet rays are irradiated onto the substrate surface in an ozone atmosphere, plasma is irradiated onto the substrate surface, or the substrate surface is cleaned by a chemical solution containing hydrogen peroxide.

Abstract: An integrated circuit comprises a doped semiconductor portion including an amorphous portion and a contact structure comprising a conductive material. The contact structure is in contact with the amorphous portion. According to another embodiment, an integrated circuit comprises a doped semiconductor portion including a region having a non-stoichiometric composition and a contact structure comprising a conductive material. The contact structure is in contact with the region having a non-stoichiometric composition.

Abstract: An interconnecting structure production method includes providing a substrate, forming a semiconductor layer on the substrate, forming a doped semiconductor layer on the semiconductor layer, the doped semiconductor layer containing a dopant, forming an oxide layer in a surface of the doped semiconductor layer by heating the surface of the doped semiconductor layer in atmosphere of an oxidizing gas with a water molecule contained therein, forming an alloy layer on the oxide layer, and forming an interconnecting layer on the alloy layer.

Abstract: By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature at 300° C. or less, setting the sputtering power from 1 kW to 9 kW, and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from ?1 ×1010cm2 to 1×1010 dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.3 ppm, preferably equal to or less than 0.1 ppm, and having a low electrical resistivity (equal to or less than 40 ??•cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased.

Abstract: Chemical vapor deposition methods use trisilane and a halogen-containing etchant source (such as chlorine) to selectively deposit Si-containing films over selected regions of mixed substrates. Dopant sources may be intermixed with the trisilane and the etchant source to selectively deposit doped Si-containing films. The selective deposition methods are useful in a variety of applications, such as semiconductor manufacturing.

Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (a-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the a-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the a-Si layer, wherein interface defects existing between the a-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.

Abstract: Programmable via devices and methods for the fabrication thereof are provided.

Abstract: Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a plurality of amorphous silicon features, and re-growing the amorphous silicon features to define a thin active silicon layer consisting of regrown silicon features. The amorphous silicon features may be regrown such that a number have a first crystal orientation and another number have a different second crystal orientation.

Abstract: A method of fabricating a semiconductor device includes sequentially forming a first pattern and a second pattern on a substrate, the second pattern being a non-single-crystalline semiconductor stacked on the first pattern, wherein a portion of the substrate is exposed adjacent to the first and second patterns, forming a non-single-crystalline semiconductor layer on the substrate, the semiconductor layer contacting the second pattern and the exposed portion of the substrate, and, using the substrate as a seed layer, changing the crystalline state of the semiconductor layer to be single-crystalline and changing the crystalline state of the second pattern to be single-crystalline.

Abstract: A method for fabricating a polysilicon liquid crystal display device includes: forming a first amorphous silicon layer on a substrate; forming a photoresist pattern on the first amorphous silicon layer; forming a second amorphous silicon layer over the photoresist pattern and the first amorphous silicon layer; defining a channel region on the first amorphous silicon layer; crystallizing the first and second silicon layers; forming an active layer by patterning the crystallized silicon layers; forming a first insulating layer on the active layer; forming a gate electrode on the first insulating layer; forming source and drain electrodes electrically connected to the active layer; and forming a pixel electrode electrically connected to the drain electrode.

Abstract: A phase change memory device includes a silicon substrate having a phase change cell region. A plurality of phase change cell are formed in the phase change region of the silicon substrate. A contact comprising a first contact and a second contact is formed on each of the phase change cells. A plurality of bit lines are electrically connected to the contacts. A contact plug is formed on the silicon substrate in a region outside of the phase change cell region, and a word line is formed over the silicon substrate and is connected to the contact plug.

Abstract: The present invention relates to an array substrate for a flat display device and a method for fabricating the same, in which a number of masks is reduced for reducing a cost and improving a device performance.

Abstract: Method of fabricating a microelectronic structure includes preparing a first structure having a first material different from silicon on a surface thereof and forming at least one covering layer of a second material by IBS (ion beam sputtering) and having a thickness of less than one micron, where the at least one cover layer has a free surface and molecular bonding the free surface to one face of a second structure where the at least one covering layer constitutes a bonding layer for the first and second structures.

Abstract: A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon.

Abstract: A semiconductor substrate is covered by a dielectric region. The dielectric region accommodates a memory element and a selection element forming a phase change memory cell. The memory element is formed by a resistive element and by a storage region of a phase change material extending on and in contact with the resistive element at a contact area. The selection element is formed by a switching region of chalcogenic material embedded in the dielectric region and belonging to a stack extending on the resistive element and including also the storage region. A mold region extends on top of the resistive element and delimits a trench having a substantially elongated shape. At least one portion of the storage region extends in the trench and defines a phase change memory portion over the contact area.

Abstract: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film comprising a plurality of insulating films provided on the charge storage layer and comprising a nitride film as an uppermost layer, and a single-layer control gate electrode provided on the second insulating film and comprising metal silicide.

Abstract: Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell.

Abstract: A memory device includes a memory array comprising a plurality of storage locations disposed above a plurality of generally parallel lines, where each storage location comprises a programmable material disposed on a sidewall of a conductive element.

Abstract: A phase change memory device having a reduced contact area and a method for manufacturing the same is presented. The phase change random access memory device includes a bottom electrode contact pattern layer, and at least one phase change pattern layer formed on a sidewall of the bottom electrode contact pattern layer. The contact areas are minimized by being between the narrow width of the bottom electrode contact pattern layer, i.e., at the sidewall, and the phase change pattern layers. As a result the minimized contact area is proportional to the thickness of the bottom electrode contact pattern layer.

Abstract: A method of manufacturing a phase change memory (PCM) includes forming a pinch plate layer transversely to a PCM layer that is insulated from the pinch plate layer by a dielectric layer. Biasing the pinch plate layer causes a depletion region to form in the PCM layer. During a read of the PCM in a reset or partial reset state the depletion region increases the resistance of the PCM layer significantly.

Abstract: A method of degassing a thin layer and a method of manufacturing a silicon thin film includes applying microwaves to a silicon thin film deposited on a substrate to induce a resonance of impurities of H2, Ar, He, Xe, O2, and the like present in the silicon thin film so as to remove the impurities from the silicon thin film. A wavelength of the microwaves is equal to a natural frequency of an element of an object to be removed. According to a resonance of impurities induced by microwaves, the impurities can be very effectively removed from the silicon thin film so as to obtain a high quality silicon thin film. In particular, the microwaves are very suitable to be used in the manufacture of silicon thin films at low temperature.

Abstract: To provide a semiconductor device with high performance and low cost and a manufacturing method thereof. A first region including a separated (cleavage) single-crystal semiconductor layer and a second region including a non-single-crystal semiconductor layer are provided over a substrate. It is preferable that laser beam irradiation be performed to the separated (cleavage) single-crystal semiconductor layer in an inert atmosphere, and laser beam irradiation be performed to the non-single-crystal semiconductor layer in an air atmosphere at least once.

Abstract: A method of fabricating a nonvolatile memory device includes; forming a first sacrificial layer pattern including a first open area that extends in a first direction on a lower dielectric layer, forming a pre-lower dielectric layer pattern including a recess that extends in the first direction using the first sacrificial layer pattern, forming a second sacrificial layer pattern including a second open area that extends in a second direction on the pre-lower dielectric layer pattern and the first sacrificial layer pattern, wherein the second open area intersects the first open area, forming a lower dielectric layer pattern including contact holes spaced apart in the recess using the first sacrificial layer pattern and second sacrificial layer pattern, wherein the contact holes extend to a bottom of the lower dielectric layer pattern, and forming a bottom electrode in the contact hole.

Abstract: A method of manufacturing a nonvolatile memory device including forming on a lower insulating layer a first sacrificial pattern having first openings extending in a first direction, forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern wherein the second openings intersect the first openings, etching the lower insulating layer using the first and second sacrificial patterns to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other, forming a bottom electrode in the contact holes, and forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode.

Abstract: Embodiments of the present invention include an improved method of forming a thin film solar cell device using a plasma processing treatment between two or more deposition steps. Embodiments of the invention also generally provide a method and apparatus for forming the same. The present invention may be used to advantage to form other single junction, tandem junction, or multi-junction solar cell devices.