And Subsequent Doping Of Polycrystalline Semiconductor Patents (Class 438/491)
-
Publication number: 20090166623Abstract: A first interconnection is formed along a groove of a substrate and on a bottom surface of the groove, and has a first thickness. A second interconnection is electrically connected to the first interconnection and has a second thickness larger than the first thickness. An acceleration sensing unit is electrically connected to the second interconnection. A sealing unit has a portion opposed to the substrate with the first interconnection therebetween, and surrounds the second interconnection and the acceleration sensing unit on the substrate. A cap is arranged on the sealing unit to form a cavity on a region of the substrate surrounded by the sealing unit. Thereby, airtightness of the cavity can be ensured and also an electric resistance of the interconnection connected to the acceleration sensing unit can be reduced.Type: ApplicationFiled: June 30, 2008Publication date: July 2, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kimitoshi SATO, Mika OKUMURA, Yasuo YAMAGUCHI, Makio HORIKAWA
-
Publication number: 20090121224Abstract: A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.Type: ApplicationFiled: January 2, 2008Publication date: May 14, 2009Inventor: Young Hoon KIM
-
Patent number: 7521303Abstract: A method of crystallizing an amorphous semiconductor thin film used for a thin film transistor (TFT) is provided. The method includes the steps of: forming first and second crystallization induced metal patterns locally in respective portions of a source region and a drain region of the TFT on an amorphous semiconductor thin film; and crystallizing an amorphous semiconductor via independent two-times heat treatment using the first and second crystallization induced metal patterns. In this case, the independent two-times heat treatment is executed before and after ions of impurities are injected, respectively. In this way, a metal induced lateral crystallization double heat treatment is executed before and after ions of impurities are injected, respectively. As a result, the entire crystallization heat treatment time necessary for crystallizing the amorphous semiconductor thin film can be greatly reduced, and a poly-crystalline TFT having low leakage current can be obtained.Type: GrantFiled: June 7, 2005Date of Patent: April 21, 2009Inventor: Woon Suh Paik
-
Patent number: 7488612Abstract: A method for fabricating a liquid crystal display (LCD) device comprises forming an active pattern and a data line on a substrate, the active pattern including a source, a drain, and a channel regions; a first insulation film on a portion of the substrate; forming a gate electrode in a portion of the active pattern where the first insulation film is formed; a second insulation film on the substrate; forming a plurality of first contact holes exposing a portion of the source and drain regions and a second contact hole exposing a portion of the data line; forming a source electrode from a transparent conductive material connected to a source region within the respective first contact hole and a data line within the second contact hole; and forming a pixel and a drain electrodes from the transparent conductive material connected to a drain region within the respective first contact hole.Type: GrantFiled: October 18, 2007Date of Patent: February 10, 2009Assignee: LG Dsiplay Co., Ltd.Inventors: Joon-Young Yang, Yong-In Park, Sang-Hyun Kim
-
Publication number: 20080311697Abstract: The invention relates to a method for simultaneous recrystallisation and doping of semiconductor layers, in particular for the production of crystalline silicon thin layer solar cells. In this method, in a first step a substrate base layer 1 is produced, in a step subsequent thereto, on the latter an intermediate layer system 2 which has at least one doped partial layer is deposited, in a step subsequent thereto, an absorber layer 3 which is undoped or likewise doped is deposited on the intermediate layer system 2, and in a recrystallisation step, the absorber layer 3 is heated, melted, cooled and tempered. In an advantageous method modification, instead of an undoped capping layer, a capping layer system 4 which has at least one partial layer can also be applied applied on the absorber layer 3.Type: ApplicationFiled: September 14, 2005Publication date: December 18, 2008Applicant: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDInventor: Stefan Reber
-
Publication number: 20080202576Abstract: Photovoltaic modules comprise solar cells having doped domains of opposite polarities along the rear side of the cells. The doped domains can be located within openings through a dielectric passivation layer. In some embodiments, the solar cells are formed form thin silicon foils. Doped domains can be formed by printing inks along the rear surface of the semiconducting sheets. The dopant inks can comprise nanoparticles having the desired dopant.Type: ApplicationFiled: February 15, 2008Publication date: August 28, 2008Inventor: Henry Hieslmair
-
Publication number: 20080153269Abstract: The present invention pertains to a system and method for implementing dummy tiles in forming a memory device. The system and method involves forming at least a portion of a memory core array upon a semiconductor substrate comprising, forming STI structures in the substrate, depositing an oxide layer over the substrate, forming a first polysilicon layer over the oxide layer, doping the first polysilicon layer, forming a second polysilicon layer over the first polysilicon layer, patterning at least one memory core, patterning at least one dummy tile and performing back end processing.Type: ApplicationFiled: December 26, 2006Publication date: June 26, 2008Inventors: Cinti Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming-Sang Kwan, Yu Sun, Jean Yee-Mei Yang
-
Publication number: 20080149939Abstract: Provided are an electronic cooling device and a fabrication method thereof. The method may include forming an insulating layer on a semiconductor substrate, forming first and second silicide layers on the insulating layer, forming separate paired p-type and n-type semiconductors on each of the first and second silicide layers, forming a first interlayer dielectric (ILD) layer on the p-type and n-type semiconductors, exposing top surfaces of the n-type and p-type semiconductors, forming a third silicide layer on one semiconductor on each of the first and second silicide layers, forming a second ILD layer on the third silicide layer, and etching the second and first ILD layers to form contact holes exposing top surfaces of the first and second silicide layers.Type: ApplicationFiled: December 11, 2007Publication date: June 26, 2008Inventor: Chang Hun Han
-
Publication number: 20080105878Abstract: A nonvolatile semiconductor storage device is provided in which memory cells comprising PN junction diodes having satisfactory rectifying characteristics are arranged in three dimensions. The semiconductor storage device includes: a first wire which extends in one direction; a second wire which extends in a direction intersecting the first wire; and a memory cell which is positioned at a portion of intersection of the first wire with the second wire between the first wire and the second wire, the memory cell comprising a storage element and a PN junction diode connected thereto, positioned on a side of the second wire used in selecting the memory cell, and a P-type semiconductor forming the PN junction diode forms a portion of the second wire, wherein a plurality of structures, each structure comprising the first wire, the second wire, and the memory cell is provided three-dimensionally.Type: ApplicationFiled: October 30, 2007Publication date: May 8, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Shinji Ohara
-
Patent number: 7368368Abstract: In one embodiment the present invention is a method of conducting multiple step multiple chamber chemical vapor deposition while avoiding reactant memory in the relevant reaction chambers. The method includes depositing a layer of semiconductor material on a substrate using vapor deposition in a first deposition chamber followed by evacuation of the growth chamber to reduce vapor deposition source gases remaining in the first deposition chamber after the deposition growth and prior to opening the chamber. The substrate is transferred to a second deposition chamber while isolating the first deposition chamber from the second deposition chamber to prevent reactants present in the first chamber from affecting deposition in the second chamber and while maintaining an ambient that minimizes or eliminates growth stop effects. After the transferring step, an additional layer of a different semiconductor material is deposited on the first deposited layer in the second chamber using vapor deposition.Type: GrantFiled: August 18, 2004Date of Patent: May 6, 2008Assignee: Cree, Inc.Inventor: David Todd Emerson
-
Patent number: 7341787Abstract: The invention relates to a process for producing highly doped semiconductor wafers, in which at least two dopants which are electrically active and belong to the same group of the periodic system of the elements are used for the doping. The invention also relates to a semiconductor wafer which is free of dislocations and is doped with at least two electrically active dopants which belong to the same group of the periodic system of the elements.Type: GrantFiled: January 26, 2005Date of Patent: March 11, 2008Assignee: Siltronic AGInventors: Rupert Krautbauer, Erich Gmeilbauer, Robert Vorbuchner, Martin Weber
-
Publication number: 20080014671Abstract: There are provided preflow periods t11, t12 in which group III element materials TMG, TMA and TMI are not supplied from a group III element material container to a reaction region (reactor), while a group V element material PH3 and an Mg dopant material are supplied from a group V element material container and a dopant material container to the reaction region (reactor) after an Mg-undoped group III-V compound semiconductor layer is crystallinically grown and before an Mg-doped group III-V compound semiconductor layer is crystallinically grown. According to the semiconductor manufacturing method, an Mg doping profile can be accurately controlled.Type: ApplicationFiled: July 9, 2007Publication date: January 17, 2008Applicant: SHARP KABUSHIKI KAISHAInventors: Kei Yamamoto, Junichi Nakamura
-
Patent number: 7294535Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A heat treatment is carried out for an amorphous semiconductor thin film, to thereby obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature range of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grain boundaries and crystal grains disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.Type: GrantFiled: July 13, 1999Date of Patent: November 13, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Tamae Takano
-
Patent number: 7232742Abstract: In a method of crystallizing a semiconductor film by introducing a metallic element that promotes crystallization, a gettering thereafter is effectively performed. A material film having a high tensile stress, typically a silicon nitride film, is formed in contact with the semiconductor film or heated after the formation thereof, thereby the metallic element in a crystalline semiconductor film is gettered to the material film having a high tensile stress. Thus, the metallic Interstitial silicon density element is removed or reduced to thereby form a gettered region.Type: GrantFiled: November 27, 2000Date of Patent: June 19, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shinji Maekawa
-
Patent number: 7223649Abstract: Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.Type: GrantFiled: August 18, 2004Date of Patent: May 29, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Chul Oh, Wook-Je Kim, Nak-Jin Son, Se-Myeong Jang, Gyo-Young Jin
-
Patent number: 7115488Abstract: Since sodium contained in glass, or glass itself has low heat resistance; a CPU fabricated using a TFT formed over a glass substrate or the like has not been obtained. In the case of operating a CPU with high-speed, the length of a gate (gate length) of a TFT is required to be shorter. However, since a glass substrate has large deflection, a gate electrode cannot have been etched to have a gate length short enough to be used for a CPU. According to the invention, a conductive film is formed over a crystalline semiconductor film formed over a glass substrate, a mask is formed over the conductive film, and the conductive film is etched by using the mask; thus, a thin film transistor with a gate length of 1.0 ?m or less is formed. In particular, the crystalline semiconductor film is formed by crystallizing an amorphous semiconductor film formed over a glass substrate by laser irradiation.Type: GrantFiled: August 17, 2004Date of Patent: October 3, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Satoru Saito, Saishi Fujikawa
-
Patent number: 7015122Abstract: A method of forming a polysilicon thin film transistor is disclosed in the present invention. The method includes forming a buffer layer on a transparent substrate, forming an amorphous silicon layer on the buffer layer, crystallizing the amorphous silicon layer into a polysilicon layer using a sequential lateral solidification (SLS) method, patterning the polysilicon layer to form a polysilicon active layer, performing a rapid thermal annealing (RTA) process to the polysilicon active layer under a H2 atmosphere, performing a rapid thermal oxidation (RTO) process to form a silicon-oxidized layer on the polysilicon active layer after the RTA process, and forming a metal layer over the transparent substrate to cover the silicon-oxidized layer.Type: GrantFiled: October 30, 2003Date of Patent: March 21, 2006Assignee: LG.Philips LCD Co., Ltd.Inventor: Seok-Woo Lee
-
Patent number: 6949452Abstract: There is provided a method for fabricating an image display device having an active matrix substrate including high-performance transistor circuits operating with high mobility as drive circuits for driving pixel portions which are arranged as a matrix. The portion of a polysilicon film formed in a drive circuit region DAR1 provided on the periphery of the pixel region PAR of the active matrix substrate SUB1 composing the image display device is irradiated and scanned with a pulse modulated laser beam or a pseudo CW laser beam to be reformed into a quasi-strip-like-crystal silicon film having a crystal boundary continuous in the scanning direction so that discrete reformed regions each composed of the quasi-strip-like-crystal silicon film are formed.Type: GrantFiled: June 25, 2003Date of Patent: September 27, 2005Assignee: Hitachi, Ltd.Inventors: Mutsuko Hatano, Shinya Yamaguchi, Takeo Shiba, Mitsuharu Tai, Hajime Akimoto
-
Patent number: 6890827Abstract: To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.Type: GrantFiled: August 27, 1999Date of Patent: May 10, 2005Assignee: Agere Systems Inc.Inventors: Seungmoo Choi, Sailesh Merchant, Pradip K. Roy
-
Patent number: 6881986Abstract: A novel structure for a photodiode is disclosed. It is comprised of a p-type region, which can be a p-substrate or p-well, extending to the surface of a semiconductor substrate. A multiplicity of parallel finger-like n-wells is formed in the p-type region. The fingers are connected to a conductive region at one end.Type: GrantFiled: November 7, 2001Date of Patent: April 19, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Zung Chiou, Kuen-Hsien Lin, Chen Ying Lieh, Shou-Yi Hsu
-
Patent number: 6881653Abstract: A method of manufacturing a CMOS semiconductor device able to reduce the effective thickness of the gate insulating film and able to secure stable performance is provided. The method in one embodiment comprises the steps of: forming a polycrystalline silicon film on a gate insulating film; introducing an n-type impurity into the polycrystalline silicon film in an nMOS formation region before gate processing of the polycrystalline silicon film; performing heat treatment so that the impurity diffuses in the polycrystalline silicon film and is activated; and patterning the polycrystalline silicon to form a gate pattern before introducing an impurity into the polycrystalline silicon film at a pMOS formation region.Type: GrantFiled: December 22, 2003Date of Patent: April 19, 2005Assignee: Fujitsu LimitedInventors: Manabu Kojima, Kenichi Goto, Hiroshi Morioka, Kenichi Okabe
-
Patent number: 6878577Abstract: A method of forming an LDD of a semiconductor device. A substrate having a polysilicon layer thereon is provided, wherein the polysilicon layer comprises a first region and a second region. A patterned photoresist layer is formed on the polysilicon layer for exposing the first region and covering the second region. The photoresist layer covering the second region comprises a middle portion and an edge portion, wherein the middle portion is thicker than the edge portion. Then, an ion implantation process is performed using the photoresist layer as a mask for forming a source/drain in the first region of the polysilicon layer and an LDD in the second region underneath the edge portion of the photoresist layer.Type: GrantFiled: August 14, 2003Date of Patent: April 12, 2005Assignee: Au Optronics CorporationInventor: Ming-Sung Shih
-
Patent number: 6867113Abstract: An in-situ deposition and doping method for polycrystalline silicon layers of semiconductor devices. A first intermediate layer of in-situ doped polycrystalline silicon is grown, and a second additional layer of polycrystalline silicon is grown with a lower doping level than that of the first intermediate layer of polycrystalline silicon. In one preferred method, the second doping level is substantially lower than the first doping level. Additionally, a semiconductor memory device of the type having a gate stack is provided. The memory device includes at least one gate layer of polycrystalline silicon, and the gate layer of polycrystalline silicon is formed from a first intermediate layer of polycrystalline silicon with a first doping level, and an overlaying second additional layer of polycrystalline silicon with a second doping level that is lower than the first doping level. In a preferred embodiment, the second doping level is substantially lower than the first doping level.Type: GrantFiled: November 13, 1998Date of Patent: March 15, 2005Assignee: STMicroelectronics S.r.l.Inventor: Raffaele Zambrano
-
Patent number: 6855991Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.Type: GrantFiled: March 31, 2004Date of Patent: February 15, 2005Assignee: Agere Systems Inc.Inventors: Wen Lin, Charles W. Pearce
-
Patent number: 6852611Abstract: A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper conductor and dielectric are removed and a conductor is fabricated in contact with the DRAM storage plate. The memory allows ROM cells to be hard programmed to different data states, such as Vcc and Vss.Type: GrantFiled: July 31, 2003Date of Patent: February 8, 2005Assignee: Micron Technology, Inc.Inventors: Phillip G. Wald, Casey Kurth, Scott Derner
-
Publication number: 20040185641Abstract: In a thin film transistor (TFT) including an insulating substrate and a polycrystalline silicon island formed on the insulating layer, a grain size of the polycrystalline silicon island is elongated along one direction. A source region, a channel region and a drain region are arranged in the polycrystalline silicon island in parallel with the direction.Type: ApplicationFiled: April 1, 2004Publication date: September 23, 2004Inventors: Hiroshi Tanabe, Hiroshi Haga
-
Patent number: 6750122Abstract: A method of forming a semiconductor structure (see e.g., FIG. 3) includes forming a silicon (e.g., polysilicon) layer 14. The silicon layer 14 is patterned and etched so that at least one sidewall 20 is exposed. An oxygen bearing species (e.g., O2+) is then implanted into the sidewall 20 of the silicon layer 14. In the preferred embodiment, the oxygen bearing species is implanted at an acute angle relative to the plane of the silicon layer 14.Type: GrantFiled: September 29, 1999Date of Patent: June 15, 2004Assignee: Infineon Technologies AGInventor: Thomas Schafbauer
-
Patent number: 6743701Abstract: A method for forming an active area in a substrate includes the steps of growing an isolation oxide on a silicon substrate, providing a photresist mask to define the active areas on the substrate, performing etching and stripping processes, removing the residual oxide from the active areas and selectively growing an epitaxial silicon layer.Type: GrantFiled: December 20, 2002Date of Patent: June 1, 2004Assignee: LSI Logic CorporationInventors: Michael J. Berman, Steven E. Reder, Derryl Allman
-
Patent number: 6737339Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.Type: GrantFiled: October 24, 2001Date of Patent: May 18, 2004Assignee: Agere Systems Inc.Inventors: Wen Lin, Charles W. Pearce
-
Patent number: 6730584Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.Type: GrantFiled: June 15, 1999Date of Patent: May 4, 2004Assignee: Micron Technology, Inc.Inventors: Klaus Florian Schuegraf, Carl Powell, Randhir P. S. Thakur
-
Patent number: 6727122Abstract: A method of forming a polycrystalline silicon active layer for use in a thin film transistor is provided.Type: GrantFiled: December 6, 2002Date of Patent: April 27, 2004Assignee: LG. Philips LCD Co., Ltd.Inventors: Hyun-Sik Seo, Binn Kim, Jong-Uk Bae, Hae-Yeol Kim
-
Publication number: 20040077155Abstract: Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.Type: ApplicationFiled: October 21, 2002Publication date: April 22, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Lin Chen, Liang-Gi Yao, Shih-Chang Chen
-
Patent number: 6713371Abstract: A method to enhance grain size in polysilicon films while avoiding formation of hemispherical grains (HSG) is disclosed. The method begins by depositing a first amorphous silicon film, then depositing silicon nuclei, which will act as nucleation sites, on the amorphous film. After deposition of silicon nuclei, crystallization, and specifically HSG, is prevented by lowering temperature and/or raising pressure. Next a second amorphous silicon layer is deposited over the first layer and the nuclei. Finally an anneal is performed to induce crystallization from the embedded nuclei. Thus grains are formed from the silicon bulk, rather than from the surface, HSG is avoided, and a smooth polysilicon film with enhanced grain size is produced.Type: GrantFiled: March 17, 2003Date of Patent: March 30, 2004Assignee: Matrix Semiconductor, Inc.Inventor: Shuo Gu
-
Patent number: 6703300Abstract: There is a method for forming a multilayer electronic device. The method has the following steps: a) depositing a thin molecular layer on an electrically conductive substrate and b) depositing metal atoms or ions on the thin molecular layer at an angle of about 60 degrees or less with respect to the plane of the exposed surface of the thin molecular layer.Type: GrantFiled: March 29, 2002Date of Patent: March 9, 2004Assignee: The Penn State Research FoundationInventor: Thomas N. Jackson
-
Patent number: 6696345Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers.Type: GrantFiled: January 7, 2002Date of Patent: February 24, 2004Assignee: Intel CorporationInventors: Robert Chau, Mark Doczy, Brian Doyle, Jack Kavalieros
-
Patent number: 6693022Abstract: Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition of the polysilicon to define the doping profile. The feed of dopant to the process gas is stopped toward the end of the vapor deposition, with the result that a boundary layer of undoped silicon is deposited. As a result, a favorable surface quality and better adhesion to a neighboring layer is obtained. The structuring process comprises an at least three-step etching process in which a fluorine containing gas is used for etching in a first step, a chlorine-containing gas is used for etching in a second step and a bromine-containing gas is used for etching in a third step. The invention also encompasses wafers and semiconductor chips produced with the novel doping and/or structuring method.Type: GrantFiled: August 23, 2002Date of Patent: February 17, 2004Assignee: Infineon Technologies AGInventors: Joerg Dreybrodt, Dirk Drescher, Ralf Zedlitz, Stephan Wege
-
Patent number: 6660574Abstract: A method of forming a semiconductor device wherein treatment gate insulating layer is formed such that its edges extend beyond edges of a gate electrode. Specifically, the method includes the steps of forming a non-single crystalline semiconductor layer on an insulating surface, forming a gate electrode on the semiconductor layer with a gate insulating layer formed therebetween, doping portions of the semiconductor layer with an impurity to form source and drain regions, and exposing the doped portions with light to crystallize the portions and activate the dopant. Since the gate electrode extends beyond the edges of the gate electrode, the doping of the portions of the semiconductor layer and the exposure to light irradiation is carried out through a part of the gate insulating layer.Type: GrantFiled: December 22, 1993Date of Patent: December 9, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
-
Patent number: 6645826Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.Type: GrantFiled: March 7, 2002Date of Patent: November 11, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Taketomi Asami, Toru Takayama, Ritsuko Kawasaki, Hiroki Adachi, Naoya Sakamoto, Masahiko Hayakawa, Hiroshi Shibata, Yasuyuki Arai
-
Patent number: 6635554Abstract: System and methods for processing an amorphous silicon thin film sample into a single or polycrystalline silicon thin film are disclosed.Type: GrantFiled: March 23, 2001Date of Patent: October 21, 2003Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Robert S. Sposili, Mark A. Crowder
-
Patent number: 6613653Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.Type: GrantFiled: December 31, 2001Date of Patent: September 2, 2003Assignee: The Board of Trustees of the University of ArkansasInventors: Hameed A. Naseem, M. Shahidul Haque, William D. Brown
-
Patent number: 6602800Abstract: A plasma CVD apparatus for forming a thin film on a semiconductor substrate by plasma reaction includes: (i) a reaction chamber; (ii) a reaction gas inlet for introducing a reaction gas into the reaction chamber; (iii) a lower stage on which a semiconductor substrate is placed in the reaction chamber; (iv) an upper electrode for plasma excitation in the reaction chamber; and (v) an electrically conductive intermediate plate with plural pores disposed between the upper electrode and the lower stage. The intermediate plate divides the interior of the reaction chamber into an upper region and a lower region, wherein the lower region has no significant presence of plasma.Type: GrantFiled: May 9, 2001Date of Patent: August 5, 2003Assignee: ASM Japan K.K.Inventor: Nobuo Matsuki
-
Patent number: 6576831Abstract: Directionally solidified, multicrystalline silicon having a low proportion of electrically active grain borders, its manufacturing and utilisation, as well as solar cells comprising said silicon and a method of manufacturing said cells.Type: GrantFiled: November 14, 2001Date of Patent: June 10, 2003Assignee: Deutsche Solar GmbHInventors: Peter Woditsch, Gunther Stollwerck, Christian Hässler, Wolfgang Koch
-
Publication number: 20030064571Abstract: The present invention provides a process for producing a polycrystal silicon film which comprises a step of forming a polycrystal silicon film by light irradiation of a silicon film set on a substrate, and a step of selecting substrate samples having an average grain size in a plane of the sample of 500 nm or more. According to the present invention, stable production of a high-performance poly-silicon TFT liquid crystal display becomes possible.Type: ApplicationFiled: January 31, 2002Publication date: April 3, 2003Applicant: Hitachi, Ltd.Inventors: Kazuo Takeda, Masakazu Saito, Yukio Takasaki, Hironobu Abe, Makoto Ohkura, Yoshinobu Kimura, Takeo Shiba
-
Patent number: 6534350Abstract: A method for fabricating a low temperature polysilicon thin film transistor incorporating a channel passivation step is described. The method achieves dopant ion activation in a polysilicon gate by using laser irradiation, however, with an additional insulating material layer such as SiOx or SixNy overlying and protecting the channel portion of the polysilicon gate. Any possible contamination by residual photoresist material after a photoresist removal step on the channel portion of the polysilicon gate can thus be avoided. Furthermore, deficiencies such as dopant ions out-diffusion and lateral diffusion can be avoided. The leakage current of the thin film transistors formed by the present invention method is significantly reduced when compared to those formed by a conventional method.Type: GrantFiled: August 2, 2001Date of Patent: March 18, 2003Assignee: Industrial Technology Research InstituteInventors: Chih-Chiang Chen, Kun-Chih Lin, Chung-Shu Chang, Wen-Yu Huang, Pi-Fu Chen
-
Patent number: 6506655Abstract: A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an opening; annealing to form a third thin oxide layer and harden the second oxide layer; implanting a P-type dopant; depositing a fourth silicon nitride layer; depositing a fifth silicon oxide layer and etching it; anisotropically etching the fifth, fourth, and third layers; performing cleanings during which the fifth layer is reetched and takes a flared profile; depositing a sixth polysilicon layer; and implanting an N-type dopant.Type: GrantFiled: March 2, 2000Date of Patent: January 14, 2003Assignee: STMicroelectronics S.A.Inventors: Yvon Gris, Germaine Troillard
-
Patent number: 6486046Abstract: It is possible to prevent lowering in productivity of thin-film transistors with no decrease in performance of the transistors. Provided are depositing an amorphous semiconductor film on a substrate, a first irradiating the amorphous semiconductor film with an energy-rich beam in an atmosphere of a gas containing an inert gas as a major component with a specific amount of oxygen, to change the amorphous semiconductor film into a polycrystalline semiconductor film, and a second irradiating the polycrystalline semiconductor film with an energy-rich beam in an atmosphere of a gas containing an inert gas as major component with oxygen of an amount less than the specific amount.Type: GrantFiled: September 18, 2001Date of Patent: November 26, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Fujimura, Shinichi Kawamura
-
Patent number: 6429101Abstract: A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.Type: GrantFiled: January 29, 1999Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Arne W. Ballantine, Gregory Bazan, Bomy A. Chen, Douglas D. Coolbaugh, Ramachandra Divakaruni, Heidi L. Greer, Herbert L. Ho, Joseph F. Kudlacik, Bernard P. Leroy, Paul C. Parries, Gary L. Patton
-
Publication number: 20020055240Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.Type: ApplicationFiled: December 31, 2001Publication date: May 9, 2002Applicant: The Board of Trustees of the Univ. of ArkansasInventors: Hameed A. Naseem, M. Shahidul Haque, William D. Brown
-
Patent number: 6376348Abstract: Formation of a gate having a polysilicon and silicide layer thereover with reduced resistance and reduced thickness is provided. The polysilicon layer is annealed to diffuse the dopants out from the surface to reduce the dopant concentration to below the level which causes metal rich interface. Thus, a metal silicide layer can be deposited without an intrinsic poly cap layer or requiring the poly to having a decreased dopant concentration. As such, a thinner gate stack having lower sheet resistance and improved reliability is achieved.Type: GrantFiled: September 30, 1997Date of Patent: April 23, 2002Assignee: Siemens AktiengesellschaftInventors: Martin Schrems, Matthias Ilg
-
Patent number: 6339013Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.Type: GrantFiled: May 13, 1997Date of Patent: January 15, 2002Assignee: The Board of Trustees of the University of ArkansasInventors: Hameed A. Naseem, M. Shahidul Haque, William D. Brown