Abstract: The present invention provides a process for manufacturing a semiconductor wafer capable of effectively reducing unevenness having a wavelength of 0.5 mm or more which remains on a surface of the semiconductor wafer after a first polishing step and improving flatness thereof; and a semiconductor wafer manufactured by the manufacturing process. The manufacturing process comprises: plural polishing steps including a first polishing step and a final polishing step; and a corrective polishing step performed after the first polishing step using a polishing cloth harder than that used in the first polishing step.
Abstract: The present invention relates to a method for reproducibly forming a predetermined quantum dot structure and a device produced using same. A crystal facet of a substrate base is patterned for providing a predetermined portion of the crystal facet for subsequent predetermined crystal growth. A first growth material is deposited for crystallographically growing a predetermined mesa structure on the predetermined portion of the crystal facet. The mesa structure, which is a portion of the quantum dot structure, comprises predetermined low index side facets and a predetermined top surface. A second growth material for forming at least a quantum dot on the mesa structure is then deposited. The number, the lateral dimensions and the location of the at least a quantum dot is determined by the mesa structure. A sufficient amount of the second growth material is deposited such that a sufficient thickness for Straski-Krastinow growth of the second growth material on the top surface of the mesa structure is exceeded.
Type:
Application
Filed:
October 29, 2001
Publication date:
June 27, 2002
Inventors:
Robin L. Williams, Jacques Lefebvre, Philip Poole, Geoffrey C. Aers, Charles Lacelle, Jeffrey W. Fraser
Abstract: Aluminum nitride, AlN, layers are grown on silicon substrates using molecular beam epitaxial (MBE) growth. The AlN layer is initially grown by subjecting the silicon substrate to background ammonia followed by repetitively alternating the flux of 1) Al without ammonia and 2) ammonia without Al. After the surface of the silicon structure is sufficiently covered with AlN, the wafer is further subjected to a flux of ammonia and aluminum applied simultaneously to continue the epitaxial growth process. The process minimizes the formation of amorphous silicon nitride, SiNx, compounds on the surface of the substrate which form due to background nitrogen levels in the molecular beam epitaxial growth apparatus. A surface free of amorphous silicon nitride is necessary for formation of high quality AlN. The AlN layer may be further used as a buffer layer for AlGaN/GaN growth. After the AlN layer is grown on the silicon structure, the silicon structure may be subjected to a flux of Ga and nitrogen to form a layer of GaN.
Abstract: An apparatus and method for fabricating a spherical shaped semiconductor integrated circuit according to which a chamber is provided into which spheres of a semiconductor material are introduced therein. Process gases are also selectively introduced into the chamber. The chamber includes a metallic portion that is selectively provided a voltage. Upon receiving the voltage, the chamber attracts ions from the process gases, at least some of the attracted ions treating the spheres according to a particular aspect of the fabrication process.
Abstract: In this invention, one or more metal-containing sources and one or more ammonium halides are heated such that they evaporate into a vacuum environment (except that, in MOMBE, a beam of the organometallic source compound may be created by other means) and made to impinge on a substrate. The materials interact on the substrate to form a film of the desired nitride compound or alloy; the substrate usually will be heated to promote chemical reaction and good film properties such as high crystallinity. Other sources—to provide dopant impurities like silicon or magnesium, for example—would be part of a deposition system envisioned in this invention. Multiple film layers, including quantum wells and superlattices, may be formed using this method, in addition to a single film.
Type:
Grant
Filed:
April 27, 1999
Date of Patent:
October 23, 2001
Assignee:
The United States of America as represented by the Secretary
of the Air Force
Abstract: A method for fabricating a compound semiconductor substrate having a quantum dot array structure includes the steps of forming a plurality of dielectric thin layer patterns on a substrate, thereby forming an exposed area of the substrate, sequentially forming buffer layers and barrier layers in a pyramid shape on the exposed area of the substrate, forming Ga droplets on the barrier layers, transforming the Ga droplets into GaAs quantum dots, performing a thermal process to the substrate, and growing the buffer layers and the barrier layers to thereby form a passivation layer capping the GaAs quantum dots.
Type:
Grant
Filed:
December 2, 1999
Date of Patent:
June 5, 2001
Assignee:
Electronics and Telecommunications Research Institute
Inventors:
Jung-Rae Ro, Sung-Bock Kim, Kyoung-Wan Park
Abstract: Method for forming a single crystal GaN semiconductor substrate and a GaN diode with the substrate is disclosed which forms in a short time period, has a low crystal defect concentration and allows forming a size large enough to fabricate an optical device, the method including either the steps of fast growth of a GaN group material on an oxide substrate to a thickness without cracking and subjecting to mechanical polish to remove a portion of the oxide substrate, and growing GaN again on the grown GaN layer and complete removal of the remaining oxide substrate to obtain a GaN film, or the steps of separating the oxide substrate from the GaN layer utilizing cooling to obtain a GaN film, grown GaN on the GaN film to a predetermined thickness to form a GaN bulk single crystal and mirror polishing it to form the GaN single crystal substrate, whereby a defectless GaN single crystal substrate of a size required for fabrication of an optical device can be obtained within a short time period because fast homoeptaxia
Abstract: The method for forming the compound semiconductor device includes the step of forming a buffer layer so as to cover the periodic corrugation on the InP substrate, wherein the buffer layer forms using a crystal growth temperature lower than the preferred crystal growth temperature. Accordingly, the method for forming the compound semiconductor device can avoid a shape change and a thickness change because of defect of the periodic corrugation. Further, the compound semiconductor device includes a buffer layer formed so as to cover the periodic corrugation on the InP substrate, wherein the buffer layer forms using a crystal growth temperature lower than the preferred crystal growth temperature. Accordingly, the compound semiconductor device can get superior characteristics of the compound semiconductor device.
Abstract: A substrate structure includes a single crystal Si substrate and a surface layer, with a buffer layer interleaved therebetween. The buffer layer includes at least one of an R--Zr family oxide thin film composed mainly of a rare earth oxide and/or zirconium oxide, an AMnO.sub.3 thin film composed mainly of rare earth element A, Mn and O and having a hexagonal YMnO.sub.3 type structure, an AlO.sub.x thin film composed mainly of Al and O, and a NaCl type nitride thin film composed mainly of titanium nitride, niobium nitride, tantalum nitride or zirconium nitride. The surface layer is an epitaxial film containing a wurtzite type oxide and/or nitride. The surface layer can serve as a functional film such as a semiconductor film or an underlying film therefor, and the substrate structure is useful for the manufacture of electronic devices.
Abstract: The present invention provides an improved semiconductor device and method of impeding the diffusion of boron by providing at least one layer of polysilicon and an interface substance. A semiconductor device according to the present invention is comprised of a substrate; gate oxide coupled to the substrate; a layer of polysilicon coupled to the gate oxide; and an interface layer between the layer of polysilicon and the gate oxide, wherein the interface layer impedes diffusion of doping material.
Abstract: The invention relates to a method for integrating semiconductor device epilayers with arbitrary host substrates, where an indium gallium arsenide etch-stop layer (34) is deposited on an indium phosphide growth substrate (32) and device epilayers (36, 38) are grown on the etch-stop layer in inverse order from their final orientation. The device epilayers are then joined to an aluminum nitride host substrate (42) by inverting the growth substrate and device epilayers. The epilayers are bonded to the host substrate using mono-molecular layer forming bonding material and the growth substrate is selectively etched away from the device epilayers. As a result of the inverse epilayer growth, the epilayers are not removed from the growth substrate prior to bonding to the host substrate, thus protecting the device epilayers and reducing processing steps. Additionally, by mono-molecular bonding, sturdy semiconductor devices are formed with low thermal impedance.
Abstract: To present a manufacturing method of semiconductor device capable of forming a homogeneous and highly reproducible gallium nitride crystal, comprising the steps of forming a zinc oxide layer on a monocrystalline substrate, forming a first gallium nitride crystal in a temperature range from 0.degree. C. to 900.degree. C., and forming a second gallium nitride crystal in a temperature range from 900.degree. C. to 2000.degree. C.
Type:
Grant
Filed:
November 26, 1997
Date of Patent:
February 29, 2000
Assignee:
Matsushita Electronics Corporation
Inventors:
Masaaki Yuri, Tetsuzo Ueda, Takaaki Baba
Abstract: A fabricating method of compound semiconductor device is proposed which has a step of varying selective growth ratio of crystal by changing either a mean free path of material gas in gas atmosphere for use in crystal growth or a thickness of a stagnant layer of the material gas, using selective growth mask having opening portion consisting of first region having a narrow width and second region having a wide width.
Abstract: A nitrogen doped single crystal silicon carbide boule is grown by the physical vapor transport process by introducing nitrogen gas into the growth furnace. During the growth process the pressure within the furnace is maintained at a constant value, P.sub.o, where P.sub.o .ltoreq.100 Torr. This is accomplished by measuring the pressure within the furnace and providing the pressure measurement to a process controller which regulates the nitrogen introduction as nitrogen gas is incorporated into the crystal structure. The partial pressure of the nitrogen may be selected to be at a value between 1 and P.sub.o. If the desired partial pressure is less than P.sub.o, an inert gas is added to make up the difference.
Type:
Grant
Filed:
May 8, 1997
Date of Patent:
August 10, 1999
Assignee:
Northrop Grumman Corporation
Inventors:
Donovan L. Barrett, Richard H. Hopkins, James P. McHugh, Hudson McDonald Hobgood
Abstract: In accordance with the invention, a uniformly spaced three-dimensional array of quantum dots is fabricated by forming a uniform grid of intersecting dislocation lines, nucleating a regular two-dimensional array of quantum dots on the intersections, and replicating the array on successively grown layers. The substrate is partitioned into a grid of in-plane lattice parameters, thereby providing a regular array of preferential nucleation sites for the influx atoms of a different size during the epitaxial process. The regularity of the array results in an equal partition of the incoming atoms which, in turn, leads to uniformly sized islands nucleating on these preferred sites. The result is a uniformly sized, regularly distributed two-dimensional array of quantum dots which can be replicated in succeeding layers.