Doping Of Semiconductor Patents (Class 438/499)
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Patent number: 10832913Abstract: A method for forming a semiconductor structure comprises heating a solid material to form a gaseous substance; ionizing the gaseous substance to produce a first type of ions; and implanting the first type of ions into a semiconductor substrate. The method can achieve better abruptness, better shallow junction depth, and better sheet resistance.Type: GrantFiled: February 14, 2018Date of Patent: November 10, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsan-Chun Wang, Chiao-Ting Tai, Che-Fu Chiu, Chun-Feng Nieh
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Patent number: 9029266Abstract: According to one embodiment, a semiconductor device manufacturing method includes depositing a silicon film above a semiconductor substrate, forming an insulating film which includes silicon oxide or silicon nitride on the silicon film, forming a physical guide having a depressed portion above the insulating film, forming a directed self-assembly material layer which includes a first polymer and a second polymer in the depressed portion of the physical guide, phase-separating the directed self-assembly material layer into a first region which includes the first polymer and a second region which includes the second polymer, removing the second region, processing the insulating film by using the physical guide and the first region as masks, and transferring a pattern corresponding to the second region to the insulating film. Further, the silicon film is processed by using the pattern transferred onto the insulating film as a mask.Type: GrantFiled: August 21, 2013Date of Patent: May 12, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kasahara, Noriko Sakurai
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Patent number: 9023720Abstract: After formation of a silicon Fin part on a silicon substrate, a thin film including an impurity atom which becomes a donor or an acceptor is formed so that a thickness of the thin film formed on the surface of an upper flat portion of the silicon Fin part becomes large relative to a thickness of the thin film formed to the surface of side wall portions of the silicon Fin part. A first diagonal ion implantation from a diagonal upper direction to the thin film is performed and subsequently a second diagonal ion implantation is performed from an opposite diagonal upper direction to the thin film. Recoiling of the impurity atom from the inside of the thin film to the inside of the side wall portions and to the inside of the upper flat portion is realized by performing the first and second diagonal ion implantations.Type: GrantFiled: August 25, 2011Date of Patent: May 5, 2015Assignee: Sen CorporationInventors: Genshu Fuse, Michiro Sugitani
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Patent number: 9018046Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.Type: GrantFiled: March 15, 2013Date of Patent: April 28, 2015Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Joshipura Jwalant, Nitin Bansal, Amit Katyal, Massimiliano Picca
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Patent number: 8796667Abstract: A static random access memory (SRAM) includes: a first carbon nanotube (CNT) inverter, a second CNT inverter, a first switching transistor, and a second switching transistor. The first CNT inverter includes at least a first CNT transistor. The second CNT inverter is connected to the first CNT inverter and includes at least one second CNT transistor. The first switching transistor is connected to the first CNT inverter. The second switching transistor is connected to the second CNT inverter.Type: GrantFiled: December 1, 2009Date of Patent: August 5, 2014Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Foundation for Corporate CollaborationInventors: Eun-hong Lee, Un-jeong Kim, Woo-jong Yu, Young-hee Lee
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Publication number: 20140057421Abstract: A semiconductor device production method includes: forming a protection film on a semiconductor substrate; forming a first resist pattern on the protection film; implanting a first impurity ion into the semiconductor substrate using the first resist pattern as a mask; removing the first resist pattern; forming on the surface of the semiconductor substrate a chemical reaction layer that takes in surface atoms from the semiconductor substrate through chemical reaction, after the removing of the first resist pattern; removing the chemical reaction layer formed on the semiconductor substrate and removing the surface of the semiconductor substrate, after the forming of the chemical reaction layer; and growing a semiconductor layer epitaxially on the surface of the semiconductor substrate, after the removing of the surface of the semiconductor substrate.Type: ApplicationFiled: August 13, 2013Publication date: February 27, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: JUNJI OH, MASANORI TERAHARA
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Publication number: 20130237042Abstract: A method of manufacturing a semiconductor device of an embodiment includes: preparing a silicon carbide substrate of a hexagonal system; implanting ions into the silicon carbide substrate; forming, by epitaxial growth, a silicon carbide film on the silicon carbide substrate into which the ions have been implanted; and forming a pn junction region in the silicon carbide film.Type: ApplicationFiled: September 4, 2012Publication date: September 12, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Johji Nishio, Chiharu Ota, Takashi Shinohe
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Patent number: 8513100Abstract: In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film.Type: GrantFiled: December 21, 2011Date of Patent: August 20, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Wensheng Wang
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Patent number: 8501141Abstract: An object of the present invention is to effectively add Ge in the production of GaN through the Na flux method. In a crucible, a seed crystal substrate is placed such that one end of the substrate remains on the support base, whereby the seed crystal substrate remains tilted with respect to the bottom surface of the crucible, and gallium solid and germanium solid are placed in the space between the seed crystal substrate and the bottom surface of the crucible. Then, sodium solid is placed on the seed crystal substrate. Through employment of this arrangement, when a GaN crystal is grown on the seed crystal substrate through the Na flux method, germanium is dissolved in molten gallium before formation of a sodium-germanium alloy. Thus, the GaN crystal can be effectively doped with Ge.Type: GrantFiled: March 26, 2010Date of Patent: August 6, 2013Assignees: Toyoda Gosei Co., Ltd., NGK Insulators, Ltd., Osaka UniversityInventors: Takayuki Sato, Seiji Nagai, Makoto Iwai, Shuhei Higashihara, Yusuke Mori, Yasuo Kitaoka
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Patent number: 8372708Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.Type: GrantFiled: October 4, 2011Date of Patent: February 12, 2013Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K Lui
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Patent number: 8313975Abstract: The purpose is manufacturing a photoelectric conversion device with excellent photoelectric conversion characteristics typified by a solar cell with effective use of a silicon material. A single crystal silicon layer is irradiated with a laser beam through an optical modulator to form an uneven structure on a surface thereof. The single crystal silicon layer is obtained in the following manner; an embrittlement layer is formed in a single crystal silicon substrate; one surface of a supporting substrate and one surface of an insulating layer formed over the single crystal silicon substrate are disposed to be in contact and bonded; heat treatment is performed; and the single crystal silicon layer is formed over the supporting substrate by separating part of the single crystal silicon substrate fixed to the supporting substrate along the embrittlement layer or a periphery of the embrittlement layer.Type: GrantFiled: August 31, 2011Date of Patent: November 20, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Fumito Isaka, Sho Kato, Junpei Momo
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Patent number: 8263483Abstract: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.Type: GrantFiled: July 7, 2009Date of Patent: September 11, 2012Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Hans-Joachim Schulze
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Patent number: 8231726Abstract: An object of the present invention is to obtain, with respect to a semiconductor light-emitting element using a group III nitride semiconductor substrate, a semiconductor light-emitting element having an excellent light extraction property by selecting a specific substrate dopant and controlling the concentration thereof. The semiconductor light-emitting element comprises a substrate composed of a group III nitride semiconductor comprising germanium (Ge) as a dopant, an n-type semiconductor layer composed of a group III nitride semiconductor formed on the substrate, an active layer composed of a group III nitride semiconductor formed on the n-type semiconductor layer, and a p-type semiconductor layer composed of a group III nitride semiconductor formed on the active layer in which the substrate has a germanium (Ge) concentration of 2×1017 to 2×1019 cm?3.Type: GrantFiled: January 19, 2007Date of Patent: July 31, 2012Assignee: Panasonic CorporationInventors: Hisashi Minemoto, Yasuo Kitaoka, Yasutoshi Kawaguchi, Yasuhito Takahashi, Yoshiaki Hasegawa
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Publication number: 20120153295Abstract: Radiation detector. The detector includes an ionic junction having an ionically bonded wide band gap material having a first region dominated by positively charged ionic defects in intimate contact with a second region dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. The detector also includes an ionic junction having a first ionically bonded wide band gap material dominated by positively charged ionic defects in intimate contact with a second ionically bonded wide band gap material dominated by negatively charged ionic defects forming depleted regions on both sides of the junction resulting in a built-in electric field. Circuit means are provided to establish a voltage across the junction so that radiation impinging upon the junction will cause a current to flow in the circuit.Type: ApplicationFiled: February 25, 2011Publication date: June 21, 2012Applicant: Massachusetts Institute of TechnologyInventors: Harry L. Tuller, Sean R. Bishop
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Patent number: 8183879Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.Type: GrantFiled: March 6, 2009Date of Patent: May 22, 2012Assignee: Infineon Technologies AGInventors: Ralf Brederlow, Roland Thewes
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Patent number: 8163635Abstract: A manufacturing method of a semiconductor device includes preparing a semiconductor substrate which is a base substrate of the semiconductor device and which is formed with a concavity and convexity part on the surface of the semiconductor substrate. The method further comprises depositing on the surface of the semiconductor substrate an impurity thin film including an impurity atom which becomes a donor or an acceptor in the semiconductor substrate and performing an ion implantation from a diagonal upper direction to the impurity thin film deposited on the concavity and convexity part of the semiconductor substrate. The method still further comprises recoiling the impurity atom from the inside of the impurity thin film to the inside of the concavity and convexity part by performing the ion implantation.Type: GrantFiled: December 7, 2010Date of Patent: April 24, 2012Assignee: Sen CorporationInventors: Michiro Sugitani, Genshu Fuse
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Patent number: 7989852Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first plane-like metal layer and the N plane-like metal layers are located separate planes. First and second drain regions have a symmetric shape across at least one of horizontal and vertical centerlines. First and second gate regions have a first shape that surrounds the first and second drain regions, respectively. First and second source regions are arranged adjacent to and on one side of the first gate region, the second gate region and the connecting region. The first source region, the second source region, the first drain region and the second drain region communicate with at least two of the N plane-like metal layers.Type: GrantFiled: May 30, 2008Date of Patent: August 2, 2011Assignee: Marvell World Trade Ltd.Inventor: Sehat Sutardja
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Patent number: 7960833Abstract: An integrated circuit comprises N plane-like metal layers, where N is an integer greater than one. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively, where M is an integer greater than one. The first plane-like metal layer and the N plane-like metal layers are located in separate planes. At least two of a first source, a first drain and a second source communicate with at least two of the N plane-like metal layers. A first gate is arranged between the first source and the first drain. A second gate is arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions.Type: GrantFiled: March 17, 2008Date of Patent: June 14, 2011Assignee: Marvell World Trade Ltd.Inventor: Sehat Sutardja
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Patent number: 7923821Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.Type: GrantFiled: April 30, 2008Date of Patent: April 12, 2011Assignee: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Patent number: 7709307Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.Type: GrantFiled: August 21, 2007Date of Patent: May 4, 2010Assignee: Kovio, Inc.Inventors: Arvind Kamath, Patrick Smith, James Montague Cleeves
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Patent number: 7666764Abstract: A compound semiconductor material for forming an active layer of a thin film transistor device is disclosed, which has a group II-VI compound doped with a dopant ranging from 0.1 to 30 mol %, wherein the dopant is selected from a group consisting of alkaline-earth metals, group IIIA elements, group IVA elements, group VA elements, group VIA elements, and transitional metals. The method for forming an active layer of a thin film transistor device by using the compound semiconductor material of the present invention is disclosed therewith.Type: GrantFiled: July 20, 2006Date of Patent: February 23, 2010Assignee: Industrial Technology Research InstituteInventors: Jia-Chong Ho, Jen-Hao Lee, Cheng-Chung Lee, Yu-Wu Wang, Chun-Tao Lee, Pzng Lin
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Patent number: 7662705Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.Type: GrantFiled: August 4, 2005Date of Patent: February 16, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Yong Sun Sohn, Min Yong Lee
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Publication number: 20100009525Abstract: A method including producing a monocrystalline layer is disclosed. A first lattice constant on a monocrystalline substrate has a second lattice constant at least in a near-surface region. The second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.Type: ApplicationFiled: July 7, 2009Publication date: January 14, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Hans-Joachim Schulze
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Patent number: 7605062Abstract: A doped semiconductor junction for use in an electronic device and a method for making such junction is disclosed. The junction includes a first polycrystalline semiconductor layer doped with donors or acceptors over a substrate such that the first doped semiconductor layer has a first polarity, the first layer including fused semiconductor nanoparticles; and a second layer in contact with the first semiconductor layer over a substrate to form the semiconductor junction.Type: GrantFiled: February 26, 2007Date of Patent: October 20, 2009Assignee: Eastman Kodak CompanyInventor: Keith B. Kahen
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Patent number: 7595260Abstract: A bulk-doped semiconductor may be at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may have a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof.Type: GrantFiled: October 4, 2006Date of Patent: September 29, 2009Assignee: President and Fellows of Harvard CollegeInventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Yu Huang
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Patent number: 7494903Abstract: A method is disclosed for making a doped semiconductor transport layer for use in an electronic device comprising: growing in-situ doped semiconductor nanoparticles in a colloidal solution; depositing the in-situ doped semiconductor nanoparticles on a surface; and annealing the deposited in-situ doped semiconductor nanoparticles so that the organic ligands boil off the surface of the in-situ doped semiconductor nanoparticles.Type: GrantFiled: January 29, 2007Date of Patent: February 24, 2009Assignee: Eastman Kodak CompanyInventor: Keith B. Kahen
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Publication number: 20090014840Abstract: The invention is a method for the production of a silicon foil with a targeted charge carrier transport to the p-n transition by means of an integral electric field (‘drift field’). By varying the crystal growth speed and introducing a doping substance into the fluid silicon beforehand, a crystallization process can be carried out in such a way that a gradient over the foil thickness is produced in the doping profile in the silicon. This gradient of the doping profile gives rise to an electric field. With the aid of various foil casting techniques foils that are suitable for the production of solar cells can thus be produced in a relatively simple manner.Type: ApplicationFiled: June 10, 2005Publication date: January 15, 2009Applicant: RGS DEVELOPMENT B.V.Inventor: Axel Georg Schonecker
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Patent number: 7459381Abstract: A method for reducing parasitic resistance in an integrated circuit, comprises connecting first and second terminals of a first transistor to second and first plane-like metal layers, respectively; connecting third and fourth terminals of a second transistor to said first and a third plane-like metal layer, respectively; and connecting first, second and third contact portions of a fourth plane-like metal layer to said second plane-like metal layer, said first plane-like metal layer and said third plane-like metal layer, respectively.Type: GrantFiled: March 22, 2006Date of Patent: December 2, 2008Assignee: Marvell World Trade Ltd.Inventor: Sehat Sutardja
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Publication number: 20080242063Abstract: A solder composition and a method of making the composition. The solder composition comprises a Sn-containing base material and a barrier component having a reactivity with Sn which is higher than a reactivity of Ni or Cu with Sn, the barrier component being present in the composition in an amount sufficient to reduce a reactivity of Sn with both Ni and Cu.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Mengzhi Pang, Charan Gurumurthy
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Patent number: 7375011Abstract: A method of making an ex-situ doped semiconductor transport layer for use in an electronic device includes: growing a first set of semiconductor nanoparticles having surface organic ligands in a colloidal solution; growing a second set of dopant material nanoparticles having surface organic ligands in a colloidal solution; depositing a mixture of the first set of semiconductor nanoparticles and the second set of dopant material nanoparticles on a surface, wherein there are more semiconductor nanoparticles than dopant material nanoparticles; performing a first anneal of the deposited mixture of nanoparticles so that the organic ligands boil off the surfaces of the first and second set of nanoparticles; performing a second anneal of the deposited mixture so that the semiconductor nanoparticles fuse to form a continuous semiconductor layer and the dopant material atoms diffuse out from the dopant material nanoparticles and into the continuous semiconductor layer.Type: GrantFiled: February 22, 2007Date of Patent: May 20, 2008Assignee: Eastman Kodak CompanyInventor: Keith B. Kahen
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Patent number: 7368317Abstract: The invention relates to a method of producing an n-type diamond. The inventive method comprises an n-doping stage during which a donor species is vacuum diffused in a diamond that was initially doped with an acceptor, in order to form donor groups containing the donor species, at a temperature that is less than or equal to the dissociation temperature of the complexes formed between the acceptor and the donor species.Type: GrantFiled: June 3, 2005Date of Patent: May 6, 2008Assignees: Centre National de la Recherche Scientifique-CNRS, Universite de Versailles St-Quentin En YvelinesInventors: Jacques Paul Marie Chevallier, Zephirin Symplice Teukam, Dominique Ballutaud
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Patent number: 7052980Abstract: A method for manufacturing a transistor, includes the steps of preparing a substrate, preparing a liquid material containing a silane compound, the silane compound forming a high order silane when photopolymerized, coating the liquid material on the substrate so as to form a coating film, exposing the coating film to an atmosphere comprising at least one of oxygen and ozone so as to oxidize a surface of the coating film, and performing at least one of thermal processing and photoirradiation processing on the coating film in an inert atmosphere so as to transform the coating film into a silicon layer and a silicon oxide layer disposed on the silicon layer.Type: GrantFiled: March 19, 2004Date of Patent: May 30, 2006Assignee: Seiko Epson CorporationInventor: Takashi Aoki
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Patent number: 6982212Abstract: In the method of manufacturing a semiconductor device (1) with a semiconductor body (2), a doped zone (3) is formed in the semiconductor body (2). The semiconductor body (2) has a crystalline surface region (4), which crystalline surface region (4) is at least partly amorphized so as to form an amorphous surface layer (5). The amorphization is achieved by irradiating the surface (6) with a radiation pulse (7) which is absorbed by the crystalline surface region (4). The radiation pulse (7) has a wavelength which is chosen such that the radiation is absorbed by the crystalline surface region (4), and the energy flux of the radiation pulse (7) is chosen such that the crystalline surface layer (5) is melted. The method is useful for making ultra-shallow junctions.Type: GrantFiled: November 20, 2002Date of Patent: January 3, 2006Assignee: Koninklijke Philips Electronics N.V.Inventor: Peter Adriaan Stolk
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Patent number: 6855991Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.Type: GrantFiled: March 31, 2004Date of Patent: February 15, 2005Assignee: Agere Systems Inc.Inventors: Wen Lin, Charles W. Pearce
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Patent number: 6737339Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.Type: GrantFiled: October 24, 2001Date of Patent: May 18, 2004Assignee: Agere Systems Inc.Inventors: Wen Lin, Charles W. Pearce
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Patent number: 6686281Abstract: A substrate processing apparatus for forming a boron doped silicon-germanium film on one or more substrates in a reaction furnace of a low pressure CVD apparatus uses a mixture gas of GeH4 and SiH4 as a reaction gas, and BCl3 as a doping gas. The substrate processing apparatus includes a plurality of gas outlets for supplying GeH4 at different locations in the reaction tube and a doping gas line for supplying BCl3 at least at an upstream side of gas flow in the reaction tube.Type: GrantFiled: September 5, 2002Date of Patent: February 3, 2004Assignee: Hitachi Kokusai Electric Inc.Inventors: Hirohisa Yamazaki, Takaaki Noda
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Patent number: 6544868Abstract: The present invention provides a method of manufacturing a low resistivity p-type compound semiconductor material over a substrate. The method of the present invention comprises the steps of forming a p-type impurity doped compound semiconductor layer on the substrate by either HVPE, OMVPE or MBE and applying a microwave treatment over the p-type impurity doped compound semiconductor layer for a period of time. The high resistivity p-type impurity doped compound semiconductor layer is converted into a low resistivity p-type compound semiconductor material according to the present invention.Type: GrantFiled: April 25, 2002Date of Patent: April 8, 2003Assignee: United Epitaxy Company, Ltd.Inventors: Tzong-Liang Tsai, Chung-Ying Chang
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Patent number: 6395653Abstract: A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying beneath the top layer 3, an lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6, and an uneven distribution of crystal lattice defects. The crystal lattice defects are substitutionally or interstitially included nitrogen or vacancies.Type: GrantFiled: May 22, 2000Date of Patent: May 28, 2002Assignee: Wacker Siltronic Gesellschaft für Halbleitermaterialien AGInventors: Gunther Obermeier, Alfred Buchner, Theresia Bauer, Jürgen Hage, Rasso Ostermeir, Wilfried Von Ammon
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Patent number: 6268271Abstract: A method for forming a plurality of buried layers inside a semiconductor device is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Then, the first type p+-type ions are implanted into the semiconductor substrate to form the p+-type region under the surface of semiconductor substrate. The semiconductor substrate is etched to form a plurality of concave portions and a plurality of convex portions using the first photoresist. The n+-type ions are second implanted into the semiconductor substrate as a plurality of n+-type region. Next, the oxide layer is deposited over the surface of the plurality of concave portions and the surface of the plurality of convex portions. The plurality of n+-type regions are heated to form as the buried layers. The oxide layer is removed. Finally, a silicon layer is formed to fill the plurality of concave of portions a silicon layer and to cover the surface of the plurality of convex portions.Type: GrantFiled: May 31, 2000Date of Patent: July 31, 2001Assignee: United Microelectronics Corp.Inventor: Kuen-Shyi Tsay
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Patent number: 6258701Abstract: A process for forming insulating structures for integrated circuits that includes depositing a silicon oxide layer; shaping the silicon oxide layer to form first delimiting walls of the insulating regions substantially perpendicular to the substrate; and shaping the silicon oxide layer to form second delimiting walls inclined with respect to the substrate. The first walls have an angle of between approximately 70° and 110° with respect to the surface of the substrate; the second walls have an angle of between approximately 30° and 70° with respect to the surface of the substrate 11. The first delimiting walls are formed using a first mask and etching anisotropically first portions of the oxide layer; the second delimiting walls are formed using a second mask and carrying out a damage implantation for damaging second portions of the oxide layer and subsequently wet etching the damaged portions.Type: GrantFiled: January 11, 2000Date of Patent: July 10, 2001Assignee: STMicroelectronics S,r.l.Inventors: Riccardo Depetro, Michele Palmieri