Abstract: Doped nitride-based semiconductor materials and methods of producing these materials are described herein.

Abstract: A method of synthesizing catalyst doped ZnS nanostructures including preparing a silicon substrate by vacuum depositing a metal catalyst nanostructure on an ultrathin silicon oxide layer, doping a zinc sulfide (ZnS) nanostructure with a catalyst of the metal catalyst nanostructure including at least one of gold (Au), manganese (Mn), and tin (Sn), and modulating ZnS intrinsic defects by the concentration of the catalyst and the size of the ZnS and metal catalyst nanostructures, in which the catalyst is dissolved in a nanowire of the ZnS nanostructure during growth, the concentration of the catalyst in the nanowire is dependent on the size of the catalyst, and the doping is tuned by growth conditions.

Abstract: After formation of a silicon Fin part on a silicon substrate, a thin film including an impurity atom which becomes a donor or an acceptor is formed so that a thickness of the thin film formed on the surface of an upper flat portion of the silicon Fin part becomes large relative to a thickness of the thin film formed to the surface of side wall portions of the silicon Fin part. A first diagonal ion implantation from a diagonal upper direction to the thin film is performed and subsequently a second diagonal ion implantation is performed from an opposite diagonal upper direction to the thin film. Recoiling of the impurity atom from the inside of the thin film to the inside of the side wall portions and to the inside of the upper flat portion is realized by performing the first and second diagonal ion implantations.

Abstract: An object of the present invention is to effectively add Ge in the production of GaN through the Na flux method. In a crucible, a seed crystal substrate is placed such that one end of the substrate remains on the support base, whereby the seed crystal substrate remains tilted with respect to the bottom surface of the crucible, and gallium solid and germanium solid are placed in the space between the seed crystal substrate and the bottom surface of the crucible. Then, sodium solid is placed on the seed crystal substrate. Through employment of this arrangement, when a GaN crystal is grown on the seed crystal substrate through the Na flux method, germanium is dissolved in molten gallium before formation of a sodium-germanium alloy. Thus, the GaN crystal can be effectively doped with Ge.

Abstract: A method that includes implantation of dopants while a III-nitride body is being grown on a substrate, and an apparatus for the practice of the method.

Abstract: The present invention relates to a process for producing a doped silicon layer on a substrate, comprising the steps of (a) providing a liquid silane formulation and a substrate, (b) applying the liquid silane formulation to the substrate, (c) introducing electromagnetic and/or thermal energy to obtain an at least partly polymorphic silicon layer, (d) providing a liquid formulation which comprises at least one aluminum-containing metal complex, (e) applying this formulation to the silicon layer obtained after step (c) and then (f) heating the coating obtained after step (e) by introducing electromagnetic and/or thermal energy, which decomposes the formulation obtained after step (d) at least to metal and hydrogen, and then (g) cooling the coating obtained after step (f) to obtain an Al-doped or Al- and metal-doped silicon layer, to doped silicon layers obtainable by the process and to the use thereof for production of light-sensitive elements and electronic components.

Abstract: The invention relates to a method of fabricating photovoltaic cells in which at least one layer of semiconductor material is deposited continuously on a carbon ribbon (10) to form a composite ribbon (20), said layer having a free face (22, 24) opposite from its face in contact with the carbon ribbon. According to the invention, at least one treatment (28) is applied to the layer of semiconductor material, from said free face (22, 24), in order to implement photovoltaic functions of the cells on said layer, prior to eliminating the carbon ribbon (10). The invention makes it possible to increase productivity in the fabrication of photovoltaic cells, which cells can be of very small thicknesses.

Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.

Abstract: An object of the present invention is to obtain, with respect to a semiconductor light-emitting element using a group III nitride semiconductor substrate, a semiconductor light-emitting element having an excellent light extraction property by selecting a specific substrate dopant and controlling the concentration thereof. The semiconductor light-emitting element comprises a substrate composed of a group III nitride semiconductor comprising germanium (Ge) as a dopant, an n-type semiconductor layer composed of a group III nitride semiconductor formed on the substrate, an active layer composed of a group III nitride semiconductor formed on the n-type semiconductor layer, and a p-type semiconductor layer composed of a group III nitride semiconductor formed on the active layer in which the substrate has a germanium (Ge) concentration of 2×1017 to 2×1019 cm?3.

Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.

Abstract: A manufacturing method of a semiconductor device includes preparing a semiconductor substrate which is a base substrate of the semiconductor device and which is formed with a concavity and convexity part on the surface of the semiconductor substrate. The method further comprises depositing on the surface of the semiconductor substrate an impurity thin film including an impurity atom which becomes a donor or an acceptor in the semiconductor substrate and performing an ion implantation from a diagonal upper direction to the impurity thin film deposited on the concavity and convexity part of the semiconductor substrate. The method still further comprises recoiling the impurity atom from the inside of the impurity thin film to the inside of the concavity and convexity part by performing the ion implantation.

Abstract: A method of forming a patterned layer, including the steps of: (i) depositing via a liquid medium a first material onto a substrate to form a first body on said substrate; (ii) depositing via a liquid medium a second material onto said substrate to form a second body, wherein said first body is used to control said deposition of said second material so as to form a patterned structure including said first and second bodies; and (iii) using said patterned structure to control the removal of selected portions of a layer of material in a dry etching process or in a wet etching process using a bath of etchant.

Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.

Abstract: A vertical semiconductor device with improved junction profile and a method of manufacturing the same are provided. The vertical semiconductor device includes a pillar vertically extended from a surface of a semiconductor substrate, a silicon layer formed in a bit line contact region of one sidewall of the pillar, and a junction region formed within a portion of the pillar contacting with the silicon layer.

Abstract: A method of forming II-VI semiconductor nanowires, comprises: providing a support; depositing a layer including metal alloy nanoparticles on the support; and, heating the support and growing II-VI semiconductor nanowires where the metal alloy nanoparticles act as catalysts and selectively cause localized growth of the nanowires.

Abstract: A Group IV based nanoparticle fluid is disclosed. The nanoparticle fluid includes a set of nanoparticles—comprising a set of Group IV atoms, wherein the set of nanoparticles is present in an amount of between about 1 wt % and about 20 wt % of the nanoparticle fluid. The nanoparticle fluid also includes a set of HMW molecules, wherein the set of HMW molecules is present in an amount of between about 0 wt % and about 5 wt % of the nanoparticle fluid. The nanoparticle fluid further includes a set of capping agent molecules, wherein at least some capping agent molecules of the set of capping agent molecules are attached to the set of nanoparticles.

Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.

Abstract: The present invention relates generally to the field of macro- and microelectronics with the potential for large-scale integration, optics, communications, and computer technology and particularly to the materials for these and other related fields. The present invention provides an anisotropic semiconductor film on a substrate, comprising at least one solid layer of material that comprises predominantly planar graphene-like carbon-based structures and possesses anisotropy of conductivity, and wherein the layer thickness is in a range from approximately 5 nm to 1000 nm.

Abstract: A single crystal silicon wafer for use in the production of insulated gate bipolar transistors is made of single crystal silicon grown by the Czochralski method and has a gate oxide with a film thickness of from 50 to 150 nm. The wafer has an interstitial oxygen concentration of at most 7.0×1017 atoms/cm3, a resistivity variation within the plane of the wafer of at most 5% and, letting tox (cm) be the gate oxide film thickness and S (cm2) be the electrode surface area when determining the TZDB pass ratio, a density d (cm?3) of crystal originated particles (COP) having a size at least twice the gate oxide film thickness which satisfies the formula d??ln(0.9)/(S·tox/2). The wafers have an increased production yield and a small resistivity variation.

Abstract: The invention relates to the use of Reelin as a marker for diagnosing psychiatric conditions. The disclosed tools and techniques can facilitate the diagnosis of psychiatric disorders including major depression, bipolar disorder, schizophrenia and autism.

Abstract: A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters.

Abstract: A method of manufacturing a device comprising individual thin films including a silicon film, a gate insulating film, a conductive film for a gate electrode, an interlayer insulating film, and a conductive film for an electrode and wiring, comprising: a step of applying a liquid material to form an applied film; and a heat treatment and/or a light irradiating treatment of making the applied film into the silicon film, wherein, as the liquid material, a high-order silane composition comprising a high-order silence formed by photopolymerization by irradiating a silane compound solution having a photopolymerization property with UV rays is used.

Abstract: A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices.

Abstract: A method of growing single crystal silicon in a liquid phase comprises preparing a melt by dissolving a solid of silicon containing boron, aluminum, phosphorus or arsenic at a predetermined concentration into indium melted in a carbon boat or a quartz crucible, supersaturating the melt, and submerging a substrate into the melt, thereby growing a silicon crystal containing a dopant element. This method can provide a method of growing a thin film of crystalline silicon having a high crystallinity and a dopant concentration favorably controlled, thereby serving for mass production of inexpensive solar cells which have high performance as well as image displays which have high contrast and are free from color ununiformity.

Abstract: An epitaxial semiconductor crystal plate or wafer capable of attaining increased reliability with enhanced luminance, a manufacturing method thereof, as well as a light-emitting diode (LED). It has been found that epitaxial wafers with enhanced illuminance and increased yield of manufacture can be fabricated by specifically arranging a double-heterostructure epitaxial wafer such that the interface between its p-type clad layer 2 and p-type GaAlAs active layer 3 and that between an n-type GaAlAs clad layer 4 and p-type GaAlAs active layer 3 measure 1×1017 cm−3 or less in oxygen concentration. Also, in order to cause the oxygen concentration near the p-type GaAlAs active layer 3 in layers of the epitaxial wafer to be less than or equal to 1×1017 cm−3, it may be preferable that a nondoped GaAs polycrystal for use as a preselected original material in liquid-phase epitaxial growth be less than or equal to 1×1016 cm−3 or there about.

Abstract: A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying beneath the top layer 3, an lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6, and an uneven distribution of crystal lattice defects. The crystal lattice defects are substitutionally or interstitially included nitrogen or vacancies.

Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.

Abstract: A method of polishing copper with reduced erosion and dishing by a multi-step polishing technique is provided. In one aspect of the invention, a copper layer is polished at a first removal rate and then polished at a second removal rate less than the first removal rate. In another aspect, a computer readable medium is provided bearing instructions, the instructions arranged, when executed by one or more processors, to cause one or more processors to control a polishing system to polish the substrate surface at a first removal rate on a first platen and then polished at a second removal rate less than the first removal rate on a second platen. Further embodiments of the invention include reducing dishing by: controlling platen rotating speeds; increasing the concentration of active chemicals; and cleaning the polishing pads between substrates.

Abstract: An epitaxial semiconductor wafer characterized by making the P-N junction face which having either flat or uneven face in a manner of uniformed thickness from the top surface, due to making a P or N type first layer by the Chemical Vapor Deposition on the basic plate and also to making a N or P type secondary layer on said first layer, while both of the layers being highly and pure controlled silicon, and the light reflectors being located at the out side of said each P or N type layer for concentrating the incoming light to the P-N junction portion.

Abstract: Integrated circuitry and methods of forming integrated circuitry are described. In one implementation, a common masking step is utilized to provide source/drain diffusion regions and halo ion implantation or dopant regions relative to the source/drain regions within one well region of a substrate; and well contact diffusion regions within another well region of the substrate. The common masking step preferably defines at least one mask opening over the substrate within which the well contact diffusion region is to be formed, and the mask opening is suitably dimensioned to reduce the amount of halo ion implantation dopant which ultimately reaches the substrate therebelow. According to one aspect, a plurality of mask openings are provided. According to another aspect, a suitably-dimensioned single mask opening is provided.

Abstract: The present invention relates to a device isolation structure and a device solation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern.

Abstract: A process for removing copper from a boron doped, polished silicon wafer which contains copper on its polished surface and in its interior. In the process, the wafer is annealed at a temperature of at least about 75.degree. C. to increase the concentration of copper on the polished surface of the wafer and decrease the concentration of copper in the interior of the wafer. The polished surface of the annealed wafer is then cleaned to reduce the concentration of copper thereon. In addition, the annealing step is carried out at a temperature and a time such that the concentration of copper on the polished surface of the silicon will not increase by a factor of more than two upon storage of the annealed and cleaned wafer at room temperature for a period of 5 months.

Abstract: A method for fabricating semiconductor substrates with resistivity below 0.02 ohm-cm is provided. This low resistivity is achieved by doping a silicon melt with a phosphorus concentrations above 1.times.10.sup.18. The silicon melt is also doped with a germanium concentration that is 1.5 to 2.5 times that of the phosphorus concentration and a stress and dislocation free crystalline boule is grown. Phosphorus in high concentrations will induce stress in the crystal lattice due to the difference in the atomic radius of silicon atoms versus phosphorus atoms. Germanium compensates for the atomic radius mismatch and also retards the diffusion of the phosphorus as the diffusion coefficient remains relatively constant with a doping of 1.times.10.sup.18 to 1.times.10.sup.21 atoms per cm.sup.3. This will retard phosphorus from diffusing into an overlying epitaxial layer and retard other layers formed on the substrate from being auto-doped.