Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.

Abstract: A group III nitride single crystal substrate including a main surface, the main surface including: a center; a periphery; an outer region whose distance from the center is greater than 30% of a first distance, the first distance being a distance from the center to the periphery; and an inner region whose distance from the center is no more than 30% of the first distance, wherein a ratio (?A??B)/?B is within the range of ±0.1%, wherein ?A is a minimum value of peak wave numbers of micro-Raman spectra in the inner region; and ?B is an average value of peak wave numbers of micro-Raman spectra in the outer region.

Abstract: Methods of producing grating materials with variable height fins are provided. In one example, a method may include providing a mask layer atop a substrate, the mask layer including a first opening over a first processing area and a second opening over a second processing area. The method may further include etching the substrate to recess the first and second processing areas, forming a grating material over the substrate, and etching the grating material in the first and second processing areas to form a plurality of structures oriented at a non-zero angle with respect to a vertical extending from a top surface of the substrate.

Abstract: A method is disclosed for reducing the size and density of defects in a single crystal silicon wafer. The method involves subjected a single crystal silicon ingot to an anneal prior to wafer slicing.

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes in a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer includes a coating layer coated on an outer surface of a main body formed in the material layer, selectively removing a first portion of the coating layer from the material layers to expose the underlying main body of the material layers while maintaining a second portion of the coating layer remaining on the material layers, laterally etching the main body of the material layers exposed by removal of the coating layer, and selectively growing film layers on the exposed main body of the material layer.

Abstract: In one aspect, an organic light-emitting display apparatus is provided including a first sub-pixel, a second sub-pixel, and a third sub-pixel that are each a different color, the apparatus including: a substrate; a first electrode disposed on the substrate; a second electrode disposed on the first electrode so as to face the first electrode; an organic emission layer disposed between the first electrode and the second electrode and comprising a first organic emission layer, a second organic emission layer, and a third organic emission layer; a hole transport layer disposed between the first electrode and the organic emission layer; and an electron accepting layer disposed between the first electrode and the second electrode. The organic light-emitting display apparatus has improved image quality and lifetime.

Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.

Abstract: This invention relates to a method for manufacturing a semiconductor device and semiconductor manufactured thereby, including growing, from a seed island mesa, an abrupt hetero-junction comprising a semiconductor crystal with few crystal defects on a dissimilar substrate that can be used as light emitting and photovoltaic device.

Abstract: A power device manufacturing method is provided. The power device manufacturing method may perform patterning of regions on which a source electrode and a drain electrode are to be formed, may regrow n+-gallium nitride (GaN) and p+-GaN in the patterned regions and thus, a thin film crystal may not be damaged. Also, a doping concentration of n+-GaN or p+-GaN may be adjusted, an ohmic resistance in the source electrode region and the drain electrode region may decrease, and a current density may increase. The power device manufacturing method may regrow n+-GaN and p+-GaN at a high temperature after an n-GaN layer and a p-GaN layer are patterned. Accordingly, a thin film crystal may not be damaged and thus, a reliability may be secured, and an annealing process may not be additionally performed and thus, a process may be simplified and a cost may be reduced.

Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

Abstract: A process of fabricating a nanostructure is disclosed. The process is effected by growing the nanostructure in situ within a trench formed in a substrate and having therein a metal catalyst selected for catalyzing the nanostructure growth, under the conditions in which the growth is guided by the trench. Also disclosed are nanostructure systems comprising a nanostructure, devices containing such systems and uses thereof.

Abstract: A semiconductor device and manufacturing method therefor includes a ?-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a ?-shaped recess.

Abstract: A method for manufacturing a semiconductor power device, comprising the steps of: forming a trench in a semiconductor body having a first type of conductivity; partially filling the trench with semiconductor material via epitaxial growth so as to obtain a first column having a second type of conductivity and having an internal cavity. The epitaxial growth includes simultaneously supplying a gas containing dopant ions of the second type of conductivity, hydrochloric acid HCl in gaseous form and dichlorosilane DCS in gaseous form, so that the ratio between the amount of HCl and the amount of DCS has a value of from 3.5 to 5.5.

Abstract: This disclosure provides systems, methods and apparatus for processing multiple substrates in a processing tool. An apparatus for processing substrates can include a process chamber, a common reactant source, and a common exhaust pump. The process chamber can be configured to process multiple substrates. The process chamber can include a plurality of stacked individual subchambers. Each subchamber can be configured to process one substrate. The common reactant source can be configured to provide reactant to each of the subchambers in parallel. The common exhaust pump can be connected to each of the subchambers.

Abstract: The object of the present invention is to provide a method of fabricating a thermoelectric material and a thermoelectric material fabricated thereby. According to the present invention, since carbon nanotubes with no surface treatment are dispersed in the alloy, electrical resistivity decreases and electrical conductivity increases in comparison to surface-treated carbon nanotubes and an amount of thermal conductivity decreased is the same as that in the case of using surface-treated carbon nanotubes, and thus, a ZT value, a thermoelectric figure of merit, is improved. A separate reducing agent is not used and an organic solvent having reducing powder is used to improve economic factors related to material costs and process steps, and carbon nanotubes may be dispersed in the thermoelectric material without mechanical milling.

Abstract: A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.

Abstract: Methods of selective formation leave high quality epitaxial material using a repeated deposition and selective etch process. During the deposition process, an inert carrier gas is provided with a silicon-containing source without hydrogen carrier gas. After depositing silicon-containing material, an inert carrier gas is provided with an etchant to selectively etch deposited material without hydrogen. The deposition and etch processes can be repeated until a desired thickness of silicon-containing material is achieved. Using the processes described within, it is possible to maintain temperature and pressure conditions, as well as inert carrier gas flow rates, to provide for increased throughput. The inert flow can be constant, or etch rates can be increased by reducing inert flow for the etch phases of the cycles.

Abstract: Methods are disclosed for growing high crystal quality group III-nitride epitaxial layers with advanced multiple buffer layer techniques. In an embodiment, a method includes forming group III-nitride buffer layers that contain aluminum on suitable substrate in a processing chamber of a hydride vapor phase epitaxy processing system. A hydrogen halide or halogen gas is flowing into the growth zone during deposition of buffer layers to suppress homogeneous particle formation. Some combinations of low temperature buffers that contain aluminum (e.g., AlN, AlGaN) and high temperature buffers that contain aluminum (e.g., AlN, AlGaN) may be used to improve crystal quality and morphology of subsequently grown group III-nitride epitaxial layers. The buffer may be deposited on the substrate, or on the surface of another buffer. The additional buffer layers may be added as interlayers in group III-nitride layers (e.g., GaN, AlGaN, AlN).

Abstract: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.

Abstract: When a mixed gas of trichlorosilane and dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 1000 to 1100° C., preferably, 1040 to 1080° C. When dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 900 to 1150° C., preferably, 1000 to 1150° C. According to this, a silicon epitaxial wafer, which has low haze level, excellent flatness (edge roll-off), and reduced orientation dependence of epitaxial growth rate, and is capable of responding to the higher integration of semiconductor devices, can be obtained, and this epitaxial wafer can be used widely in production of semiconductor devices.

Abstract: Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas.

Abstract: A method for producing a semiconductor device is provided. The method includes: forming in a semiconductor substrate a plurality of semiconductor mesas extending to an upper side so that adjacent semiconductor mesas are spaced apart from each other by one of a substantially empty trench and a trench substantially filled with a sacrificial layer selectively etchable with respect to the semiconductor mesas; forming a support structure mechanically connecting the semiconductor mesas spaced apart from each other by one of the substantially empty trench and the trench substantially filled with the sacrificial layer; and processing the semiconductor substrate from the upper side while the semiconductor mesas are mechanically connected via the support structure.

Abstract: A composite substrate 10 includes a sapphire body 1A, a seed crystal film 4 composed of gallium nitride crystal and provided on a surface of the sapphire body, and a gallium nitride crystal layer 7 grown on the seed crystal film 4 and having a thickness of 200 ?m or smaller. Voids 5 are provided along an interface between the sapphire body 1A and the seed crystal film 4 in a void ratio of 4.5 to 12.5 percent.

Abstract: Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.

Abstract: Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.

Abstract: A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

Abstract: A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.

Abstract: A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.

Abstract: The present invention provides a method of producing an epitaxial wafer having a highly flat rear surface without polishing top and rear surfaces of the epitaxial wafer after forming an epitaxial film. A method of producing an epitaxial wafer 100 according to the present invention comprises a step of preparing a semiconductor wafer 10 having a beveled portion 11 formed on its end portion, a first surface 12b, a second surface 12a opposite to the first surface 12b, and edges 13b and 13a on both of the first surface 12b and the second surface 12a, the each edge 13a and 13b is boundary with the beveled portion 11; a step of processing of rolling off an outer peripheral portion 14 of the first surface 12b to form a roll-off region, the outer peripheral portion 14 is extending outward of the wafer from a predetermined position P inner than the position of the edge 13b on 12a the first surface 12b; and a step of forming a first epitaxial film 20 on the second surface 12a.

Abstract: The present invention relates to a self alignment and assembly fabrication method for stacking multiple material layers, wherein a variety of homogeneous/heterogeneous materials can be stacked on a substrate by this self alignment and assembly fabrication method, without using any epitaxial buffer layers or gradient buffer layers; Moreover, these stacked materials can be single crystal, polycrystalline or non-crystalline phase materials. So that, by applying this self alignment and assembly fabrication method to fabricate a multi-layer device, not only the material cost can be effectively reduced, but the wafer alignment problem existing in the conventional wafer bonding process can also be solved. In addition, in the present invention, rapid melting growth (RMG) is used for growing the multiple crystallized materials laterally and rapidly from the substrate surface by liquid phase epitaxy, therefore the thermal budget can be largely reduced when fabricating the multi-layer device.

Abstract: A method for forming an epitaxial layer on a substrate surface having crystalline defect or amorphous regions and crystalline non-defect regions includes preferential polishing or etching the crystalline defect or amorphous regions relative to the crystalline non-defect regions to form a decorated substrate surface having surface recess regions. A capping layer is deposited on the decorated substrate surface to cover the crystalline non-defect regions and to at least partially fill the surface recess regions. The capping layer is patterned by removing the capping layer over the crystalline non-defect regions to form exposed non-defect regions while retaining the capping layer in at least a portion of the surface recess regions. Selective epitaxy is then used to form the epitaxial layer, wherein the capping layer in the surface recess regions restricts epitaxial growth of the epitaxial layer over the surface recess regions.

Abstract: A method for growing a semipolar nitride comprises steps: forming a plurality of parallel discrete trenches on a silicon substrate, each discrete trenches having a first wall and a second wall, wherein a tilt angle is formed between the surface of the silicon substrate and the first wall; forming a buffer layer on the silicon substrate and the trenches, wherein the buffer layer on the first wall has a plurality of growing zones and a plurality of non-growing zones among the growing zones and complementary to the growing zones; forming a cover layer on the buffer layer and revealing the growing zones; and growing a semipolar nitride from the growing zones of the buffer layer and covering the cover layer. Thereby cracks caused by thermal stress between the silicon substrate and semipolar nitride are decreased and the quality of the semipolar nitride film is improved.

Abstract: A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about 2.0 ?m.

Abstract: A manufacturing method of an SiC single crystal includes preparing an SiC substrate, implanting ions into a surface portion of the SiC substrate to form an ion implantation layer, activating the ions implanted into the surface portion of the SiC substrate by annealing, chemically etching the surface portion of the SiC substrate to form an etch pit that is caused by a threading screw dislocation included in the SiC substrate and performing an epitaxial growth of SiC to form an SiC growth layer on a surface of the SiC substrate including an inner wall of the etch pit in such a manner that portions of the SiC growth layer grown on the inner wall of the etch pit join with each other.

Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.

Abstract: Embodiments of methods for depositing silicon germanium (SiGe) layers on a substrate are disclosed herein. In some embodiments, the method may include depositing a first layer comprising silicon and germanium (e.g., a seed layer) atop the substrate using a first precursor comprising silicon and chlorine; and depositing a second layer comprising silicon and germanium (e.g., a bulk layer) atop the silicon germanium seed layer using a second precursor comprising silicon and hydrogen. In some embodiments, the first silicon precursor gas may comprise at least one of dichlorosilane (H2SiCl2), trichlorosilane (HSiCl3), or silicon tetrachloride (SiCl4). In some embodiments, the second silicon precursor gas may comprise at least one of silane (SiH4), or disilane (Si2H6).

Abstract: The non-polar or semi-polar group III nitride layer disclosed in a specific example of the present invention can be used for substrates for various electronic devices, wherein problems of conventional polar group III nitride substrates are mitigated or solved by using the nitride substrate of the invention, and further the nitride substrate can be manufactured by a chemical lift-off process.

Abstract: Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.

Abstract: An (AlInGaN) based semiconductor device, including one or more (In,Al)GaN layers overlying a semi-polar or non-polar III-nitride substrate or buffer layer, wherein the substrate or buffer employs patterning to influence or control extended defect morphology in layers deposited on the substrate; and one or more (AlInGaN) device layers above and/or below the (In,Al)GaN layers.

Abstract: The present invention provides a method for producing an n-type Group III nitride semiconductor product having a high Si concentration and exhibiting favorable crystallinity. In the production method, specifically, an AlN buffer layer is formed on a sapphire substrate by MOCVD, and then a first layer (thickness: 2 ?m) is formed from undoped GaN on the buffer layer by MOCVD at 1,140° C. Subsequently, a second layer (thickness: 200 nm) is formed from SiO2 on the first layer by plasma CVD, and then the second layer is removed by use of BHF (buffered hydrofluoric acid). Next, a GaN layer (thickness: 50 nm) is grown, by MOCVD at 1,140° C., on the first layer exposed by removal of the second layer without supply of an n-type dopant gas. Thus, on the first layer is provided a third layer formed of n-type GaN doped with Si at a high concentration and exhibiting favorable crystallinity.

Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns.

Abstract: A crystalline structure comprising a substrate, which has a surface. The surface has one or more wells formed therein defining one or more growing area and at least one layer of dissimilar crystalline material epitaxially grown on the growing area. A method of making a crystalline structure having a low threading dislocation density comprising the steps of (a) patterning a surface of a substrate material such that one or more wells defining a growing area is formed therein; and (b) epitaxially growing at least one strained layer of dissimilar crystalline material on the growing area of the surface of the substrate material, such that the threading dislocation density of the at least one strained layer is reduced by the one or more wells.

Abstract: A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.

Abstract: A semiconductor device and manufacturing method therefor includes a ?-shaped embedded source or drain regions. A U-shaped recess is formed in a Si substrate using dry etching and a SiGe layer is grown epitaxially on the bottom of the U-shaped recess. Using an orientation selective etchant having a higher etching rate with respect to Si than SiGe, wet etching is performed on the Si substrate sidewalls of the U-shaped recess, to form a ?-shaped recess.

Abstract: A semiconductor process is disclosed. The semiconductor process includes the steps of: providing a substrate having a specific area defined thereon; and performing an etch process by using an etchant comprising H2O2 to etch the specific area for forming a recess.

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: A nitride crystal or wafer with a removable surface layer comprises a high quality nitride base crystal, a release layer, and a high quality epitaxial layer. The release layer has a large optical absorption coefficient at wavelengths where the base crystal is substantially transparent and may be etched under conditions where the nitride base crystal and the high quality epitaxial layer are not. The high quality epitaxial layer may be removed from the nitride base crystal by laser liftoff or by chemical etching after deposition of at least one epitaxial device layer. The nitride crystal with a removable surface layer is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation.

Abstract: Embodiments of the present disclosure relate to methods for pretreatment of substrates and group III-nitride layers for manufacturing devices such as light emitting diodes (LEDs), laser diodes (LDs) or power electronic devices. One embodiment of the present disclosure provides a method including providing one or more substrates having an aluminum containing surface in a processing chamber and exposing a surface of each of the one or more substrates having an aluminum containing surface to a pretreatment gas mixture to form a pretreated surface. The pretreatment gas mixture includes ammonia (NH3), an aluminum halide gas (e.g., AlCl3, AlCl) and an etchant containing gas that includes a halogen gas (e.g., Cl2) or hydrogen halide gas (e.g., HCl).