Abstract: The present invention relates to various high quality n-type and p-type doped gallium-based semiconductor materials, electronic components incorporating these materials, and processes of producing these materials. In particular, The present invention relates processes to achieve high quality, uniform doping of a whole wafer or a thin layer of gallium-based semiconductor materials for various applications such as a vertical power transistor or diode.

Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.

Abstract: In certain desirable embodiments, the present invention relates to the use of 15N isotopes into GaAsN, InAsN or GaSbN films for ion beam analysis. A semiconductor-nitride assembly for growing and analyzing crystal growth in a group III-V semiconductor sample that includes: a substrate; a buffer layer deposited on the substrate, a nitrogen gas injector to incorporate enriched nitrogen gas and the nitrogen gas injector includes a concentration of enriched nitrogen gas, a thin film consisting of at least one group III element containing compound where at least one group III element is covalently bonded with the nitrogen in the presence of the same or different group V element of the buffer layer, and a proton beam to analyze the incorporation of the nitrogen gas in the thin film layer is described.

Abstract: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus includes a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.

Abstract: A charge transfer device 1 has an P-type region, an N-type well provided to the surficial portion of the P-type region, and transfer electrodes having P-type conductivity, provided over the N-type substrate while placing an insulating film in between.

Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.

Abstract: A 13C diamond is doped by proton induced transmutation. P-type doping is achieved by the 13C(p,??)10B reaction. N-type doping is achieved by the 13C(p,?)14N reaction. The transmutation reaction that occurs is determined by selection of proton beam energy. Stacks of junctions each calculated to be in the order of 10 nm thick have been achieved.

Abstract: A method and system for integrated circuit (IC) processing combines an ion implantation tool and a laser anneal tool in a single unit with a shared precision X-Y scanner. A semiconductor wafer is loaded onto a the X-Y table of the scanner. Data defining the desired ion implantation is used to first customize circuit areas on the semiconductor wafer by gating ON and OFF the ion beam while semiconductor wafer is scanned. Any inadvertent ion beam interruptions are noted by storing the locations of the interruptions. The wafer is then reprocessed to correct faults caused by the interruptions. The laser anneal tool positions the laser beam over the semiconductor wafer it is then scanned while gating the laser beam ON and OFF to custom anneal the wafer devices. Again, any inadvertent laser beam interruptions are detected and the locations of the interruptions are stored for reprocessing to correct faults.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.

Abstract: A method is disclosed for producing highly uniform semi-insulating characteristics in single crystal silicon carbide for semiconductor applications. The method includes irradiating a silicon carbide single crystal having net p-type doping and deep levels with neutrons until the concentration of 31P equals or exceeds the original net p-type doping while remaining equal to or less than the sum of the concentration of deep levels and the original net p-type doping.

Abstract: A probe of a scanning probe microscope (SPM) having a field-effect transistor (FET) structure at the tip of the probe, and a method of fabricating the probe are provided. The SPM probe having a source, channel, and drain is formed by etching a single crystalline silicon substrate into a V-shaped groove and doping the etching sloping sides at one end of the V-shaped groove with impurities.

Abstract: Semiconductor devices are known comprising a multiple p-n junction RESURF semiconductor material (10) that provides a voltage-sustaining space-charge zone when depleted from a blocking junction (40). Charge balance is important in the alternating p-type (11) and n-type (12) regions which together provide the voltage-sustaining space-charge zone. The invention provides a low-cost yet reliable way of manufacturing such a material (10), and also devices with such a material (10). A p-type silicon body (100) having an acceptor doping concentration (Na) for the p-type regions (11) of the material is subjected to irradiation with collimated beams (152) of thermal neutrons (150) at window areas (52) in a mask (50) so as to form the n-type regions (12) by transmutation of silicon atoms into phosphorus. A well-defined and controllable phosphorus doping concentration to balance the low acceptor concentration of the p-type regions (11) is achievable in this manner, even when the acceptor concentration is of boron.

Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to the heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).

Abstract: A method for doping Gallium Nitride (GaN) substrates is provided wherein Gallium (Ga) is transmuted to Germanium (Ge) by applying thermal neutron irradiation to a GaN substrate material or wafer. The Ge is introduced as an impurity in GaN and acts as a donor. The concentration of Ge introduced is controlled by the thermal neutron flux. When the thermal neutron irradiation is applied to a GaN wafer the fast neutrons are transmuted together with the former and cause defects such as the collapse of the crystallization. The GaN wafer is thermally treated or processed at a fixed temperature to eliminate such defects.

Abstract: A semiconductor substrate having a source/drain region is initially provided, wherein a channel is formed in the space between the source/drain region within the semiconductor substrate. Then the oxide-nitride-oxide layers are formed on the semiconductor substrate, wherein the nitride layer is a charge trapping layer. Afterward, an electrically conductive material layer such as a gate is formed on and overlays the oxide-nitride-oxide layers. Subsequently, the memory cell is programmed by ultraviolet light irradiation to increase the threshold voltage of the memory cell.

Abstract: According to the present method of manufacturing a semiconductor device, since a contact hole has its opening gradually and continuously made smaller toward the lower interconnection layer, a cavity, which has been produced conventionally, would not be produced in a barrier metal layer and a metal interconnection layer formed along the side wall of the contact hole. As a result, even when the reduction in size of the semiconductor has progressed, it is possible to provide a method of manufacturing semiconductor device having its contact hole in a proper shape, and to provide such a semiconductor device.

Abstract: When the temperature of a silicon substrate is increased, a first annealing gas which is mainly composed of argon or the like that does not react with said silicon substrate with a trace of oxygen added thereto, is supplied to the position of the silicon substrate to prevent any unwanted reaction from occurring on the silicon substrate whose temperature is increasing. When the temperature of the silicon substrate is lowered, a second annealing gas which is mainly composed of nitrogen or the like which has a high thermal conductivity is supplied to the silicon substrate to quickly lower the temperature of the silicon substrate and prevent a doped impurity from being undesirably diffused.

Abstract: We have discovered that, contrary to conventional wisdom about forming DP defects, electrical saturation in highly doped 2D layers of Si does not occur. In accordance with one aspect of our invention, free-carrier concentrations in excess of about 7×1020 cm−3 can be attained in single crystal Si layers &dgr;-doped with a Group V element. In one embodiment, free-carrier concentrations in excess of about 2×1021 cm−3 are realized in single crystal Si that is &dgr;-doped with Sb. In another embodiment, the &dgr;-doped layer is formed as an integral part of an FET.

Abstract: The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.

Abstract: Efficient transmutation doping of silicon through the bombardment of silicon wafers by a beam of protons is described. A key feature of the invention is that the protons are required to have an energy of at least 4 MeV to overcome the Coulomb barrier, thereby achieving practical utility . When this is done, transmutationally formed phosphorus in concentrations as high as 10.sup.16 atoms per cc. are formed from proton beams having a fluence as low as 10.sup.19 protons per square cm. As a byproduct of the process sulfur is also formed in a practical concentration range of about 10.sup.13 atoms per cc. This is readily removed by annealing at temperatures of the order of 700.degree. C. Because of the high energy of the protons, several silicon wafers may be processed simultaneously. As expected, the additional phosphorus is uniformly deposited throughout the entire thickness of a wafer. Masks, either freestanding or contact, may also be used in order to limit the transmuted regions to particular desired areas.

Abstract: Efficient transmutation doping of silicon through the bombardment of silicon wafers by a beam of deuterons is described. A key feature of the invention is that the deuterons are required to have an energy of at least 4 MeV, to overcome the Coulomb barrier and thus achieve practical utility. When this is done, transmutationally formed phosphorus in concentrations as high as 10.sup.16 atoms per cc. are formed from deuteron beams having a fluence as low as 10.sup.19 deuterons per square cm. As a byproduct of the process sulfur is also formed in a practical concentration range of about 10.sup.14 atoms per cc. This can be removed by annealing at temperatures in the order of 700 .degree. C. Additional sulfur continues to form as a result of the decay of P.sup.32. Because of the high energy of the deuterons, several silicon wafers may be processed simultaneously if a suitable mask is available and proper alignment is achieved.

Abstract: An X-ray imaging array is described together with a method for its manufacture. The array is defined by a set of PN junctions in a silicon wafer that extend all the way through between the two surfaces of the wafer. The PN junctions are formed using neutron transmutation doping that is applied to P-type silicon through a mask, resulting in an array of N-type regions (that act as pixels) in a sea of P-type material. Through suitable placement of the biassing electrodes, a space charge region is formed that is narrower at the top surface, where X-rays enter the device, and wider at the lower surface. This ensures that most of the secondary electrons, generated by the X-ray as it passes through the wafer, get collected at the lower surface where they are passed to a charge readout circuit.

Abstract: Bulk crystalline materials are annealed by introducing into them mechanical energy of sufficient intensity to create a large amplitude sound wave. The mechanical energy may be introduced into the material, for example, by laser ablation. Where the bulk crystalline material is a doped semiconductor, the process also electrically activates the material.