Abstract: The invention provides a method of making silicon-on-insulator SOI substrates with nitride buried insulator layer by implantation of molecular deuterated ammonia ions ND3+, instead of implanting nitrogen ions (N+, or N2+) as is done in prior art nitride SOI processes. The resultant structure, after annealing, has a buried insulator with a defect density which is substantially lower than in prior art nitride SOI. The deuterated nitride SOI substrates allow much better heat dissipation than SOI with a silicon dioxide buried insulator. These substrates can be used for manufacturing of high speed and high power dissipation monolithic integrated circuits.

Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The floor of the trench is formed so as to be as smooth and planar as possible, thereby preventing undesirable exposure of the underlying active regions through any unknown or undesired cavity caused by scratches or pits or a deeper than desired sidewall.

Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A method for image reversal in semiconductor processing includes forming a first implant mask layer upon a semiconductor substrate and forming a patterned photoresist layer over the first implant mask layer. Portions of the first implant mask layer not covered by the patterned photoresist layer are removed so as to expose non-patterned portions of the substrate. The photoresist layer is then removed, and a second implant mask layer is formed over the non-patterned portions of the substrate, wherein the first implant mask layer has an etch selectivity with respect to the second implant mask layer. The remaining portions of the first implant mask layer are removed to expose a reverse image of the substrate, including initially patterned portions of the substrate.

Abstract: Non-alloyed, low resistivity contacts for semiconductors using Group III-V and Group II-VI compounds and methods of making are disclosed. Co-implantation techniques are disclosed.

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

Abstract: A doping method includes the step of attaching molecules or clusters to the surface of a semiconductor substrate to enable charge transfer from the molecules or clusters to the substrate surface, thereby inducing carriers underneath the substrate surface. A semiconductor device is fabricated through attachment of molecules or clusters to the surface of a semiconductor substrate. The attachment enables charge transfer from the molecules or clusters to the substrate surface to induce carriers underneath the substrate surface.

Abstract: The present invention provides a semiconductor device production method that eliminates the risk of the occurrence of residual resist in the production process, and as a result, allows the electrical characteristics and reliability of the device to be improved. In this semiconductor device production method comprising steps of: subsequently laminating a first resist layer and a second resist layer having desired patterns on a semiconductor substrate, forming a first conductive region on the semiconductor substrate by injecting a first ion into the semiconductor substrate using the first and second resist layers as masks, removing the second resist layer, forming a second conductive region on the semiconductor substrate by injecting a second ion into the semiconductor substrate using the remaining first resist layer as a mask, and removing the first resist layer.

Abstract: Provided is a process for forming a semiconductor device having salicided contacts. A concentration of metal is formed at the substrate surface by exposing the substrate to a metal plasma. The concentration of metal is then annealed to produce a salicided contact. In a separate embodiment, the metallization plasma and salicide anneal occur in-situ in one process step.

Abstract: The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germanium leaving no source, gate, or drain for the transistor. In embodiments of the invention, nickel is blanket deposited over the source, drain, and gate regions of the germanium-based transistor, annealed to cause the nickel to react with the germanium, and wet etched to remove un-reacted nickel from dielectric regions (e.g., shallow trench isolation (STI) regions) but leave NiGe in the source, gate, and drain regions. The wet etch is a mild oxidizing solution at room temperature.

Abstract: A method of disordering a quantum well heterostructure, including the step of irradiating the heterostructure with a particle beam, wherein the energy of the beam is such that the beam creates a substantially constant distribution of defects within the heterostructure. The irradiating particles can be ions or electrons, and the energy is preferably such that the irradiating particles pass through the heterostructure. Light ions such as hydrogen ions are preferred because they are readily available and produce substantially uniform distributions of point defects at relatively low energies. The method can be used to tune the wavelength range of an optoelectronic device including such a heterostructure, such as a photodetector.

Abstract: A method of manufacturing a semiconductor device is described, wherein clusters of N- and P-type dopants are implanted to form the transistor structures in CMOS devices. For example, As4Hx+ clusters and either B10Hx− or B10Hx+ clusters are used as sources of As and B doping, respectively, during the implants. An ion implantation system is described for the implantation of cluster ions into semiconductor substrates for semiconductor device manufacturing. A method of producing higher-order cluster ions of As, P, and B is presented, and a novel electron-impact ion source is described which favors the formation of cluster ions of both positive and negative charge states. The use of cluster ion implantation, and even more so the implantation of negative cluster ions, can significantly reduce or eliminate wafer charging, thus increasing device yields.

Abstract: Monotomic boron ions for ion implantation are supplied from decaborane vapour. The vapour is fed to a plasma chamber and a plasma produced in the chamber with sufficient energy density to disassociate the decaborane molecules to produce monatomic boron ions in the plasma.

Abstract: A semiconductor wafer is provided having both a memory array area and a periphery circuit region defined on the surface of the semiconductor wafer. A gate composed of a silicon oxide layer and a silicon germanium layer is formed on the surface of the periphery circuit region, and a spacer, a source and a drain of the MOS transistor are formed around the gate. Finally, a nickel (Ni) layer is formed on the surface of the source and the drain, and a rapid thermal annealing process (RTA process) with a temperature ranging between 400° C. and 500° C. is performed for forming a silicon nickel layer on the surface of the source and the drain. Additionally, a shallow junction for the source and the drain is formed.

Abstract: A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enclosed elemental dopant source which is within a secondary vacuum enclosure. A quantity of the elemental dopant atoms having thermal velocities are deposited onto a surface of the wafer, and the wafer is heated for diffusing the elemental dopant into the wafer. In one embodiment, the heating is conducted by heating the wafer in ultra-high vacuum for diffusing the portion of the doping atoms into the wafer, and the deposition and heating occur simultaneously. In another embodiment, the surface of the wafer is hydrogen terminated, the wafer is removed from the UHV system, and the heating of the wafer is conducted outside of the UHV system by heating the wafer in a furnace.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A method of reducing the boron-penetrating of effect in a CMOS transistor provides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the silicon substrate in the active layer. A polysilicon layer is then deposited on the silicon substrate. Next, boron ions (B+) are doped into the polysilicon layer. Next, a gate photoresist with a predetermined gate pattern is formed on the polysilicon layer. The polysilicon not covered by the gate photoresist is then etched to form a polysilicon gate. The gate photoresist is used as a mask to dope boron difluoride ions (BF2+) into the silicon substrate. Finally, after removing the gate photoresist, a tempering procedure is performed to form a shallow junction area of a source/drain region on the silicon substrate.

Abstract: Disclosed is a method for forming a nano-crystal. In the above method, there is prepared a substrate having a metal film or a semiconductor film formed thereon. A focused-ion beam is irradiated onto a plurality of positions on a surface of the metal film or the semiconductor film, whereby the metal film or the semiconductor film is removed at a focal portion of the focused-ion beam but an atomic bond in the metal film or the semiconductor film is broken at an overlapping region of the focused-ion beams due to an radiation effect of the focused-ion beam to form the nano-crystal. The method allows a few nm or less-sized nano-crystals to be formed with ease and simplicity using the focused-ion beam. As a result, the formed nano-crystals come to have a binding energy capable of restraining thermal fluctuation phenomenon at room temperature and thereby it becomes possible to fabricate a tunneling transistor capable of being operated at room temperature.

Abstract: A method of manufacturing a semiconductor device with a core device and an input/output (I/O) device on a semiconductor substrate has been developed. The semiconductor device, fabricated according to the present method, features the I/O device having graded dopant profiles, obtained from a transient enhanced diffusion effect for suppressing a hot carrier effect, and having pocket/halo implant region for decreasing leakage current.

Abstract: A method of removing silicon carbide. A silicon wafer is used as a dummy wafer for inspecting the properties of a silicon carbide thin film which is to be formed thereover. A silicon nitride layer with a thickness larger than about 1000 angstroms is formed on the dummy wafer as a base layer of the silicon carbid thin film. The silicon carbide thin film is then formed on the base layer. The property inspection of the silicon carbide thin film is performed. After the properties inspection, the silicon carbide is stripped using a high density hydrogen plasma. After the step of high density hydrogen plasma, if the remaining silicon nitride layer is thicker than about 500 angstroms, the remaining silicon nitride layer can be used as the base layer again for forming and inspecting the properties of the silicon carbide thin film.

Abstract: A method of fabricating ion implanted doping layers in semiconductor materials by subjecting the material to an ultrasonic treatment during the implantation of predetermined impurities. In an alternate embodiment ultrasonic vibrations are generated by primary ion currents of sufficient density reflected by a piezo-electric element applied to the semiconductor material.

Abstract: A method for forming a dielectric layer with a low dielectric constant (low-k) is described. A semiconductor substrate is provided. A dielectric layer is formed on the substrate. A doping step is performed on the dielectric layer. An annealing step is performed and a gas is simultaneously fed so that the dielectric layer is converted into the low-k dielectric layer.

Abstract: The invention relates to a method of manufacturing a thin film of solid material comprising at least the following steps: a step of ionic implantation through one face of a substrate of said solid materials using ions capable of creating in the volume of the substrate and at a depth close to the mean depth of penetration of the ions, a layer of micro-cavities or micro-bubbles, this step being carried out at a particular temperature and for a particular length of time, an annealing step intended to bring the layer of micro-cavities or micro-bubbles to a particular temperature and for a particular length of time with the intention of obtaining cleavage of the substrate on both sides of the layer of micro-cavities or micro-bubbles. The annealing step is carried out to a thermal budget made in relation to the thermal budget of the ionic implantation step and possibly other thermal budgets inferred for other steps, in order to provide said cleavage of the substrate.

Abstract: A novel plasma treatment method (800, 814). The method includes forming an rf plasma discharge in a vacuum chamber. The plasma discharge includes an inductive coupling structure, which has a first cusp region at a first end of the structure and a second cusp region at a second end of the structure. In some embodiments, a third cusp region, which is between the first and second cusp regions, can also be included. The first cusp region is provided by a first electro-magnetic source and the second cusp region is provided by a second-electro magnetic source. The first electro-magnetic source and the second electro-magnetic source confines a substantial portion of the rf plasma discharge to a region away from a wall of the vacuum chamber. Accordingly, a plasma discharge is substantially a single ionic species (e.g., H1+) can be formed.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to form a pattern at a selected depth (20) underneath the surface. The particles have a concentration sufficiently high to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A technique for forming a film of material having active devices from a donor substrate. The technique has a step of introducing energetic particles in a selected manner through a surface and active devices of a donor substrate a selected depth underneath the active devices, where the particles have a relatively high concentration to define a donor substrate material above the selected depth. The surface of the donor substrate is attached to a release layer on a transfer substrate. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate at the selected depth, whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate. The transfer substrate holds the cleaved material and is used to transfer the cleaved material with active devices onto a target substrate.

Abstract: The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.

Abstract: A technique for forming a film of material from a donor substrate. The technique has a step of introducing energetic particles in a selected patterned manner through a surface of a donor substrate having devices to a selected depth underneath the surface, where the particles have a relatively high concentration to define a donor substrate material above the selected depth and the particles for a pattern at the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate at the selected depth, whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.

Abstract: A method for forming gate structures with smooth sidewalls by amorphizing the polysilicon along the gate boundaries is described. This method results in minimal gate depletion effects and improved critical dimension control in the gates of smaller devices. The method involves providing a gate silicon oxide layer on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon is deposited over the gate silicon oxide followed by a masking oxide layer deposited over the gate electrode layer. The masking oxide layer is patterned for the formation of the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not protected by the masking oxide mask and also amorphizes the area along the boundaries of the polysilicon gate.

Abstract: Methods are provided for fabrication of a circuit on a substrate. After formation of gate electrodes, sidewall spacers are formed on the sides of the gate electrodes. Source/drain extensions and source/drain regions of p-type devices are implanted through openings in a first mask. Source/drain extensions and source/drain regions of n-type devices are implanted through openings in a second mask. The source/drain extensions are implanted at low energy and at a high tilt angle with respect to a normal to the substrate surface, so that the source/drain extensions are formed laterally under the sidewall spacers. The source/drain regions are implanted at low or zero tilt angle and at equal to or higher energy and higher dose than the steps of implanting the source/drain extensions. In one optional feature, the first and second masks are used for implanting wells, channel stops and threshold adjusts for the p-type devices and the n-type devices, respectively.

Abstract: A method for determining a cause for defect formation in an insulating material layer deposited on an electrically conductive layer on a wafer surface is disclosed. In the method, on top of a semi-conducting wafer which has a first insulating material layer deposited, a second insulating material layer is deposited to replace an electrically conductive layer. A third insulating material layer is then deposited on top of the second insulating layer and a water jet which has a high pressure is scanned across a top surface of the third insulating layer with the wafer held in a stationary position. Surface defects are then counted in the predetermined path on the top surface of the third insulating layer for determining the cause for defect formation. When no defects are found, the formation is attributed to electrostatic discharges occurring in the metal conductive layer.

Abstract: A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

Abstract: A system and method for using a nitrous oxide plasma treatment to eliminate defects at an interface between a stop layer and an integral layered dielectric. The system and method provide a reliable and simplified technology that eliminates the small bubble-like defects that can be common to thin nitride layers. The system includes a plasma device and a processing chamber. The method encompasses the steps of preparing a first integral layered dielectric on a substrate before depositing a stop layer thereupon. A plasma gas is then ionized. Preferably, the plasma gas is composed of nitrogen and oxygen. The stop layer is then exposed to the plasma gas until a primary surface of the stop layer is bombarded plane. A second integral layered dielectric is then formed on the primary surface. A top surface of the second integral layered dielectric is generally plane and parallel to the primary surface.

Abstract: The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

Abstract: A semiconductor device having a structure including no LDD region while being structured in such a manner that fixed charges are charged in portions of a gate oxide film overlapping with side walls of a gate electrode formed on the gate oxide film so as to reduce the intensity of electric field between the source and drain of a transistor included in the semiconductor device. The charged-up positive or negative fixed charges serve to invert the conductivity of the channel region portion of a semiconductor substrate on which the gate oxide film is formed, thereby providing the same effect as the LDD region. The invention also provides a method for fabricating the semiconductor device.

Abstract: A CMOS device and a method for forming the same is provided so as to overcome the problem of boron penetration through the thin gate oxide of P-channel devices. Silicon is implanted into the polysilicon gate electrode of the PMOS device functioning as a diffusion barrier for preventing boron penetration through the thin gate oxide and into the semiconductor substrate. As a result, the reliability of the CMOS device will be enhanced.

Abstract: A method for forming salicide contacts and polycide conductive lines in integrated circuits is described which employs the ion implantation of both germanium and arsenic into polysilicon structures and into source/drain MOSFET elements is described. The method is particularly beneficial in the manufacture of sub-micron CMOS integrated circuits. Germanium is implanted into the polysilicon and into the source/drain surfaces forming a amorphized surface layer. Next a low dose, low energy arsenic implant is administered into the amorphized layer. The low dose shallow arsenic implant in concert with the amorphized layer initiates a balanced formation of titanium suicide over both NMOS and PMOS devices in CMOS integrated circuits without degradation of the PMOS devices with an accompanying reduction of gate-to-source/drain shorts. Amorphization by the electrically neutral germanium ions permits the use of a lower dose of arsenic than would be required if arsenic alone were implanted.

Abstract: A method of manufacturing a semiconductor device comprising the steps of: ionizing decaborane; and implanting ionized decaborane into a silicon wafer. Solid decaborane can be vaporized in a reduced pressure atmosphere or by heating. A single decaborane molecule can provide 10 boron atoms while the acceleration energy per each boron atom can be reduced to about 1/10 of the acceleration energy for a decaborane molecule.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A process for ROM coding is described. First, the active device areas and isolation regions are defined on a semiconductor substrate. Then, silicon isotopes (Si.sup.30) are implanted into the active device areas to form isotope regions. Next, the remaining portions of the MOSFET structures are then formed. Next, an interlayer dielectric layer, and a metal layer are sequentially deposited and patterned to finish the basic ROM structure. Upon the receipt of an order, a passivation layer is deposited overlaying the interlayer dielectric layer. Next, a photoresist layer is coated over the passivation layer, and code implant windows are patterned. Finally, neutron irradiation is performed to activate the silicon isotopes into N-type phosphorus ions.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A process is disclosed for forming one or more doped regions beneath the surface of a single crystal semiconductor substrate, such as retrograde wells or deeper source/drain regions, by implantation at low energy which comprises orienting the crystal lattice of the semiconductor substrate, with respect to the axis of the implantation beam, i.e., the path of the energized atoms in the implantation beam, to maximize the number of implanted atoms which pass between the atoms in the crystal lattice. This results in the peak concentration of implanted atoms in the crystal lattice of the single crystal semiconductor substrate being deeper than the peak concentration of implanted atoms in the substrate would be if the axis of the implantation beam were not so oriented with respect to the crystal lattice of the semiconductor substrate during implantation.

Abstract: A method for forming a P-type region in a semiconducting crystalline substrate by ion implantation is disclosed, wherein the implant specie is an ionic molecule that contains titanium and boron.

Abstract: A semiconductor having at least one p-channel transistor (10) with shallow p-type doped source/drain regions (16 and 18) which contain boron implanted into the doped regions (16 and 18) in the form of a compound which consists of boron and an element (or elements) selected from the group which consists of element of substrate (21) and elements which forms a solid solution with the substrate (21). In particular, in the case of silicon substrate, the compound may comprise BSi2, B2Si, B4Si and B6Si. The use of such compounds enables the highly reliable contacts to be formed on the p-doped regions.

Abstract: A process for suppressing boron penetration in BF.sub.2.sup.+ -implanted P.sup.+ -poly-Si gates provides a nitrided layer between the oxide layer and poly-Si through use of inductively-coupled nitrogen plasma (ICNP) to form an energy barrier which the boron ion can hardly penetrate. The process includes the steps of growing an oxide layer by washing the silicon, introducing nitrogen gas into the inductively-coupled plasma (ICP) system and carrying out nitrogen plasma surface treatment at RF power of 150w to 250w; stacking polysilicon of 3000 .ANG. low pressure chemical vapor deposition (LPCVD) system; implanting BF.sub.2.sup.+ at 5.times.10.sup.15 atom/cm.sup.2 and 50 KeV; removing the surface oxide layer by annealing at 900.degree. C. for a time; and plating Al to form a MOS capacitor and measuring electric properties.