Abstract: A p-GaN layer 5 comprising materials such as a Group III nitride compound semiconductor is formed on a sapphire substrate 1 through MOVPE treatment, and a first metal layer 6 made of Co/Au is formed thereon. Then in a planar electron beam irradiation apparatus using plasma, electron beams are irradiated to the p-GaN layer 5 through the first metal layer 6. Accordingly, the first metal layer 6 prevents the surface of the p-GaN layer 5 from being damaged and resistivity of the p-GaN layer 5 can be lowered. Next, a second metal (Ni) layer 10 is formed on the first metal layer 6. And the first metal layer 6 is etched through the second metal layer 10 by using fluoric nitric acid. As a result, the first metal layer is almost completely removed. Then a light-transmitting p-electrode 7 made of Co/Au is formed thereon. As a result, a p-type semiconductor having decreased contact resistance and lower driving voltage can be obtained and optical transmittance factor of the p-type semiconductor improves.

Abstract: Methods for reducing the contact resistance presented by the interface between a silicide and a doped silicon region are presented. In a first method, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy, metal is implanted through the silicide layer into the doped silicon region immediately adjacent the interface. In a second method, a second metal is added to the refractory metal before formation of the silicide. After annealing the refractory metal and the doped silicon region, the second metal diffuses into the doped silicion region immediately adjacent the interface without forming additional phases in the silicide.

Abstract: A gate insulating film in a memory cell portion is thicker than a gate insulating film in a peripheral circuitry. Source/drain of an MOS transistor in the memory cell portion have double-diffusion-layer structures, respectively, and source/drain of an MOS transistor in the peripheral circuitry have triple-diffusion-layer structures, respectively.

Abstract: A method of programming a first memory cell in an array of at least four memory cells in a semiconductor device, each memory cell including a polysilicon gate, first and second spaced-apart diffused regions, a silicide layer provided over the polysilicon gate, an oxide spacer provided contiguous with a vertical sidewall of the polysilicon gate, and a layer of phase change material provided over at least a portion of the silicide layer, contiguous with the oxide spacer, and over the first diffused region.

Abstract: A method of decreasing the dielectric constant of a dielectric layer. First, a dielectric layer is formed on a first conductive layer. A substance is then implanted into the dielectric layer.

Abstract: Provided is an excellent p-type nitride type 3-5 group compound semiconductor having escellent electrical properties such as a low contact resistance to an electrode metal, a low ohmic property, etc., by heat-treating a nitride type 3-5 group compound semiconductor doped with p-type dopant in an hydrogen-containing gas atmosphere of a specific concentration.

Abstract: Edges of a slit and cut to length foil having a dielectric oxide film on at least one surface are edge formed by comprising anodizing the foil in an aqueous oxalic acid electrolyte, further edge a forming the foil in an aqueous citrate electrolyte, preferably dibasic ammonium citrate electrolyte, depolarizing the foil, and then edge forming the foil in an aqueous phosphate electrolyte, preferably an ammonium dihydrogen phosphate.

Abstract: A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate structures, providing an etch stop layer over the first insulating layer, providing a second insulating layer over the etch stop layer, creating a first aperture in the second insulating layer between the first and second gate structures, creating a second aperture in the first insulating layer below the first aperture, and filling the first and second apertures with a conductive material to form the contact. The first aperture has a first aperture width and extends to the etch stop layer. The second aperture has a second aperture width which is less than the first aperture width.

Abstract: Edges of a slit and cut to length foil having a dielectric oxide film on at least one surface are edge formed by edge forming the foil in an aqueous citrate electrolyte, preferably an aqueous ammonium citrate electrolyte, depolarizing the foil, and then edge forming the foil in an aqueous phosphate electrolyte, preferably an ammonium dihydrogen phosphate electrolyte. Using this formation process, a foil with excellent hydration resistance and capacitance is produced.

Abstract: An enhancement mode RF device and method of fabrication includes a stack of compound semiconductor layers, including a central layer defining a device channel, a doped cap layer, and a buffer epitaxially grown on a substrate. Source and drain implant areas, extending at least into the buffer, are formed to define an implant free area in the device channel between the source and drain. Source and drain metal contacts are positioned on an upper surface of the central layer. Several layers of insulation and dielectric are positioned over the device and a gate opening is formed and filled with gate metal. During epitaxial growth, the doped cap layer is tailored with a thickness and a doping to optimize channel performance including gate-drain breakdown voltage and channel resistance.

Abstract: There is disclosed a method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon (SEG) process. The method includes forming a nitride film at a predetermined in a semiconductor substrate region except for the region in which a contact plug will be formed, forming an USG film on the entire surface of the substrate in which the nitride film is formed by chemical enhanced vapor deposition method or a plasma method, etching the USG film by reactive ion etch method to expose the surface of silicon in the structure, and forming a contact plug by performing in-situ process while performing selective epitaxial growth method for the silicon film exposed through the contact hole in the structure.

Abstract: A method for suppressing silicidation retardation effects caused by high dopant concentrations, in particular high Arsenic concentrations, at the surface of a semiconductor substrate. The method includes implanting a preamorphization substance into the substrate to define the boundary of the source/drain, then implanting the dopant at high energy to establish a dopant concentration peak that is distanced from the surface of the substrate. The dopant is activated by rapid thermal annealing, with the relatively deep dopant concentration peak facilitating subsequent improved formation of silicide on the surface of the substrate.

Abstract: In a method of fabricating a semiconductor device in which a metal film is formed that is to serve as the diffusion barrier layer material of a plug electrode material that is used when forming a plug electrode on a diffusion layer electrode or a gate electrode in which a metal silicide layer has been formed, increase in the resistance of the plug electrode is prevented. Immediately after the formation of a plug hole by a dry etching method, silicon ions are implanted with an acceleration voltage of at least 20 KeV and at a dosage of at least 1×1013 atoms/cm2, following which a titanium film and a titanium nitride film are formed as the metal film by a sputtering method without carrying out etching by an RF etching method.

Abstract: An improved method of fabricating a contact hole is provided. A semiconductor substrate is provided wherein a transistor is formed on the substrate. A dielectric layer is formed over the substrate. A patterned mask layer with an opening is formed on the dielectric layer. An UV curing treatment is performed on the mask layer. The dielectric layer is anisotropically etched using the mask layer as a mask to form a contact hole in the dielectric layer.

Abstract: A method of manufacturing a printhead chip comprising the steps of first forming a resistive layer and a conductive layer over a substrate, wherein the resistive layer and the conductive layer act as a heater and a conductive line respectively. Thereafter, at least one insulating layer is deposited over the conductive layer and the resistive layer. Next, at least one metallic layer is deposited over the insulating layer without performing any intermediate photolithographic or etching operations, and then the metallic layer is patterned to form a contact opening. The contact opening passes through the metallic layer and the insulating layer while exposing a portion of the conductive layer. Subsequently, a metal plug is formed in the contact opening so that the metallic layer and the conductive layer are connected, thereby forming an electric circuit. Finally, a thick film is formed over the metallic layer acting as an ink channel for the printhead.

Abstract: A component is produced on a substrate made of SiC. The component has at least one ohmic contact and at least one Schottky contact. The component is brought to a temperature of more than 1300° C. at least during the growth of an epitaxial layer. To ensure that the production of the ohmic contact does not lead to impairment of other structures on the component and that the ohmic contact, for its part, is insensitive with respect to later method steps at high temperatures, the first metal is applied to the substrate for the ohmic contact before the epitaxial layer is grown.

Abstract: A method of improving short channel effects in a transistor. First, a substance is implanted in a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor having a source, a drain, and a channel region is formed on the substrate, wherein the at least one void is in the channel region of the transistor.

Abstract: An integrated circuit device and method of making include an interconnect structure and a capacitor. The interconnect structure includes a metal line and a contact, and the capacitor includes upper and lower metal electrodes. The method includes forming a dielectric layer adjacent a semiconductor substrate, and simultaneously forming a first opening for the interconnect structure and a second opening for the capacitor, in the first dielectric layer. The method further includes selectively depositing a first conductive layer to fill the first opening to form the interconnect structure, and forming the upper and lower metal electrodes with a capacitor dielectric therebetween to form the capacitor in the second opening. The integrated circuit device provides a high-density capacitor having metal electrodes and which is compatible and integrated with dual damascene structures. As such, the capacitor is situated in a same level as a dual damascene interconnect structure.

Abstract: Provided is a semiconductor device having a semiconductor resistance element, which is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration difficult to be controlled, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region 21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a doner concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.

Abstract: A method for simultaneously annealing a source/drain region and removing an overlying native oxide layer using a H2 anneal in the fabrication of integrated circuits is described. Semiconductor device structures are provided in and on a semiconductor substrate wherein the semiconductor device structures include gate electrodes and associated source and drain regions. A resist protective dielectric layer is deposited overlying the semiconductor device structures. The resist protective dielectric layer is etched away where it is not covered by a mask exposing a top surface of the gate electrode and a surface of the semiconductor substrate overlying the source and drain regions wherein a native oxide layer forms on the exposed surfaces. The substrate is annealed using H2 whereby the native oxide is removed and whereby the exposed surface of the semiconductor substrate is recrystallized.

Abstract: A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.

Abstract: A method of activating a compound semiconductor layer into a p-type compound semiconductor layer is provided. In order to reduce the electrical conductivity of the compound semiconductor layer grown by a VPE method, electromagnetic waves having energy larger than the band gap of the compound semiconductor layer are irradiated and annealing is performed. If the amount of the p-type impurities contained in the layer during growth thereof increases, the resistivity of the layer increases and an annealing temperature is lowered. Also, the contact resistance between the compound semiconductor layer and an electrode is reduced.

Abstract: A method of fabricating a self-aligned metal silicide. Two neighboring gates are formed on a substrate, and each of the gates comprises a cap layer thereon. Source/drain regions are formed in the substrate. The source/drain regions comprise a common source/drain region between these two gates. A metal suicide layer is formed on the source/drain region. A first insulation layer is formed to cover the source/drain regions. The cap layer is removed, followed by a pre-amorphous implantation process. A metal silicide layer is formed on the gate. A passivation is formed to protect the metal silicide layer on the gate. A second insulation layer is formed to cover the passivation layer and the first insulation layer. The second and the first insulation layers are patterned to form a contact window to expose the common source/drain region.

Abstract: A method for forming a contact of a semiconductor device is described, in which a conductive layer pattern is electrically connected to a semiconductor substrate and an interlayer insulating film is formed on the semiconductor substrate including the conductive layer pattern. The interlayer insulating film is etched down to a top surface of the conductive layer pattern using a contact formation mask to form a contact hole. The conductive layer pattern is isotropically etched through the contact hole so as to extend the surface area of the exposed conductive layer pattern and the contact hole is filled with conductive material, forming a contact plug electrically connected to the conductive layer pattern. It is therefore possible to extend the contact area between the conductive layer pattern and a contact plug. As a result, the contact resistance is reduced.

Abstract: The adhesion of a conductive polymer film to an oxidized porous pellet anode is improved by the incorporation of a silane coupling agent in the polymer impregnating solution. The incorporation of the silane coupling agent also decreases leakage current and dissipation factor. Suitable silanes are those of the general formula (R1—R3)—Si—(OR2)3. Each of R2 and R3 is a C1-C6 alkyl group such as methyl, ethyl, or propyl R1 can be chosen from a wide variety of organic functional groups such as epoxy, glycidoxy, amino, and pyrrole. The most preferred silane is 3-glycidoxypropyltrimethoxysilane.

Abstract: Semiconductor device and method for fabricating the same, which can improve an isolation characteristic and prevent a leakage current in conducting a borderless process, the device including a semiconductor substrate having an active region and a field region defined thereon, a bilayered gate electrode formed in one direction on the active region, a trench formed in the field region, an isolation region formed in, and on the trench to form a step to the semiconductor substrate so as to be projected from the semiconductor substrate, an insulating film barrier formed along a boundary of the active region projected from the semiconductor substrate, impurity regions in the semiconductor substrate in the active region on both sides of the gate line, a planar protection film having contact holes to the impurity regions on both sides of the active region, and a contact plug formed in each of the contact holes.

Abstract: A method of manufacturing a buried contact in an SRAM includes retaining a portion of the gate oxide layer adjacent to the source/drain region when a buried contact opening is formed. The retained gate oxide layer protects the substrate by acting as a buffer region, thus preventing the over-etching of substrate, which would form a deep trench. Consequently, contact resistance between the buried contact and the source/drain region is lowered, and leakage current at the junction is prevented.

Abstract: A method of manufacturing a flash memory structure that also includes the process of forming a shallow trench isolation structure. The method comprises the steps of providing a semiconductor substrate, and then forming a shallow trench isolation structure within the substrate. Thereafter, etching is carried out to form a shallow trench within a portion of the shallow trench isolation structure. The shallow trench is formed where a common source terminal is subsequently formed. Next, metallic material is deposited into the trench to form a buried metallic layer. Then, a stacked gate is formed above the semiconductor substrate. Finally, ions are implanted into the substrate on each side of the stacked gate using the stacked gate itself as a mask to form a source region and a drain region. The source region and the buried metallic layer are connected together to form a common source region.

Abstract: A method for producing a semiconductor device which comprises a step for forming a gate electrode on a main surface of a semiconductor substrate via a gate oxide film, and a step for directing plasma ions with a gas mixture comprising a first gas containing a hydride of an impurity element and a second gas containing a fluoride of the impurity element into a surface of the semiconductor substrate.

Abstract: A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.

Abstract: Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices are obtained by forming an amorphous silicon carbide termination region in a monocrystalline silicon carbide substrate, at a face thereof, adjacent and surrounding a silicon carbide device. The amorphous termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize the substrate face. The device contact or contacts act as an implantation mask to provide a self-aligned termination region for the device. The terminated devices may exhibit voltage breakdown resistance which approaches the ideal value for silicon carbide.