Abstract: The invention concerns a method for making a thin layer from a structure, including the following steps:

Abstract: There is provided a stable single-phase composition of bisphenolic stillbottoms and methods for making such compositions. There is also provided a resole and a novolac composition that includes in the manufacture of the resins the use of a stable solution of bisphenolic stillbottoms. Methods for making the resins are also provided. There is further provided a low molecular weight phenolic resin useful in the manufacture of paper laminates, such that the resin exhibits improved paper saturation and reduced phenol emissions during treating when compared to the prior art. There is also provided a laminate composition that results in a paper laminate that exhibits improved flexibility when compared to the prior art.

Abstract: A method for fabricating a thin film transistor array and driving circuit comprising the steps of: providing a substrate; patterning a polysilicon layer and an N+ thin film over the substrate to form a plurality of islands; patterning the islands to form P+ doped regions; patterning out source/drain terminals and the lower electrode of a storage capacitor; etching back the N+ thin film; patterning out a gate and the upper electrode of the storage capacitor and patterning a passivation layer and a conductive layer to form pixel electrodes and a wiring layout.

Abstract: A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or Palladium contact layer.

Abstract: A method of implanting dopants into a semiconductor structure wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. The invention also includes semiconductor structures having two doped regions of a semiconductive material separated by a region less heavily doped than the doped regions.

Abstract: A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the resist mask opening to capture any implanted ions scattered in the resist and deflected out of the resist into the mask opening to prevent these ions from reaching the semiconductor substrate and affecting the concentration of ions at the edge of the mask and thus the performance of the integrated circuit.

Abstract: A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction separating the channel region from the substrate of first conductivity type. In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.

Abstract: A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.

Abstract: An integrated inductor is formed on an integrated circuit or other substrate. The inductor is formed of a stack of almost totally enclosed rings of conductive material in which each ring has a single gap. Vias connect adjacent rings on opposite sides of their gaps so as to form a coil shaped structure. The inductor has applications in filtering, in an oscillator, in an antenna, combined with an active detection circuit, combined with an electron source, in a microelectromechanical systems or MEMS, or the like. The inductor may be formed in a vertical orientation or in a horizontal orientation. Chemical mechanical polishing may be used for planarizing layers.

Abstract: An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top surface (49) of the inductor is substantially coplanar with an interconnect surface (31) of the semiconductor substrate, which facilitates connecting to the inductor with standard integrated circuit metallization (57).

Abstract: In this bypass-function added solar cell, a plurality of island-like p+ regions, which is third regions, are formed at a boundary between a p-type region and an n-type region layer constituting a substrate so that the p+ regions project into the region and the region and are separated away from the surface of the substrate. Therefore, in this solar cell, unlike prior art counterparts, the insulating film for isolating the p+ regions and the n electrodes constituting the np+ diode from one another is no longer necessary, thus allowing a reduction in manufacturing cost. As a result, a bypass-function added solar cell with a bypass-diode function added thereto can be provided with low cost and by simple process.

Abstract: An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of the channel region. One way to achieve this arrangement with disposable gate processing is to add disposable sidewalls inside the gate opening (after removing the disposable gate), patterning to selectively remove the source or gate side sidewalls, implant the source and drain regions and remove the remaining sidewall and the proceed. According to a second embodiment, wherein the channel implant can be symmetrical, a relatively low net VT implant is provided in the central region of the channel and a relatively high net VT implant is provided in the channel regions adjacent to the source and drain regions.

Abstract: A process for stripping a photoresist layer after exposure to an ion implantation process. The process includes subjecting a substrate having the ion implanted photoresist layer thereon to a UV radiation exposure and subsequently removing the ion implanted photoresist by conventional stripping processes.

Abstract: A mask ROM and a method for manufacturing such a mask ROM are provided. Here, the mask ROM can be effective to obtain a product that corresponds to each user's specification, where the same aluminum reticle is used even though each user uses different specification. For manufacturing the mask ROM, one of a first route and a second route is selected. The first route is for providing a second NAND circuit 26 with an input of a pulse obtained by passing a standard pulse 93 from an address transition detecting circuit through a first delay circuit 23 and an input of a fixed potential.

Abstract: A method of manufacturing a semiconductor device with a core device and an input/output (I/O) device on a semiconductor substrate has been developed. The semiconductor device, fabricated according to the present method, features the I/O device having graded dopant profiles, obtained from a transient enhanced diffusion effect for suppressing a hot carrier effect, and having pocket/halo implant region for decreasing leakage current.

Abstract: A process for stripping a photoresist layer after exposure to an ion implantation process. The process includes subjecting a substrate having the ion implanted photoresist layer thereon to a UV radiation exposure and subsequently removing the ion implanted photoresist by conventional stripping processes.

Abstract: A spot-implant method for MOS transistors. An asymmetric masking film (50) is formed on a semiconductor substrate and on a transistor gate (30) with an opening (45) adjacent to the transistor gate (30). A spot region (70) is formed adjacent to the transistor gate (30) by ion implantation (60).

Abstract: A method for use with a plasma immersion ion implantations systems wherein a substrate W having a patterned photoresist P thereon is implanted. The method includes ionizing a first gas in a chamber 12 to produce electrically inactive ions and reacting the electrically active ions with the photoresist P to produce outgassing 64. The outgassed material 64 is continuously evacuated until outgassing is substantially completed. The method further includes ionizing a second gas to produce electrically active ions and implanting a positively charged species of the electrically active ions into the substrate. Also disclosed is a method for curing the photoresist prior to ion implantation. A gas is ionized in the chamber 12 to produce positively and electrons. The electrons are first attracted to a substrate in the chamber having patterned photoresist P thereon for hardening the photoresist. The positively charged ions are then implanted into substrate W wherein photoresist outgassing is substantially prevented.

Abstract: Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

Abstract: Heterogeneous assays for different analytes in a single biological sample are performed simultaneously in a multiplexed assay that combines flow cytometry with the use of magnetic particles as the solid phase and yields an individual result for each analyte. The particles are distinguishable from each other by characteristics that permit them to be differentiated into groups, each group carrying an assay reagent bonded to the particle surface that is distinct from the assay reagents of particles in other groups. The magnetic particles facilitate separation of the solid and liquid phases, permitting the assays to be performed by automated equipment. Assays are also disclosed for the simultaneous detection of antibodies of different classes and a common antigen specificity or of a common class and different antigen specificities.

Abstract: An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.

Abstract: A method for manufacturing a field effect transistor (100) includes steps of forming a gate stack (102) on the surface (114) of a semiconductor substrate (108), and defining source/drain regions (104, 106) on either side of the gate stack and a channel region (130) under the gate stack. The channel region has one end (132) proximate a first source/drain region and another end (134) proximate a second source/drain region. The method further includes forming a masking layer (174) on the surface of the semiconductor substrate. The masking layer has a nominal alignment position and a misalignment tolerance. The method still further includes implanting doping ions in the semiconductor substrate to asymmetrically dope the field effect transistor, including selecting a tilt angle and a rotation angle (B, D, F, H) sufficient to ensure shadowing of one end of the channel region from implantation of the doping ions.

Abstract: A method for making a ULSI MOSFET chip includes masking areas such as transistor gates with photoresist mask regions. Prior to ion implantation, the top shoulders of the mask regions are etched away, to round off the shoulders. This promotes subsequent efficient quasi-vertical ion implantation, commonly referred to as “high aspect ratio implantation” in the semiconductor industry.

Abstract: In a process for adjusting the carrier lifetime in a semiconductor component (1) by means of particle irradiation (P), at least two defect regions (10, 11, 12, 13) are produced in the semiconductor component (1). In this process, a particle beam (P), consisting of particles (a, b, c, d) with at least approximately the same initial energy, is acted on by at least one means (2), before reaching the semiconductor component (1), in such a way that the particles (a, b, c, d) subsequently have different energy values, at least two energy value groups being distinguishable. It is thereby possible, with a single particle irradiation operation, to produce an arbitrary number of defect regions whose arrangement and weighting is arbitrarily selectable.

Abstract: A method of making a semiconductor device includes forming gate electrode over a substrate and a protective layer over the gate electrode. A portion of the protective layer is selectively removed to expose a peripheral region of the gate electrode. A remainder of the protective layer remains disposed over a central region of the gate electrode. An upper portion of the peripheral region of the gate electrode is then removed typically leaving an underlying portion. Often, a dopant material is implanted into the substrate adjacent to and beneath the underlying portion to simultaneously form lightly-doped and heavily-doped regions beneath and adjacent to the underlying portion, respectively. In addition, all or part of the underlying portion may be oxidized to provide a gate electrode with reduced width.

Abstract: A method for fabricating a semiconductor device having LDD structure. The method includes: a first step for forming an electrically insulating layer on an active area defined on a surface of a semiconductor substrate; a second step for forming a conductive layer on said insulating layer; a third step for forming a patterned photoresist layer of a downward tapered shape on said conductive layer; a fourth step for forming a gate electrode by patterning said conductive layer using a mask provided by bottom portions of said patterned photoresist layer; a fifth step for forming heavilyly doped regions at both sides of said gate electrode by introducing ions using a mask provided by top portions of said patterned photoresist layer; a sixth step for removing said patterned photoresist layer; and a seventh step for forming lightly doped regions at both sides of said gate electrode by introducing ions using a mask provided by said gate electrode.

Abstract: A semiconductor device and a method of fabricating such a semiconductor device in which a silicon nitride film constituting a protective film for ion implantation is used for improving the device structure in order that conversion of a metal film into a silicide for reducing the resistance of a shallow-junction diffused layer may not be prevented by the knock-on phenomenon of oxygen, thereby reduce the fabrication cost. A silicon nitride film, which is used as a protective film for ion implantation into a substrate and a gate polysilicon, is processed into side walls of the gate polysilicon thereby to omit the step of forming side walls by a silicon oxide film. Further, in the case where boron is diffused into the gate polysilicon, boron diffusion is suppressed by nitrogen knock-on, thereby preventing boron from going through the gate oxide film.

Abstract: A method of improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, an implant mask which has a variable permeability to implanted impurities is formed on the surface of a substrate having a first dopant region. A first portion of the implant mask overlies a first portion of the first dopant region. The structure is subjected to high energy implantation which forms a heavily doped region. A first portion of the heavily doped region is located along the lower boundary of the first dopant region. A second portion of the heavily doped region which extends along a side boundary of the first dopant region is formed by impurity ions which pass through the first portion of the implant mask. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: The present invention aims to provide a continuous forming method and apparatus for functional deposited films having excellent characteristics while preventing any mutual mixture of gases between film forming chambers having different pressures, wherein each of semiconductor layers of desired conduction type is deposited on a strip-like substrate within a plurality of film forming chambers, by plasma CVD, while the strip-like substrate is being moved continuously in a longitudinal direction thereof through the plurality of film forming chambers connected via a gas gate having the structure of introducing a scavenging gas into a slit-like separation passage, characterized in that at least one of the gas gates connecting the i-type layer film forming chamber for forming the semiconductor junction and the n- or p-type layer film forming chamber having higher pressure than the i-type layer film forming chamber has the scavenging gas introducing position disposed on the n- or p-type layer film forming chamber sid

Abstract: A semiconductor device (83)including a transistor (85) with a nonuniformly doped channel region can be formed with a relatively simple process without having to use high dose implants or additional heat cycles. In one embodiment, a polysilicon layer (14) and silicon nitride layer (16) are patterned at the minimum resolution limit. The polysilicon layer is then isotropically etched to form a winged gate structure (32). A selective channel implant step is performed where ions are implanted through at least one of the nitride wings of the winged gate structure (32) but are not implanted through the polysilicon layer (14). Another polysilicon layer (64)is conformally deposited and etched such that the polysilicon (74) does not extend beyond the edges of the nitride wings.

Abstract: A semiconductor fabrication method is provided for forming transistors upon a semiconductor substrate wherein the semiconductor substrate has first, second and third substrate regions. A single mask layer is formed over the semiconductor substrate. The single mask layer has a first mask portion covering the first substrate region, a second mask portion exposing the second substrate region, and a third mask portion partially covering the third substrate region. A first type impurity dopant is differentially introduced into the first, second and third substrate regions according to the single mask layer. First, second and third transistors are formed in the first, second and third substrate regions, respectively. The first and second transistors have differing conductivity types and the first and third transistors have the same conductivity type. The first and third transistors also have differing threshold voltages according to the differential introducing of the dopant.