Abstract: A method of forming a multi-layered dual-doped polysilicon structure that minimizes Boron penetration into the n+ polysilicon during formation of the p+ polysilicon. The method of the present invention also reduces the migration of Boron (p+ gate dopant) from the p+ polysilicon and the migration of Arsenic and/or Phosphorous (n+ gate dopant) from the n+ polysilicon during subsequent fabrication processing steps. The present invention is also directed to a semiconductor device having a gate dopant barrier that minimizes gate dopant penetration and migration.

Abstract: A method for manufacturing a CMOS semiconductor device having a first conductivity type (1st-type) MOS transistor including a gate electrode made of a 1st-type polysilicon film of high impurity concentration and a second conductivity type (2nd-type) MOS transistor including a gate electrode made of a 2nd-type polysilicon film of high impurity concentration on a single semiconductor substrate, comprising the steps of: forming a polysilicon film on the substrate; forming a first resist mask on the polysilicon film so as to cover a 2nd-type MOS transistor formation region, followed by implanting a 1st-type impurity at a high concentration into the polysilicon film by using the first resist mask; removing the first resist mask; forming a second resist mask on the polysilicon film so as to cover a 1st-type MOS transistor formation region, followed by implanting a 2nd-type impurity at a high concentration into the polysilicon film by using the second resist mask; etching the 2nd-type polysilicon film by a specific

Abstract: After an ion having n-type or p-type impurity necessary for a crystalline silicon film is implanted by a known ion implantation or ion doping, a laser light or an equivalent intense light is irradiated onto the crystalline silicon film, to thereby improve the crystallinity of the silicon film and activate the impurity, and in the succeeding process, the silicon film is not thermally annealed at 450.degree. C. or higher. Also, under a state where a substrate is heated at 50 to 500.degree. C., preferably 200 to 350.degree. C., an ion having n-type or p-type impurity necessary for a crystalline silicon film is implanted by the ion doping, and in the succeeding process, the silicon film is not thermally annealed at 450.degree. C. or higher.

Abstract: In a method for manufacturing a surface channel type P-channel MOS transistor, a gate insulating layer is formed on a semiconductor substrate, and a gate electrode is formed on the gate insulating layer. Then, a P-type impurity diffusion preventing operation is performed upon the gate electrode, and P-type impurities are implanted into the gate electrode.

Abstract: Gate electrodes for integrated circuit field effect transistors are fabricated by forming a polysilicon layer on a gate insulating layer opposite an integrated circuit substrate, forming an amorphous impurity layer on the polysilicon layer opposite the gate insulating layer, and forming an amorphous silicon layer on the amorphous impurity layer opposite the polysilicon layer. The amorphous silicon layer, the amorphous impurity layer and the polysilicon layer are patterned to define a gate electrode pattern. The polysilicon layer, the amorphous impurity layer and the amorphous silicon layer then are converted into a polysilicon gate having a first surface adjacent the gate insulating layer, a second surface opposite the gate insulating layer, and a buried doped layer within the polysilicon gate electrode that is spaced apart from the first and second surfaces thereof. The converting preferably takes place by thermally treating the gate electrode pattern.

Abstract: The thickness of a capacitor dielectric layer is reduced by a manufacturing method. A first polysilicon layer is deposited on a substrate that has an isolation structure. Subsequently, nitrogen ions are implanted into the first polysilicon layer. The thickness of an oxide layer formed on the first polysilicon layer is determined by dosage of the implanted nitrogen ions. Next, the first polysilicon layer is patterned, so as to form a bottom electrode of the capacitor and expose a portion of the substrate. A thermal oxidation process is then performed to form an oxide layer, which is used as a gate oxide layer on the substrate and is also used as a dielectric layer in capacitor on the bottom electrode. Subsequently, a second polysilicon layer is deposited and patterned as an upper electrode of the capacitor on the capacitor dielectric layer.

Abstract: The present invention relates to a process for the production of polycrystalline silicon mouldings substantially free of low lifetime edge regions and the use of these mouldings.

Abstract: A method of making a semiconductor device includes forming gate electrode over a substrate and a protective layer over the gate electrode. A portion of the protective layer is selectively removed to expose a peripheral region of the gate electrode. A remainder of the protective layer remains disposed over a central region of the gate electrode. An upper portion of the peripheral region of the gate electrode is then removed typically leaving an underlying portion. Often, a dopant material is implanted into the substrate adjacent to and beneath the underlying portion to simultaneously form lightly-doped and heavily-doped regions beneath and adjacent to the underlying portion, respectively. In addition, all or part of the underlying portion may be oxidized to provide a gate electrode with reduced width.

Abstract: In a non-volatile semiconductor memory device, a top surface of a floating gate that is made of polysilicon is advantageously kept smooth to increase the uniformity of an overlying interpoly dielectric layer onto which a control gate is formed. The floating gate is doped after at least a portion of the overlying interpoly dielectric layer has been formed. Ion implantation techniques are employed to implant dopants through the overlying layer or layers and into the floating gate. Consequently, the potential for polysilicon grain growth at or near the top surface of the floating gate, which can lead to significant depressions in the overlying layers and data retention problems in the memory cell, is substantially reduced.

Abstract: With the growing practice of doping gates for MOSFETs with boron, problems have been encountered due to later diffusion of the boron into the active region. To block this, argon ions are implanted into the gate pedestal material prior to doping it with boron. The damage caused by the argon ions results in traps that getter the boron atoms, behaving in effect as a diffusion barrier. The invention is directed specifically to gate pedestals that are less than about 3000 Angstroms thick. Under these conditions it has been determined that the implantation energies of the argon ions should not exceed 80 keV. It is also important that the dosage of argon be in the range from 1.times.10.sup.15 to 1.times.10.sup.16 per cm.sup.2. Preferably doses in excess of 5.times.10.sup.15 should be used as they also lead to improvements in subthreshold swing and hot carrier immunity.

Abstract: A multi-step dry-etching method that sequentially employs plasma etching and reactive ion etching process steps to form the pairs of adjacent, doped polysilicon gate electrodes of a twin-well CMOS device. The initial dry-etching process step uses to best advantage the speed of plasma etching to rapidly form pairs of adjacent p- and n-type gate-precursor features with substantially vertical sidewalls from the upper 50-80% of a doped polysilicon layer which lies on an insulating film. The gate-precursor features and, subsequently, the gate electrodes are formed from pairs of adjacent p- and n-type regions within the doped polysilicon layer which lie over pairs of adjacent n- and p-wells (the twin wells of the CMOS device), respectively, within a substrate. The subsequent dry-etching process step uses reactive ion etching to complete the formation of the pairs of adjacent, doped polysilicon gate electrodes from the remaining 50-20% of the etched, doped polysilicon layer without over-etching the insulating film.

Abstract: A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions.The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance.

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract: In manufacturing a semiconductor device, an amorphous silicon layer with a predetermined thickness to be electrically connected to a silicon substrate is formed on a silicon oxide film formed on the silicon substrate. The interface between the silicon oxide film and the amorphous silicon layer is mixed by implanting ions through the amorphous silicon layer. Nuclei are formed on the surface of the amorphous silicon layer by annealing of the amorphous silicon layer and irradiation of a predetermined material. Convexities are formed on the surface of the amorphous silicon layer using the nuclei as centers by annealing the amorphous silicon layer having the nuclei.

Abstract: A method for producing a polycrystalline silicon structure and a polycrystalline silicon layer to be produced by the method of first forming a primary silicon structure in an amorphous or polycrystalline form, and doping the structure with a dopant, in particular with oxygen, in a concentration exceeding the solubility limit. In a subsequent heat treatment, dopant precipitations are formed which control grain growth in a secondary structure being produced. Such a contact polycrystalline silicon structure can be used, in particular, as a connection of a monocrystalline silicon region.

Abstract: A method is provided for forming a polysilicon gate. A stacked gate with a first polysilicon layer/an oxide layer/a second polysilicon layer multiple structure is formed. The invention provides another method for forming a polysilicon gate, in which a first polysilicon layer is formed and waits for a period of time. Then, a second polysilicon layer is formed on the first polysilicon layer. A grain boundary is formed between the first polysilicon layer and the second polysilicon layer. The invention provides still another method for forming a polysilicon gate, in which a polysilicon layer is formed at the temperature of about 600-700.degree. C. and the pressure of about 1-5 torr to form a small-grained polysilicon layer. The three methods for forming a polysilicon gate can prevent the heavy ions from passing through the polysilicon gate and the gate oxide layer into the substrate while performing a pre-amorphization implant process.

Abstract: An STI fabrication method for a semiconductor device is disclosed, which includes the steps of forming a trench on a semiconductor substrate, forming a conductive film on the trench, ion-implanting a germanium into the conductive film, and oxidizing the conductive film.

Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration.

Abstract: A CMOS device and a method for forming the same is provided so as to overcome the problem of boron penetration through the thin gate oxide of P-channel devices. Silicon is implanted into the polysilicon gate electrode of the PMOS device functioning as a diffusion barrier for preventing boron penetration through the thin gate oxide and into the semiconductor substrate. As a result, the reliability of the CMOS device will be enhanced.

Abstract: A semiconductor process in which the transistor channel is defined by opposing sidewalls of a pair of masking structures formed on an upper surface of a semiconductor substrate. The spacing between the opposed sidewalls is defined by the thickness of the spacer structure formed between the sidewalls. The thickness of the spacer structure is preferably in the range of approximately 0.04 microns. A masking layer is formed on an upper surface of a semiconductor substrate. The masking layer includes first and second masking structures and a channel trench material. Opposing sidewalls of the first and second masking structures are laterally displaced by a channel displacement. The opposing sidewalls together with an upper surface of the semiconductor substrate define a channel trench. The channel trench is displaced above and aligned with a channel region of the semiconductor substrate. The channel trench material fills the channel trench.

Abstract: A method for fabricating MOS transistors comprises the steps of forming a polysilicon layer, having an underlying gate oxide layer on the major surface of a silicon substrate, providing a mask to cover a predetermined portion except the portion for an N-type polysilicon layer to be formed, doping the polysilicon layer uncovered by the first mask with N-type ions, providing a second mask to cover a predetermined portion except the portion for a P-type polysilicon layer to be formed, doping the polysilicon layer uncovered by the second mask with boron ions, subjecting the polysilicon layer to a patterning process to define gate electrodes of an NMOS and PMOS transistors, providing a third mask to cover a predetermined portion except the portion for an NMOS transistor to be formed, doping N-type ions into substrate portion for the NMOS transistor to be formed using the third mask and the gate electrodes as a mask to thereby form a source and a drain of the NMOS transistor, forming a silicon oxide layer over each

Abstract: A method of forming buried contacts in MOSFET and CMOS devices which substantially reduces the depth of the buried contact trench. A split polysilicon process is used to form the gate electrode and contact electrode. The first polysilicon layer is very thin layer of undoped polysilicon, having a thickness of less than 100 Angstroms. The second polysilicon layer is a layer of doped polysilicon having a thickness of between about 950 and 1150 Angstroms. The buried contact can be formed either using ion implantation or diffusion of impurities from the layer of doped second polysilicon into the contact region. When the metal layers are etched to form the gate electrode and contact electrode the resulting buried contact trench is less than 500 Angstroms deep.

Abstract: A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.

Abstract: A flash memory has diffused layers extending in a column direction to form channel regions between each two of the diffused layers, field oxide films extending in a row direction to divide the channel regions into separate channels arranged in a matrix, a floating gate disposed for each channel as a split gate, and a strip control gates extending in the row direction and overlying each row of the split floating gate. Each of the floating gates has a lower layer having a lower impurity concentration and an upper layer having a higher impurity concentration. The lower impurity concentration of the lower layer prevents fluctuations in device characteristics while the higher concentration of the upper layer enhances etch rates in two etching process for forming the floating gates of a matrix.

Abstract: A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric operatively positioned adjacent the thin film channel region; and e) the thin film channel region comprising at least an inner layer, an outer layer and a middle layer sandwiched between the inner layer and the outer layer, the inner layer and the outer layer comprising polycrystalline silicon and having respective energy bandgaps, the middle sandwich layer comprising a polycrystalline material and having a lower energy bandgap than either of the inner and outer layers. Alternately, the channel region is homogeneous, comprising germanium or an alloy of polycrystalline silicon and germanium.

Abstract: A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening.

Abstract: Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source.

Abstract: A method for fabricating a silicon-on-sapphire wafer for processing by silicon-wafer-processing equipment. A layer is deposited on a backside of a silicon-on-sapphire wafer, the layer having optical and electrical properties of silicon, wherein the silicon-on-sapphire wafer may be sensed by a sensor designed to sense a presence of a silicon wafer.

Abstract: A method of fabricating a metal-oxide semiconductor (MOS) transistor is provided. This method is devised particularly to reduce the level of degradation to the MOS transistor caused by hot carriers. In the fabrication process, a plasma treatment is applied to the wafer to as to cause the forming of a thin layer of silicon nitride on the wafer which covers the gate and the lightly-doped diffusion (LDD) regions on the source/drain regions of the MOS transistor. This thin layer of silicon nitride acts as a barrier which prevents hot carriers from crossing the gate dielectric layer, such that the degradation of the MOS transistor due to hot carriers crossing the gate dielectric layer can be greatly minimized.

Abstract: A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop.

Abstract: A semiconductor fabrication process is presented which optimizes the position of impurities within a gate conductor a the source/drain straddling the gate conductor. Optimal positioned is achieved by using separate implants of different energies depending upon whether the gate conductor connotes a PMOS or NMOS transistor. A layer of polysilicon used to form the gate conductor is doped before patterning so that the source and drain regions are protected. A low energy implant is performed when implanting a fast diffuser such as boron, and a high energy implant is performed when implanting a slow diffuser like arsenic. This enables optimum positioning of the impurities throughout the gate conductor cross-section after heat cycles are applied. Fast diffusers are initially placed far from the bottom surface of the polysilicon, and diffuse near the bottom surface of the polysilicon when heat is applied.

Abstract: A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N.sub.2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e.

Abstract: The method of manufacturing a thin film transistor, including the steps of: a first step, after a poly-crystal silicon film has been formed on a substrate (1), for forming a layer to be formed as an conductive layer (2a) for the thin film transistor by patterning the formed polycrystal silicon film; a second step for doping impurity ions at the layer to be formed as the conductive layer; a third step for cooling the substrate by a cooling mechanism after the second step; and a fourth step for forming a source region (4a.sub.1) and a drain region (4a.sub.2) in the conductive layer, respectively by repeating the second and third steps. By this method, impurities can be doped at microscopic regions, and further the highest possible throughput can be obtained.

Abstract: A method for manufacturing integrated circuit semiconductor device is provided for doping polysilicon formed on an N-well in a semiconductor substrate. Form a silicon oxide layer on the N-well. Then form a blanket polysilicon layer over the silicon oxide layer and pattern the polysilicon layer into a structure. Form a sacrificial oxide layer over the polysilicon structure. Then ion implant .sup.49 (BF.sub.2).sup.+ ions into the N-well and the polysilicon layer forming the source/drain regions and doping the polysilicon layer with P-type dopant thereby forming a doped polysilicon layer from the polysilicon layer. Then etch the sacrificial oxide layer away from the device. Form a polyoxide layer over the polysilicon structure. Then form a silicon oxide layer over the polyoxide layer followed by forming a glass layer thereover.

Abstract: First and second conductivity type regions are produced in a polysilicon layer using only a single masking step. In one embodiment, the polysilicon layer is doped to a first conductivity type. A first oxide layer is then formed and patterned over the polysilicon layer to cover a first region and expose a second region of the polysilicon layer. The exposed second region of the polysilicon layer is then counter-doped, with the first oxide layer acting as a mask to prevent counter-doping of the underlying first region of the polysilicon layer. In accordance with the present invention, n-channel devices with n-type or p-type polysilicon gates and p-channel devices with p-type or n-type polysilicon gates can be formed without having to add a single process step. Thus, n-channel and p-channel devices with two different threshold voltages can be realized without adding a single process step.

Abstract: A method and apparatus of forming local interconnects in a MOS process deposits a layer of polysilicon over an entire region after several conventional MOS processing steps. The region is then masked to provide protected regions and unprotected regions. The mask may be used to define local interconnects and other conductive elements such as the source and drain contact regions for a MOS transistor. After masking, the region is bombarded with atoms to enhance the oxidation potential of the unprotected regions. The masking is removed and the substrate is then exposed to oxidizing conditions which cause the unprotected regions to rapidly oxidize to form a thick oxide layer. The formerly protected polysilicon regions may then be doped to render them conductive.

Abstract: The present invention is a method of manufacturing a high/low resistance on a mix-mode product. The method includes forming a polysilicon layer over a wafer. A blanket ion implantation is performed to implant ions into the entire polysilicon layer. The polysilicon layer is then separated into a high resistance area and a low resistance area. The low resistance area top surface is raised higher than the high resistance area. A photoresist is then formed on the polysilicon areas. The photoresist is subsequently etched back to the top surface of the low resistance areas. A second implant is done on the low resistance area.

Abstract: A semiconductor device on a semiconductor wafer, wherein improvements are realized to agglomeration control, resistivity, and thermal stability of a titanium disilicide layer on a polysilicon layer. Agglomeration control is achieved through the use of two carefully selected low dose barrier diffusion matrix implants into the polysilicon layer, one of which is situated at an interface between the layer of polysilicon and the resultant layer of titanium disilicide film after heat treatment, and the other of which is near the surface of the resultant layer of titanium disilicide film after heat treatment.

Abstract: A semiconductor device (10) is formed in a semiconductor substrate (11) that acts as a collector region. A base region (12) is formed in the semiconductor substrate (11) and an emitter region (52) is formed such that it contacts at least a portion of the base region (12). A conductive layer (28) is used to provide electrical connection to the emitter region (52). The portion of the conductive layer (28) above the emitter region (52) is counter-doped to address the problems of an interfacial oxide layer (27) that exists between the emitter region (52) and the conductive layer (28).

Abstract: A method for making low sheet resistance sub-quarter-micrometer gate electrode lengths on field effect transistors has been achieved. The method involves patterning gate electrodes on a silicon substrate from a conductively doped polysilicon layer having a silicon nitride layer on the surface. After forming the FET lightly doped drains (LDD), the sidewall spacers, and the heavily doped source/drain contact regions with titanium contacts, an insulating layer is chemically/mechanically polished back to the silicon nitride or silicon oxynitride on the gate electrode layer to form a planar self-aligning mask. A pre-amorphizing implantation is carried out, and a titanium silicide is selectively formed on the gate electrodes resulting in small grain sizes and much reduced sheet resistance. The self-aligned mask prevents ion implant damage to the shallow source/drain regions adjacent to the FET gate electrodes.

Abstract: A process for fabricating an MOS device (44) having a segmented channel region (48) includes the fabrication of a compound MOS gate electrode (46). Both the segmented channel region (48) and the MOS gate electrode (46) are formed by creating an opening (18) and an insulating layer (16) overlying a first polycrystalline silicon layer (14). The lateral extent of both the MOS gate electrode (46) and a buried junction region (24) formed in the semiconductor substrate (10) are defined by first sidewall spacer (22) and a second sidewall spacer (32) formed adjacent to the first sidewall spacer (22).

Abstract: In a method of fabricating semiconductor devices such as transistors and in the devices formed thereby, a doped polysilicon layer is formed overlying an insulated gate. The doped polysilicon layer extends over the top and the sidewalls of the gate to contact the underlying substrate. The dopants implanted in the polysilicon layer are diffused into the underlying substrate to form the source region in a self-aligned process which requires no extra masking step. The doped polysilicon layer, by contacting the source region and also overlying the gate, allows external electrical contact to be made on the top of the gate to the source regions, eliminating the need for a special source contact adjacent to the gate. This conserves surface area of the device, allowing fabrication of a smaller and hence more economical device.

Abstract: A polysilicon resistor (40) includes a field oxide layer (12) and a polysilicon layer (20) that covers a portion of field oxide layer (12). The polysilicon layer (20) possesses a predetermined electrical resistance value. Nitride/oxide stack (42) covers a predetermined portion of the polysilicon layer (20) and forms at least one exposed location of polysilicon layer (20) on which not to implant a dopant to achieve a predetermined resistance value. Silicide layer (34) covers exposed location.

Abstract: A heterojunction bipolar transistor in an integrated circuit has intrinsic and extrinsic base portions. The intrinsic base portion substantially comprises epitaxial silicon-germanium alloy. The extrinsic base portion substantially comprises polycrystalline material, and contains a distribution of ion-implanted impurities. An emitter overlies the intrinsic base portion, and a spacer at least partially overlies the emitter. The spacer overhangs the extrinsic base portion by at least a distance characteristic of lateral straggle of the ion-implanted impurities.