Abstract: P-type and n-type regions are defined in the first surface of a substrate upon which is formed an epitaxial layer of preferably Si—Ge material, preferably capped by Si material. During epitaxy formation, dopant in the defined regions diffuses down to form p-type and n-type junctions in the Si material, and diffuses up to form p-type and n-type junctions in the Si—Ge epitaxial material. Si junctions are buried beneath the surface and are surface recombination velocity effects are reduced. Photon energy striking the second substrate surface generates electron-hole pairs that experience the high bandgap of the Si materials and the low bandgap of the Si—Ge epitaxy. The tandem structure absorbs photon energy from about 0.6 eV to about 3.5 eV and exhibits high conversion efficiency.

Abstract: A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enclosed elemental dopant source which is within a secondary vacuum enclosure. A quantity of the elemental dopant atoms having thermal velocities are deposited onto a surface of the wafer, and the wafer is heated for diffusing the elemental dopant into the wafer. In one embodiment, the heating is conducted by heating the wafer in ultra-high vacuum for diffusing the portion of the doping atoms into the wafer, and the deposition and heating occur simultaneously. In another embodiment, the surface of the wafer is hydrogen terminated, the wafer is removed from the UHV system, and the heating of the wafer is conducted outside of the UHV system by heating the wafer in a furnace.

Abstract: In order to manufacture components of a semiconductor structure, a buffer layer is epitaxially grown onto a well in a substrate. This buffer layer is subsequently removed in the region outside the wells. This measure reduces edge losses because of the conductive, autodoped layer along the boundary area of the substrate with respect to a following epitaxial layer. The components are suitable for high frequency applications.

Abstract: Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

Abstract: Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and the dopant is diffused through those layers. The polysilicon provides sacrificial silicon that serves to prevent the formation of boron silicon nitride on the substrate surface and also protects the oxide layer during etching of the silicon glass layer. The oxide layer then acts as an etch stop during removal of the polysilicon layer. In this way, no damage done to the substrate surface during the diffusion or subsequent etch steps and the need for expensive ion implanter steps is avoided.

Abstract: An avalanche photodiode fabricating method with a simplified fabrication process and an improved reproducibility is disclosed.

Abstract: A semiconductor device which can reduce contact resistance, is disclosed. A semiconductor device according to the present invention includes a lower conductor pattern and an upper conductor pattern. The lower conductor pattern is in contact with the upper conductor pattern. The lower conductor pattern includes a first doped polysilicon layer, a first tungsten silicide layer and a cap layer formed sequentially. Here, the cap layer is formed to a doped polysilicon layer containing a small amount of tungsten and has stoichiometrical equivalent ratio x of Si higher than the first tungsten silicide layer. The upper conductor pattern includes a second doped polysilicon layer and a second tungsten layer formed sequentially. The contact of lower conductor pattern and the upper conductor pattern is substantially formed between the cap layer and the second doped polysilicon layer. Preferably, stoichiometrical equivalent ratio x of Si for the first tungsten silicide layer is 2.3 to 2.

Abstract: A method for doping one side of a semiconductor substrate, such as in a silicon wafer, wherein an oxide layer is deposited on both the side to be doped and the non-doped side of the semiconductor substrate. A doping layer, containing a doping agent, is deposited onto the oxide layer on the side to be doped. The doping agent passes through the oxide layer on the side to be doped and into the semiconductor substrate. The oxide layer on the non-doped side serves as a protective layer, preventing diffusion of the doping agent into the undoped side of the substrate.

Abstract: High integrity cobalt silicide contacts are formed with shallow source/drain junctions. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, followed by silicidation and diffusing impurities from a doped film during or after silicidation in an environment which discourages out-diffusion of the impurities to the environment. The resulting source/drain junctions are self-aligned to the cobalt silicide/silicon substrate interface, thereby preventing junction leakage while advantageously enabling forming the cobalt silicide contacts at optimum thickness to avoid parasitic series resistances. The formation of self-aligned source/drain junctions to the cobalt silicide/silicon substrate interface facilitates reliable device scaling, while the avoidance of unwanted diffusion of impurities to the environment assures adequate doping of the source/drain regions.

Abstract: This invention relates to a method for the heat treatment of a ZnSe crystal substrate to dope it with Al as a donor impurity, a ZnSe crystal substrate prepared by this heat treatment and a light-emitting device using the ZnSe crystal substrate, in particular, the method for the heat treatment of a ZnSe crystal substrate comprising previously forming an Al film on the substrate, first subjecting the substrate to a heat treatment in a Se atmosphere and then subjecting to a heat treatment in a Zn atmosphere.

Abstract: An opto-electronic device has a diffusion area of one conductive type formed in a semiconductor substrate of another conductive type, an ohmic contact layer making contact with the diffusion area, and an electrode making contact with the ohmic contact layer. The diffusion area is formed by solid-phase diffusion. The same mask is used to define the patterns of both the diffusion source layer and the ohmic contact layer, so that the ohmic contact layer is self-aligned with the diffusion area.

Abstract: Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement.

Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.

Abstract: High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. These are formed by depositing a layer of cobalt on a substrate above intended source/drain regions, and depositing a doped amorphous silicon film on the cobalt. Silicidation, as by rapid thermal annealing, is performed to form a low-resistance cobalt suicide while consuming the amorphous silicon film and diffusing impurities from the doped amorphous silicon film through the cobalt silicide into the substrate. The diffusion of the impurities forms shallow junctions extending into the substrate a substantially constant depth below the cobalt silicide/silicon substrate interface.

Abstract: A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

Abstract: Doped semiconductor with high dopant concentrations in small semiconductor regions without excess spreading of the doped region are formed by:(a) applying a dopant-containing oxide glass layer on the semiconductor surface,(b) capping the dopant-containing oxide glass layer with a conformal silicon oxide layer,(c) heating the substrate from step (b) in a non-oxidizing atmosphere whereby at least a portion of the dopant in the glass diffuses into the substrate at the semiconductor surface, and(d) heating the glass-coated substrate from step (c) in an oxidizing atmosphere whereby at least a portion of the dopant in the glass near the semiconductor surface is forced into the substrate at the semiconductor surface by diffusion of oxygen through the glass.The method is especially useful for making buried plates in semiconductor substrates which may be used in trench capacitor structures. The preferred semiconductor substrate material is monocrystalline silicon. The preferred dopant is arsenic.

Abstract: The present invention discloses a method of doping and preventing silicide formation in selective areas of a polysilicon gate in MOS, PMOS, NMOS or CMOS manufacturing technologies. The process includes the steps of: depositing a non-conformal dopant containing layer on the top surface of the body and the top surface of the polysilicon gate; removing a portion of the non-conformal dopant containing layer to expose the top surface of the polysilicon gate; and heating to diffuse dopant from the dopant containing layer. Silicidation is then provided by depositing a metal layer and annealing the metal layer. As a first alternative method, the heating and removing step may be reversed. As a second alternative method, after removal of the non-conformal layer, a metal layer can be deposited followed by a combination anneal of the metal layer and non-conformal dopant containing layer.

Abstract: A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region immediately adjacent to the gate and a more heavily doped main portion of the source and drain region spaced apart from the gate. A first layer of glass (2% BSG) is used to provide the source of doping for the tip region and a second layer of glass (6% BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers are formed between the glass layers to define the tip region from the main portion of the source and drain regions.

Abstract: A method for forming a flash memory cell structure comprising the steps of providing a semiconductor substrate, and then sequentially forming a bottom conductive layer and a cap oxide layer over the substrate. Next, a pattern is defined in the conductive layer and the cap oxide layer. Subsequently, a thermal oxidation method is used to form a silicon oxide layer on the sidewalls of the bottom conductive layer. Then, a gate oxide layer is formed between the bottom conductive layers above the substrate. Thereafter, source/drain regions are formed in the semiconductor substrate. Then, spacer structures are formed adjacent to the silicon oxide layers. Using the spacer structures as masks, a portion of the gate oxide layer is etched. Then, the spacer structures are removed to expose the gate oxide layer. Next, a thermal oxidation method is used to form a tunneling oxide layer in the narrow region between the gate oxide layer. The tunneling oxide layer has a long narrow top profile.

Abstract: A partially ionized beam (PIB) deposition technique is used to heteroepitally deposit a thin film of CoGe.sub.2 (001) on GaAs (100) substrates 14. The resulting epitaxial arrangement is CoGe.sub.2 (001) GaAs (100). The best epitaxial layer is obtained with an ion energy 1100 eV to 1200 eV and with a substrate temperature of approximately 280.degree. Centigrade. The substrate wafers are treated only by immersion in HF:H.sub.2 O 1:10 immediately prior to deposition of the epitaxial layer. Contacts grown at these optimal conditions display ohmic behavior, while contacts grown at higher or lower substrate temperatures exhibit rectifying behavior. Epitaxial formation of a high melting point, low resistivity cobalt germanide phase results in the formation of a stable contact to n-GaAs.

Abstract: A method of manufacturing a field effect transistor according to the present invention is disclosed including the steps of preparing a semiconductor substrate; forming an insulating film for use as high concentration on the semiconductor substrate; forming an insulating film for use as low concentration on the insulating film for use as high concentration; performing a heat treatment on the insulating films to thereby diffuse impurities; forming high concentration regions and low concentration region in the surface of the semiconductor substrate; forming mesa and electrodes on the upper surface and side of the semiconductor substrate; and selectively etching the insulating film for use as low concentration so as to expose a predetermined portion of the upper surface of the semiconductor substrate, to thereby form a gate electrode so as to be in contact with the low concentration region of the predetermined portion.

Abstract: A P-type substrate for infrared photo diodes can be produced by the present invention. A CdZnTe substrate is utilized. A first layer of HgCdTe is formed by liquid phase epitaxy on the substrate. A CdTe passivation layer is formed over the HgCdTe. A ZnS layer is formed over the CdTe layer. A noble metal is introduced into either the CdTe or ZnS layers. During a subsequent baking of the composite, the noble metal diffuses throughout the composite and into the HgCdTe layer.

Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

Abstract: A semiconductor processing method of providing a polysilicon layer atop a semiconductor wafer comprises the following sequential steps: a) depositing a first layer of arsenic atop a semiconductor wafer; b) depositing a second layer of silicon over the arsenic layer, the second layer having an outer surface; c) first annealing the wafer at a temperature of at least about 600.degree. C. for a time period sufficient to impart growth of polycrystalline silicon grains in the second layer and providing a predominately polysilicon second layer, the first annealing step imparting diffusion of arsenic within the second layer to promote growth of large polysilicon grains; and d) with the second layer outer surface being outwardly exposed, second annealing the wafer at a temperature effectively higher than the first annealing temperature for a time period sufficient to outgas arsenic from the polysilicon layer.

Abstract: Methods for defect-free impurity-induced laser disordering (IILD) of AlGaInP and AlGaAs heterostructures. Phosphorus-doped or As-doped films are used in which silicon serves as a diffusion source and silicon nitride acts as a barrier for selective IILD. High-performance, index-guided (AlGa).sub.0.5 In.sub.0.5 P lasers may be fabricated with this technique, analogous to those made in the AlGaAs material system. The deposition of the diffusion source films preferably is carried out in a low pressure reactor. Also disclosed is a scheme for reducing or eliminating phosphorus overpressure during silicon diffusion into III-V semiconducting material by adding a pre-diffusion anneal step. Defects produced during intermixing are also reduced using a GaInP or GaInP/GaAs cap.