Abstract: The impurity diffusion method includes: transferring an object on which the thin film is formed into a processing chamber (operation 1); raising a temperature of the object to a vapor diffusion temperature in the processing chamber (operation 3); and supplying an impurity-containing gas that contains the impurities into the processing chamber, together with an inert gas and diffusing the impurities in the thin film formed on the object of which the temperature is raised to the vapor diffusion temperature (operation 4), wherein in the operation 4, an impurity diffusion acceleration gas for accelerating the diffusion of the impurities into the thin film is supplied into the processing chamber, together with the impurity-containing gas and the inert gas.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an active region formed to be sloped or tilted by ?° (where 0°<?°<90°) from the bottom of a semiconductor substrate, at least one gate that is formed over the sloped active region and has a surface parallel to the bottom of the semiconductor substrate, and a landing plug that is coupled to the active region and is located between the gates. As a result, the area of the active region is increased thus increasing a channel width, so that the operation of the semiconductor device can be improved as the integration degree of the semiconductor device is rapidly increased.

Abstract: According to one embodiment, in a method for manufacturing a semiconductor device, a surface region of a semiconductor substrate is modified into an amorphous layer. A microwave is irradiated to the semiconductor substrate in which the amorphous layer is formed in a dopant-containing gas atmosphere so as to form a diffusion layer in the semiconductor substrate. The dopant is diffused into the amorphous layer and is activated.

Abstract: A method of manufacturing a power semiconductor device is provided. A first oxide layer is produced on a first main side of a substrate of a first conductivity type. A structured gate electrode layer with at least one opening is then formed on the first main side on top of the first oxide layer. A first dopant of the first conductivity type is implanted into the substrate on the first main side using the structured gate electrode layer as a mask, and the first dopant is diffused into the substrate. A second dopant of a second conductivity type is then implanted into the substrate on the first main side, and the second dopant is diffused into the substrate. After diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, the first oxide layer is partially removed. The structured gate electrode layer can be used as a mask for implanting the second dopant.

Abstract: A film formation apparatus for a semiconductor process includes a source gas supply circuit to supply into a process container a source gas for depositing a thin film on target substrates, and a mixture gas supply circuit to supply into the process container a mixture gas containing a doping gas for doping the thin film with an impurity and a dilution gas for diluting the doping gas. The mixture gas supply circuit includes a gas mixture tank disposed outside the process container to mix the doping gas with the dilution gas to form the mixture gas, a mixture gas supply line to supply the mixture gas from the gas mixture tank into the process container, a doping gas supply circuit to supply the doping gas into the gas mixture tank, and a dilution gas supply circuit to supply the dilution gas into the gas mixture tank.

Abstract: It is to provide a vapor phase growth method in which an epitaxial layer consisting of a compound semiconductor such as InAlAs, can be grown, with superior reproducibility, on a semiconductor substrate such as Fe-doped InP. In vapor phase growth method for growing an epitaxial layer on a semiconductor substrate, a resistivity of the semiconductor substrate at a room temperature is previously measured, a set temperature of the substrate is controlled depending on the resistivity at the room temperature such that a surface temperature of the substrate is a desired temperature regardless of the resistivity of the semiconductor substrate, and the epitaxial layer is grown.

Abstract: A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided.

Abstract: A boron phosphide-based semiconductor device includes a single crystal substrate having formed thereon a boron-phosphide (BP)-based semiconductor layer containing boron and phosphorus as constituent elements, where phosphorus (P) occupying the vacant lattice point (vacancy) of boron (B) and boron occupying the vacant lattice point (vacancy) of phosphorus are present in the boron-phosphide (BP)-based semiconductor layer. The boron phosphide-based semiconductor device includes a p-type boron phosphide-based semiconductor layer in which boron occupying the vacancy of phosphorus is contained in a higher atomic concentration than phosphorus occupying the vacancy of boron and a p-type impurity of Group II element or Group I V element is added.

Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate; step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate, the dopant from said solids-based dopant source diffusing directly into said substrate to form a first diffusion region and, at the same time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate to form a second diffusion region in at least some areas of said substrate to form a second diffusion region in at least some areas of said substrate not covered by said pattern; and step 3) forming a metal contact pattern substantially in alignment with

Abstract: A method of fabricating a semiconductor device having an L-shaped spacer is provided. A buffer dielectric layer, a first dielectric layer, and a second dielectric layer are sequentially formed on the surface of the gate electrode and on the semiconductor substrate. Next, the second dielectric layer is etched to form a first disposable spacer on the first dielectric layer at both sidewalls of the gate electrode. Next, a deeply doped source and drain region is formed on the semiconductor substrate to be aligned to the first disposable spacer. Next, the first disposable spacer and the first dielectric layer are sequentially removed. Next, a shallowly doped source and drain region is formed on the semiconductor substrate at both sidewalls of the gate electrode adjacent to the deeply doped source and drain region. Next, a third dielectric layer, a fourth dielectric layer, and a fifth dielectric layer are sequentially formed on the buffer dielectric layer.

Abstract: In a method of manufacturing a semiconductor integrated circuit device in which a lower electrode of a capacitor is composed of a polycrystalline silicon film having a surface area increased by surface roughening, an impurity is introduced into the polycrystalline silicon film by vapor phase diffusion in order to reduce the resistance of the lower electrode.

Abstract: An LPE (Liquid Phase Epitaxy) apparatus is diverted to a Zn-diffusion apparatus for diffusing Zn into III-V group compound semiconductor. The Zn-diffusion apparatus comprises a base plank extending in a direction, having a wafer-storing cavity for storing an object wafer and an exhaustion hole for exhaling gases, a slider having a frame and a cap plate for attaching to or detaching from the frame, the frame having serially aligning M rooms with an open bottom and a rack being separated from each other by (M−1) partition walls, a manipulating bar for sliding the slider upon the base plank forward or backward in the direction, a tube for enclosing the base plank and the slider and for being capable of being made vacuous, a heater surrounding the tube for heating the slider, each rack of the rooms being allocated with a Zn-diffusion material and a V element material (or a non-doped capping wafer) in turn for aligning the rooms into repetitions of a V element room and a diffusion room.

Abstract: A method is described for safe gas phase doping a semiconductor with arsenic. The substrate including a semiconductor structure is exposed to arsine at elevated temperatures within a reaction chamber. Thereafter, prior to opening the reaction chamber, a sealant layer is formed over the semiconductor structure. The sealant layer inhibits outdiffusion of arsenic when the substrate is unloaded from the reaction chamber, enabling safe unloading at relatively high temperatures. In the illustrated embodiments, the sealant layer can be formed by oxidation, nitridation or chemical vapor deposition. Forming the sealant layer can be conducted prior to, during or after cooling the substrate to an unloading temperature. Preferably, a gettering step is conducted after gas phase doping and prior to forming the sealant layer, such as by exposing the substrate to HCl vapor.

Abstract: An LPE (Liquid Phase Epitaxy) apparatus is diverted to a Zn-diffusion apparatus for diffusing Zn into III-V group compound semiconductor. The Zn-diffusion apparatus comprises a base plank extending in a direction, having a wafer-storing cavity for storing an object wafer and an exhaustion hole for exhaling gases, a slider having a frame and a cap plate for attaching to or detaching from the frame, the frame having serially aligning M rooms with an open bottom and a rack being separated from each other by (M−1) partition walls, a manipulating bar for sliding the slider upon the base plank forward or backward in the direction, a tube for enclosing the base plank and the slider and for being capable of being made vacuous, a heater surrounding the tube for heating the slider, each rack of the rooms being allocated with a Zn-diffusion material and a V element material (or a non-doped capping wafer) in turn for aligning the rooms into repetitions of a V element room and a diffusion room.

Abstract: A method of forming a retrograde channel concentration profile in the NMOS region of a semiconductor device and forming a shallow LDD regions in a PMOS region of the semiconductor device. The retrograde channel concentration profile in the NMOS regions is formed by implanting nitrogen and boron ions into the NMOS region at selected concentrations and implantation energy levels. The nitrogen ions are implanted in the NMOS region at a selected concentration in the range of 1×1013 to 2×1015 ions per cm2 and at a selected implantation energy in the range of 10-100 KeV. The boron ions are implanted in the NMOS region at a selected concentration in the range of 1×1012 to 1×1014 ions per cm2 and at a selected implantation energy in the range of 5-50 KeV. The shallow LDD regions in the PMOS region are formed by implanting nitrogen and boron ions into the PMOS region at selected concentrations and implantation energy levels.

Abstract: A direct doping method for semiconductor wafers, comprising the steps of providing a semiconductor wafer, exposing the surface of the wafer to a process medium in order to directly dope at least a portion of the surface of the wafer, wherein the process medium comprises a dopant gas, and wherein the dopant gas comprises an organic compound of a dopant species, and heating the wafer, thermally activating the direct doping process and causing solid-state diffusion of the dopant species into the semiconductor wafer surface. The organic source of a dopant species includes the organic compounds comprising boron, arsenic and phosphorous. The wafer is heated in the presence of an organic dopant source, thermally activating the doping process and causing surface chemisorption, surface dissociation, and solid-state diffusion of the dopant species into the wafer surface. The organic dopant source can be used with a germanium-containing additive gas, a halogen-containing compound or a remote plasma energy source.

Abstract: In a method of introducing phosphorous from phosphorous oxychloride (POCl.sub.3) into an undoped gate polysilicon region formed as part of an integrated circuit structure, an initial MOS structure is developed utilizing conventional techniques through the formation of a layer of undoped polysilicon over thin gate oxide. A POCl.sub.3 layer is then formed over the undoped polysilicon and thermally annealed to drive phosphorous into the gate polysilicon to achieve a desired conductivity level. The phosphorous-rich organic layer is then cleaned from the surface of the POCl.sub.3 using sulfuric peroxide and the POCl.sub.3 layer is removed using a DI:HF solution to expose the surface of the doped polysilicon. After formation of a photoresist gate mask, arsenic, or another heavy ion species, is implanted into the exposed polysilicon to amorphized the exposed poly, thereby eliminating the polysilicon grain boundaries.