Abstract: An embedded flash memory device and a method for fabricating the same which reduces the size of a memory device using logic CMOS fabricating processes and enhancing a coupling ratio of the memory device. The flash memory device includes a coupling oxide layer on an active area of a semiconductor substrate, a first control gate formed on and/or over the coupling oxide layer and a second control gate formed on and/or over and enclosing lateral sidewalls of the coupling oxide layer and the first control gate.

Abstract: A flash memory device and method of fabricating thereof. In accordance with the method of the invention, a tunnel dielectric layer and an amorphous first conductive layer are formed over a semiconductor substrate. An annealing process to change the amorphous first conductive layer to a crystallized first conductive layer is performed. A second conductive layer is formed on the crystallized first conductive layer. A first etch process to pattern the second conductive layer is performed. A second etch process to remove an oxide layer on the crystallized first conductive layer is performed. A third etch process to pattern the amorphous first conductive layer is performed.

Abstract: Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.

Abstract: In a nonvolatile semiconductor memory device having a plurality of nonvolatile memory cells integrated on a semiconductor substrate, each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, a first interelectrode insulating film formed on the upper surface of the floating gate electrode, a second interelectrode insulating film formed to cover the side surfaces of the floating gate electrode and the first interelectrode insulating film, and a control gate electrode formed on the second interelectrode insulating film.

Abstract: A method of forming gate patterns of a nonvolatile memory device comprises forming stack patterns each having an insulating layer and a conductive layer stacked over a semiconductor substrate, and forming an anti-oxidation layer on sidewalls of the insulating layer by selectively nitrifying the insulating layer.

Abstract: The present invention discloses a tunnel insulating layer in a flash memory device and a method of forming the same, the method according to the present invention comprises the steps of forming a first oxide layer on a semiconductor substrate through a first oxidation process; forming a nitride layer on an interface between the semiconductor substrate and the first oxide layer through a first nitridation process; forming a second nitride layer on the first oxide layer through a second nitridation process; forming a second oxide layer on the second nitride layer through a second oxidation process; and forming a third nitride layer on the second oxide layer through a third nitridation process.

Abstract: A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

Abstract: A plasma oxidation processing method is performed, on a structural object including a silicon layer and a refractory metal-containing layer, to form a silicon oxide film. A first plasma oxidation process is performed by use of a process gas including at least hydrogen gas and oxygen gas and a process pressure of 1.33 to 66.67 Pa. A second plasma oxidation process is performed by use of a process gas including at least hydrogen gas and oxygen gas and a process pressure of 133.3 to 1,333 Pa, after the first plasma oxidation process.

Abstract: A structure of a non-volatile memory is described, including a substrate, isolation structures disposed in and protrudent over the substrate, floating gates as conductive spacers on the sidewalls of the isolation structures protrudent over the substrate, and a tunneling layer between each floating gate and the substrate. A process for fabricating a non-volatile memory is also described. Isolation structures are formed in a substrate protrudent over the same, a tunneling layer is formed over the substrate, and then floating gates are formed as conductive spacers on the sidewalls of the first isolation structures protrudent over the substrate.

Abstract: A method of manufacturing a semiconductor device, includes 5 steps. The first step is a step of forming a floating gate on a first surface region of a semiconductor substrate through a gate insulating film. The second step is a step of forming a tunnel insulating film so as to cover a second surface region adjacent to the first surface region and an end portion of the floating gate. The third step is a step of forming an oxide film so as to cover the tunnel insulating film and be thicker at a portion above the second surface region than at a portion above the floating gate. The fourth step is a step of etching back the oxide film and a surface of the tunnel insulating film on the floating gate. The fifth step is a step of forming a control gate on the tunnel insulating film on the second surface region.

Abstract: The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

Abstract: Disclosed is a method for fabricating a nonvolatile memory device having a stacked gate structure in which a floating gate, a charge blocking layer, and a control gate are sequentially stacked. The method includes forming a first conductive layer for floating gate over a substrate; forming a charge blocking layer and a second conductive layer for control gate over a resulting structure including the first conductive layer; forming an etch mask pattern over the second conductive layer; performing a primary etch process on the second conductive layer until the charge blocking layer is exposed; forming a passivation layer on a sidewall of the second conductive layer exposed by the primary etch process; and performing a secondary etch process on the charge blocking layer and the first conductive layer.

Abstract: A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacture process of high-integrated semiconductor devices. It is therefore possible to minimize an interference phenomenon between neighboring cells. Furthermore, an isolation film is etched after a photoresist film covering only a high-voltage transistor region is formed, or a gate oxide film is formed after a semiconductor substrate is etched at a thickness, which is the same as that of the gate oxide film of the high-voltage transistor region, so that a step between the cell region and the high-voltage transistor region is the same. Accordingly, the coupling ratio can be increased even by the gate oxide film of the high-voltage transistor region, which is thicker than the tunnel oxide film of the cell region.

Abstract: A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment.

Abstract: In a nonvolatile semiconductor memory device provided with memory cell transistors, each of the memory cell transistors has a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and element isolation insulating films respectively. The floating gate electrode on the tunnel insulating film is provided with a first floating gate electrode and a second floating gate electrode formed sequentially from the bottom, the second floating gate electrode being narrower in a channel-width direction than the first one. Levels of upper surfaces of the element isolation insulating films and the first floating gate electrode are the same. The inter-electrode insulating film continuously covers the upper and side surfaces of the floating gate electrode and the upper surfaces of the element isolation insulating films, and is higher in a nitrogen concentration in a boundary portion to the floating gate electrode than in boundary portions to the element isolation insulating films.

Abstract: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.

Abstract: Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.

Abstract: There is provided a method of manufacturing a semiconductor memory device. According to the method, a tunnel insulating layer and a charge trap layer are formed in a cell region of a semiconductor substrate defining the cell region and a peripheral region. A gate insulation layer and a first conductive layer are formed over the semiconductor substrate of the peripheral region. A blocking insulating layer is formed on the charge trap layer of the cell region and the first conductive layer of the peripheral region. A second conductive layer is formed over the entire surface including the blocking insulating layer, thereby forming a capacitor having a stack structure of the first conductive layer, the blocking insulating layer, and the second conductive layer.

Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

Abstract: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first polysilicon pattern formed on a semiconductor substrate, a second polysilicon pattern formed at a lateral side of the first polysilicon pattern such that the second polysilicon pattern extends to a height higher than the first polysilicon pattern, a third polysilicon pattern formed in a region restricted by a top surface of the first polysilicon pattern and a lateral side of the second polysilicon pattern, and a contact electrically connected with the second polysilicon pattern and the third polysilicon pattern.

Abstract: There is provided a nonvolatile memory device having a tunnel dielectric layer formed over a substrate, the charge capturing layer formed over the tunnel dielectric layer and including a combination of at least one charge storage layer and at least one charge trap layer, a charge blocking layer formed over the charge capturing layer, and a gate electrode formed over the charge blocking layer.

Abstract: A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the channel; arranging a charge storage region adjacent to the first insulator layer; arranging a second insulator layer adjacent to the charge storage region; arranging a first conductive region adjacent to the second insulator layer; arranging a filter adjacent to the first conductive region; and arranging a second conductive region adjacent to the filter. The second conductive region overlaps the first conductive region at an overlap surface. A line perpendicular to the overlap surface intersects at least a portion of the charge storage region.

Abstract: A method of manufacturing a memory cell 200. The method comprises forming a memory stack 215. Forming the memory stack includes pre-treating an insulating layer 210 in a substantially ammonia atmosphere for a period of more than 5 minutes to thereby form a pre-treated insulating layer 310. Forming the memory stack also includes depositing a silicon nitride layer on the pre-treated insulating layer.

Abstract: Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed.

Abstract: A non-volatile memory of a semiconductor device has a tunnel insulation film provided on the active area; a floating gate electrode provided on the tunnel insulation film; a control gate electrode provided over the floating gate electrode; and an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode, wherein, in a section of the non-volatile memory cell in a channel width direction, a dimension of a top face of the active area in the channel width direction is equal to or less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction.

Abstract: The semiconductor device includes a semiconductor substrate, a gate insulating film formed in contact with an upper side of the semiconductor substrate, and a gate electrode formed on the upper side of the gate insulating film and made of metal nitride or metal nitride silicide. A buffer layer for preventing diffusion of nitrogen and silicon is interposed between the gate insulating film and the gate electrode. Preferably, the buffer layer has a thickness of 5 nm or less. In the case where gate electrode contains Ti elements, and the gate insulating film contains Hf elements, the buffer layer preferably contains a titanium film.

Abstract: A method of forming a gate pattern of a flash memory device may include forming a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, a metal electrode layer, and a hard mask film over a semiconductor substrate. The metal electrode layer may be etched such that a positive slope of an upper sidewall may be formed larger than a positive slope of a lower sidewall of the metal electrode layer. The conductive layer for the control gate, the dielectric layer, and the conductive layer for the floating gate may then be etched. High molecular weight argon gas, for example, may be used to improve an anisotropic etch characteristic of plasma. Over etch of a metal electrode layer may be decreased to reduce a bowing profile. Resistance of word lines can be decreased and electrical properties can be improved.

Abstract: Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed.

Abstract: This disclosure concerns a manufacturing method of a semiconductor device comprising an etching process using an etching solution having ozone dissolved by 10 ppm or more into a liquid containing H2SO4 by 86 wt % to 97.9 wt %, HF by 0.1 wt % to 10 wt %, and H2O by 2 wt % to 4 wt %.

Abstract: A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

Abstract: A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.

Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Abstract: In semiconductor devices and methods of manufacturing semiconductor devices, a zirconium source having zirconium, carbon and nitrogen is provided onto a substrate to form an adsorption layer of the zirconium source on the substrate. A first purging process is performed to remove a non-adsorbed portion of the zirconium source. An oxidizing gas is provided onto the adsorption layer to form an oxidized adsorption layer of the zirconium source on the substrate. A second purging process is performed to remove a non-reacted portion of the oxidizing gas. A nitriding gas is provided on the oxidized adsorption layer to form a zirconium carbo-oxynitride layer on the substrate, and a third purging process is provided to remove a non-reacted portion of the nitriding gas.

Abstract: A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor type may comprise a NAND comprising tunnel oxide and having a narrow active area and/or short gate length. The transistors are exposed to a nitridation ambient. Various process embodiments and completed structures are disclosed.

Abstract: A semiconductor storage device according to the present invention includes: a semiconductor substrate; an embedded insulator embedded in a trench formed in the semiconductor substrate and having an upper portion protruding above a top surface of the semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a floating gate formed on the first insulating film at a side of the embedded insulator, having a side portion arching out above the embedded insulator, and having a side surface made of a flat surface and a curved surface continuing below the flat surface; a second insulating film contacting an upper surface, the flat surface and the curved surface of the floating gate; and a control gate opposing the upper surface, the flat surface and the curved surface of the floating gate across the second insulating film.

Abstract: A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.

Abstract: A technique to form metallic nanodots in a two-step process involving: (1) reacting a silicon-containing gas precursor (e.g., silane) to form silicon nuclei over a dielectric film layer; and (2) using a metal precursor to form metal nanodots where the metal nanodots use the silicon nuclei from step (1) as nucleation points. Thus, the original silicon nuclei are a core material for a later metallic encapsulation step. Metallic nanodots have applications in devices such as flash memory transistors.

Abstract: A method of forming a semiconductor device includes forming a trench on a semiconductor substrate to define an active region, forming a radical oxide layer on a sidewall and a bottom surface of the trench, and forming a nitride layer on the radical oxide layer. The conduction band offset of the radical oxide layer is greater than the conduction band offset of a thermal oxide layer having the same thickness as the radical oxide layer.

Abstract: The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.

Abstract: A nonvolatile memory cell has charge trapping dielectric (160) which has been modified (i.e. oxidized) adjacent to edges of blocking dielectric (180). The modification reduces the charge-trapping density adjacent to the edges of the blocking dielectric, and hence reduces the leakage current at the edges. Other features are also provided.

Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, forming a diffusion barrier for preventing metal diffusion over the insulation layer, forming a gate electrode layer over the diffusion barrier, forming a metal layer over the gate electrode layer, and performing a thermal treatment process on the substrate structure to form a metal silicide layer having a uniform thickness.

Abstract: A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate.

Abstract: A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semiconductor layer and second semiconductor layer, a first control gate electrode between the first semiconductor layer and the isolation layer, a second control gate electrode between the second semiconductor layer and the isolation layer, wherein the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer, a first charge storing layer between the first control gate electrode and the first semiconductor layer, and a second charge storing layer between the second control gate electrode and the second semiconductor layer.

Abstract: A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.

Abstract: A flash memory device and a method for fabricating the same are provided. The flash memory device includes: an active region having a plurality of surface regions and a plurality of recess regions formed lower than the surface regions; a tunnel oxide layer formed over the recess regions; a plurality of recessed floating gates formed over the tunnel oxide layer to be buried into the recess regions; a plurality of dielectric layers over the recessed floating gates; and a plurality of control gates over the dielectric layers.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming multiple conductive patterns 13a, forming an intermediate insulating film 16 on all of device isolation insulating films 6 and the conductive patterns 13a, forming a second conductive film 17 on the intermediate insulating film 16, patterning the second conductive film 17, the intermediate insulating film 16, and the multiple conductive patterns 13a, individually, to make the conductive patterns 13a into floating gates 13c and to make the second conductive film 17 into multiple strip-like control gates 17a. In the method, an edge, in a plan layout, of at least one of each of the conductive patterns 13a and each of the device isolation insulating films 6 is bent in a region between the control gates 17a adjacent in a row direction.

Abstract: A method of fabricating a non-volatile memory device, wherein a gate insulating layer, a first conductive layer, a tunneling layer, a trap nitride layer, a blocking oxide layer, and a capping layer are sequentially formed over a semiconductor substrate of a peripheral region. A contact region of the capping layer is etched. A spacer is formed on sidewalls of the capping layer. A contact region of the blocking oxide layer is etched by using the spacer as a mask. The spacer is removed while etching a contact region of the trap nitride layer. A contact region of the tunneling layer is etched.