Abstract: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

Abstract: Etchant compositions described herein include etchant compositions for etching a silicon film and may include nitric acid, fluoric acid, phosphoric acid, acetic acid, a nitrogen compound, and water. The nitrogen compound may include fluorine (F), phosphorus (P), and/or carbon (C). Also described are methods of manufacturing an integrated circuit (IC) device. The methods may include providing a structure in which a silicon film doped at a first dopant concentration and an epitaxial film doped at a second dopant concentration are stacked. The second dopant concentration may be different from the first dopant concentration. The silicon film may be selectively etched from the structure by using an etchant composition.

Abstract: An efficient wide bandgap GaN-based LED chip based on a surface plasmon effect and a manufacturing method therefor. The efficient wide bandgap GaN-based LED chip is of a flip-chip structure, and comprises, from bottom to top in sequence, a substrate, a buffer layer, an unintentionally doped GaN layer, an n-GaN layer, a quantum well layer, an electron blocking layer, a p-GaN layer, a metallic reflecting mirror layer, a passivation layer, a p-electrode layer, an n-electrode layer; and a position of a bottom surface of the metallic reflecting mirror layer connected to a surface of the p-GaN layer is provided with a micro-nano composite metal structure. A micro metal structure comprises alternating protrusion portions and recess portions; and a nano metal structure is distributed on an interface of the micro metal structure and the p-GaN layer.

Abstract: Techniques relate to forming a sorting device. A mesh is formed on top of a substrate. Metal assisted chemical etching is performed to remove substrate material of the substrate at locations of the mesh. Pillars are formed in the substrate by removal of the substrate material. The mesh is removed to leave the pillars in a nanopillar array. The pillars in the nanopillar array are designed with a spacing to sort particles of different sizes such that the particles at or above a predetermined dimension are sorted in a first direction and the particles below the predetermined dimension are sorted in a second direction.

Abstract: An etching composition may include a peracetic acid mixture, a fluorine compound, an organic solvent (e.g., acetate-series organic solvent), and water. The etching composition may be used to selectively etch silicon-germanium (SiGe).

Abstract: The present invention discloses a method of manufacturing a shadow mask, wherein hybrid processing is used to form a mask pattern on the shadow mask, the method includes: forming a wet-etched pattern by performing wet etching from above a base; and forming a laser-processed pattern that continues from the wet-etched pattern, by performing laser processing from above the base or from below the base on which the wet-etched pattern is formed. The present invention uses hybrid processing including wet etching and laser processing for manufacturing a shadow mask. The method has an effect on solving the productivity degradation of the conventional laser processing and provides a shadow mask with high quality using wet etching.

Abstract: An etching composition may include a peracetic acid mixture, a fluorine compound, an organic solvent (e.g., acetate-series organic solvent), and water. The etching composition may be used to selectively etch silicon-germanium (SiGe).

Abstract: A system for detecting target elements such as bacteria in a host analyte, comprising a substrate with an ordered array of wells having diameters to fit the size of the targets. The substrate may be a periodic macro-PSi array structure (MPSiAS) illuminated with a broadband source. The reflected light spectrum diffracted from the substrate is optically analyzed to provide the effective optical depth of the wells. Fast Fourier Transform analysis may be used for the optical analysis. Entry of target elements into wells is detected by the change in the effective optical depths of the wells. Micro-organisms as large as bacteria and viruses having dimensions comparable with the wavelength of the illumination can thus be detected. Wells with an inner section impenetrable by the target cells enables compensation for environmental changes. The detection may be performed in real time, such that production line bacterial monitoring may be achieved.

Abstract: Disclosed are a method of wet etching and a method of fabricating a semiconductor device. The wet etching method includes providing a wafer in a process bath and an etchant is accommodated, supplying the process bath with a primary etchant to control a concentration of a specific material in the etchant, supplying the process bath with a first additive to increase the concentration of the specific material in the etchant, and supplying the process bath with a second additive to suppress a defect caused by an increase in the concentration of the specific material in the etchant. The etchant includes at least one, of the primary etchant, the first additive, and the second additive. The first additive and the second additive are separately supplied to the process bath.

Abstract: An etching method according to an embodiment includes forming a catalyst layer made of a first noble metal or the combination of the second noble metal and the metal other than noble metals on a surface made of a semiconductor, the catalyst layer including a first portion and a second portion, the first portion covering at least a part of the surface, the second portion being located on the first portion, having an apparent density lower than that of the first portion, and being thicker than the first portion; and supplying an etchant to the catalyst layer to cause an etching of the surface with an assist from the catalyst layer as a catalyst.

Abstract: A method of manufacturing a plurality of semiconductor chips for a liquid discharge head from a substrate includes forming trenches of a linear form through etching from the second surface along intended cutting portions, forming modified portions in the substrate by irradiating a laser beam from the first surface side along the intended cutting portions, and splitting the substrate into the plurality of semiconductor chips for a liquid discharge head, by cutting the substrate with stress applied to the modified portions. The intended cutting portions include inclined portions extending in a direction inclined with respect to a crystal orientation plane of the substrate and uninclined portions extending in a direction along the crystal orientation plane of the substrate, and the trenches are formed at least along the inclined portions.

Abstract: Disclosed is a method of manufacturing a metal mask. A method of manufacturing a metal mask in accordance with an exemplary embodiment of the present invention includes forming through holes in a plate using a laser, by scanning the laser onto sequentially smaller overlapping portions of the plate.

Abstract: A solar cell (1) of the present invention includes a photoelectric conversion layer (2) and a photonic crystal provided inside the photoelectric conversion layer (2) in order to have a photonic band gap. The photonic crystal has defects (31) in order to provide a defect level in the photonic band gap. QV which is a Q value representing a magnitude of a resonance effect yielded by coupling between the photonic crystal and an outside is substantially equal to Q? which is a Q value representing a magnitude of a resonance effect yielded by a medium of the photoelectric conversion layer (2).

Abstract: A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate, which correspond to the dimensions of a sidewall pattern around a dummy pattern. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. N-type and P-type diffusion layers are in upper portions of the first and second fin-shaped layers, respectively, and in upper and lower portions of the first and second pillar-shaped layers, respectively. First and second gate insulating films and first and second metal gate electrodes reside around the first and second pillar-shaped layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped layers.

Abstract: Methods of forming a defect free heteroepitaxial replacement fin by annealing the sacrificial Si fin with H2 prior to STI formation are provided. Embodiments include forming a Si fin on a substrate; annealing the Si fin with H2; forming a STI layer around the annealed Si fin; annealing the STI layer; removing a portion of the annealed Si fin by etching, forming a recess; forming a replacement fin in the recess; and recessing the annealed STI layer to expose an active replacement fin.

Abstract: In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

Abstract: A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.

Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device.

Abstract: Methods and apparatus for etching materials using tetramethylammonium hydroxide (TMAH) are described. The methods may involve including an additive when applying the TMAH to the material to be etched. The additive may be a gas, and in some situations may be clean dry air. The clean dry air may be provided with the TMAH to minimize or prevent the formation of hillocks in the etched structure. Apparatus for performing the methods are also described.

Abstract: A polishing composition for a silicon wafer and a rinsing composition for a silicon wafer according to the present invention contain a nonionic surfactant of a polyoxyethylene adduct. The HLB value of the polyoxyethylene adduct is 8 to 15. The weight-average molecular weight of the polyoxyethylene adduct is 1400 or less. The average number of moles of oxyethylene added in the polyoxyethylene adduct is 13 or less. The content of the polyoxyethylene adduct in each of the polishing composition and the rinsing composition is 0.00001 to 0.1% by mass.

Abstract: Systems and methods for etching the surface of a substrate may utilize a thin layer of fluid to etch a substrate for improved anti-reflective properties. The substrate may be secured with a holding fixture that is capable of positioning the substrate. A fluid comprising an acid and an oxidizer for etching may be prepared, which may optionally include a metal catalyst. An amount of fluid necessary to form a thin layer contacting the surface of the substrate to be etched may be dispensed. The fluid may be spread into the thin layer utilizing a tray that the substrate is dipped into, a plate that is placed near the surface of the substrate to be etched, or a spray or coating device.

Abstract: A method to thin an initial silicon-on-insulator substrate that has a layer of silicon oxide buried between a silicon carrier substrate and a silicon surface layer.

Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.

Abstract: A method for manufacturing a semiconductor substrate product having: providing an etching liquid containing water, a hydrofluoric acid compound and an organic solvent, and applying the etching liquid to a semiconductor substrate, the semiconductor substrate having a silicon layer and a silicon oxide layer, the silicon layer containing an impurity, and thereby selectively etching the silicon oxide layer.

Abstract: A method of texturizing a silicon substrate comprising a) contacting the substrate with an etching solution comprising glycolic acid, b) etching a surface of the substrate thereby forming disruptions in said surface of the substrate, and c) removing the etching solution to yield a texturized substrate, said texturized substrate having a plurality of disruptions in at least one surface with a surface density of disruptions of a minimum of 60 disruptions in a 400 micron square area.

Abstract: A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H2O2) and water (H2O).

Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.

Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.

Abstract: Methods for protecting a texturized region and a lightly doped diffusion region of a solar cell to improve solar cell lifetime and efficiency are disclosed. In an embodiment, an example method includes providing a solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, a silicon substrate and where the silicon substrate includes a texturized region and a lightly doped diffusion region. The method includes placing the solar cell on a receiving medium with the front side of the solar cell placed on an upper surface of the receiving medium, where the upper surface of the receiving medium prevents damage to the to the lightly doped diffusion region and damage to the texturized region on the front side of the solar cell during a contact printing process or transferring. In an embodiment, the lightly doped diffusion region has a doping concentration below 1×1019 cm?3 and the receiving medium includes a material having a moh's hardness in the range of 5-10.

Abstract: A liquid agent for the surface treatment of monocrystalline wafers, which contains an alkaline etching agent and also at least one low-volatile organic compound. Systems of this type can be used both for the cleaning, damage etch and texturing of wafer surfaces in a single etching step and exclusively for the texturing of silicon wafers with different surface quality, whether it now be wire-sawn wafers with high surface damage or chemically polished surfaces with minimum damage density.

Abstract: A liquid composition for wet etching has improved selectivity for polysilicon over silicon dioxide, even when the polysilicon is heavily doped and/or the silicon dioxide is a low temperature oxide. The composition comprises 0.05-0.4 percent by weight hydrofluoric acid, 15-40 percent by weight nitric acid, 55-85 percent by weight sulfuric acid and 2-20 percent by weight water. A method and apparatus for wet etching using the composition are also disclosed.

Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.

Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate; and a plurality of convex structures formed on a surface of the substrate and arranged in a longitudinal direction of the substrate, each convex structure having a top surface, a bottom surface located on the surface of the substrate, a first end surface and a second end surface parallel to each other, and a front side surface and a rear side surface parallel to each other, in which the rear side surface of one of two adjacent convex structures and the front side surface of the other are located on a same plane to allow the plurality of convex structures to form a zigzag structure.

Abstract: A method of producing a semiconductor substrate product, the method containing: a step of preparing an aqueous solution containing 7% by mass or more and 25% by mass or less of a quaternary alkyl ammonium hydroxide; a step of preparing a semiconductor substrate having a silicon film comprising a polycrystalline silicon film or an amorphous silicon film; and a step of heating the aqueous solution at 80° C. or higher and applying the resultant aqueous solution onto the semiconductor substrate to etch at least a part of the silicon film.

Abstract: An electronic device manufacturing method includes a cutting step at which a wafer is cut to obtain chips before pattern formation and a polishing step at which cut surfaces of the obtained chips are subjected in one batch to barrel polishing. The method further includes an aligning step at which the polished chips are aligned so that front surfaces thereof face in an upward direction. The method further includes a bonding step at which the cut surfaces of the aligned chips are bonded together with an adhesive to thereby form a chip assembly. The method further includes a pattern forming step at which a circuit pattern is formed on each of the chips of the chip assembly and a melting step at which the adhesive on the chip assembly is melted to thereby separate the chip assembly into chips after pattern formation.

Abstract: The present invention relates to a silicon etching solution which is used for selectively etching a dummy gate made of silicon in a process for producing a transistor including a laminate formed of at least a high dielectric material film and a metal gate containing hafnium, zirconium, titanium, tantalum or tungsten by the method of removing the dummy gate made of silicon to replace the dummy gate with the metal gate and which includes 0.1 to 40% by weight of at least one alkali compound selected from the group consisting of ammonia, a diamine and a polyamine represented by the general formula (1), 0.01 to 40% by weight of at least one polyhydric alcohol selected from the group consisting of specific polyhydric alcohols and a non-reducing sugar, and 40 to 99.89% by weight of water, and a process for producing a transistor using the silicon etching solution.

Abstract: A method for simultaneously detecting and separating a target analyte such as a protein or other macromolecule that includes providing a porous silicon matrix on the silicon substrate, exposing the porous silicon matrix to an environment suspect of containing the target analyte, observing optical reflectivity of the porous silicon matrix; and correlating the changes in the silicon substrate to the target analyte.

Abstract: Polycrystalline silicon (poly-Si) can be thoroughly removed without significant effect on adjacent oxides by an aqueous solution of ammonium hydroxide with smaller concentrations of hydrogen peroxide than are normally used in ammonia-peroxide mixture (APM) formulations used for cleaning. The etching selectivity of poly-Si relative to oxides can be widely tuned by varying the hydrogen-peroxide concentration. Compared to other formulations used to remove poly-Si dummy gates in logic-node fabrication, such as TMAH, these aqueous solutions are less hazardous to workers and the environment.

Abstract: An silicon-containing antireflective coating (SiARC) material is applied on a substrate. The SiARC material which includes a base polymer and may include a boron silicate polymer including silsesquioxane. An etch sequence is utilized, which includes a first wet etch employing a basic solution, a second wet etch employing an acidic solution, and a third wet etch employing another basic solution. The first wet etch can be employed to break up the boron silicate polymer, and the second wet etch can remove the base polymer material, and the third wet etch can remove the residual boron silicate polymer and other residual materials. The SiARC material can be removed from a substrate employing the etch sequence, and the substrate can be reused for monitoring purposes.

Abstract: A process for cleaning a wafer having an uneven pattern at its surface. The process includes at least the steps of: cleaning the wafer with a cleaning liquid; substituting the cleaning liquid retained in recessed portions of the wafer with a water-repellent liquid chemical after cleaning; and drying the wafer, wherein the cleaning liquid contains 80 mass % or greater of a solvent having a boiling point of 55 to 200° C., and wherein the water-repellent liquid chemical supplied in the substitution step has a temperature of not lower than 40° C. and lower than a boiling point of the water-repellent liquid chemical thereby imparting water repellency at least to surfaces of the recessed portions.

Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and produce a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of 45° or greater therebetween, and the modified spots are made align in one row along the line.

Abstract: A reaction block having a plurality of reaction chambers defined therein is provided. A bottom surface of each of the reaction chambers is configured to provide a seal for a corresponding reaction region on the substrate and around a periphery of the substrate. The reaction block includes a plurality of inlet channels and provides a gap between a top surface of the substrate and a bottom surface of the reaction block. The gap accepts a fluid from the inlet channels, wherein the reaction block includes a plurality of vacuum channels having access to the bottom surface of the reaction block to remove the fluid from the gap. A method of selectively etching a substrate for combinatorial processing is also provided.

Abstract: A method of depositing a non-continuous coating of a first material on a substrate, comprising: a) the formation of a mask on this substrate, by forming at least two mask layers, and etching of at least one cavity in these layers, this cavity having an outline such that a coating, deposited on the substrate, through the cavities of the mask, has at least one discontinuity over said outline of the cavity; b) the deposition of the first material on the substrate, through the cavities of the mask, the coating thus deposited having at least one discontinuity over the outline of said cavity; and c) the mask is removed.

Abstract: This invention is concerning an etchant composition used to etch a silicon-containing film formed on a target substrate. The etchant composition includes at least one selected from the group consisting of an organic compound containing a hydroxyl group, an organic compound containing a carbonyl group, an inorganic acid and inorganic salt, hydrofluoric acid, ammonium fluoride and an organic acid.

Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.

Abstract: The invention relates to a method for the conditioning of flat objects such as silicon substrates. The objects, obtained by sawing from a block form a comb like structure by being fixed with one edge to a plate shaped fixation apparatus, are conditioned by conventional rinsing, separating and wet chemical treatment, wherein the treatment takes place before the separation of the sawed substrates from the fixation apparatus. An apparatus which is suitable for carrying out the method has two regions arranged parallel to the apparatus longitudinal axis (L) and above one another, wherein the upper region is configured as an adapter region (1). The lower region is formed as a holding region (2) which comprises a part, provided as a channel (11), of a circumferentially closed or closable channel system which can be supplied with liquid by means of closable supply openings (5).

Abstract: Method of selectively etching a first material on a substrate with a high selectivity towards a second material by flowing a liquid etchant across a substrate surface at a flow sufficiently fast to generate a minimum mean velocity parallel to the substrate's surface, wherein the first material is selected from a group including materials with semiconducting properties based on at least two different chemical elements.

Abstract: Low bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments.

Abstract: A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.