Abstract: The present invention provides a chemical solution, which demonstrates excellent etching performance for transition metal-containing substances and has excellent defect inhibition performance, a method for manufacturing the chemical solution, and a method for treating a substrate. The chemical solution according to an embodiment of the present invention includes one or more kinds of periodic acids selected from the group consisting of a periodic acid and a salt thereof, one or more kinds of first metal components selected from the group consisting of Ti and Zr, and water. In a case where the chemical solution includes one kind of first metal component, a content of the one kind of first metal component is 1 ppt by mass to 100 ppm by mass with respect to a total mass of the periodic acids.

Abstract: A method of selectively removing NiPt material from a microelectronic substrate, the method comprising contacting the NiPt material with an aqueous etching composition comprising: an oxidising agent; a strong acid; and a source of chloride.

Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.

Abstract: In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.

Abstract: This disclosure relates to a cleaning composition that contains 1) at least one redox agent; 2) at least one alkylsulfonic acid or a salt thereof, the alkylsulfonic acid containing an alkyl group substituted by OH or NH2; 3) at least one aminoalcohol; 4) at least one corrosion inhibitor; 5) at least one water soluble organic solvent; 6) water; and 7) optionally, at least one pH adjusting agent.

Abstract: The present invention relates to an etching composition, an etching method, and a method of preparing a semiconductor device using the same, and more particularly, to an etching composition comprising a compound capable of selectively removing a nitride film with a high selectivity while minimizing an etch rate of the oxide film, and a method of preparing a semiconductor device comprising an etching process using the etching composition.

Abstract: An apparatus for cutting a substrate is disclosed. The apparatus includes a main body containing a reactive solution and the substrate; and a catalytic cutting element disposed inside the main body and contacting one of at least two adjacent cutting peripheries of the substrate to conduct a chemical reaction to cut the substrate.

Abstract: Provided is an etchant for a semiconductor process, which contains a sulfonic acid compound, a halogen ion, nitric acid or a nitric acid ion, an organic cation, and water.

Abstract: An etching adhesive tape for manufacturing a touch screen and a manufacturing method thereof, and an etching method are disclosed. The etching adhesive tape includes a base sheet and a functional layer disposed on the base sheet, the functional layer includes a first region corresponding to a region to be etched, and the first region includes an etching paste.

Abstract: Provided are a method for etching a metal or metal oxide without using a reagent, etc., that affects the environment, a method for smoothing a surface of a metal or metal oxide on an atomic level, and a method for patterning on an atomic level. Etching of a metal or metal oxide, or smoothing of a surface of a metal or metal oxide is possible using ozone water in which only ozone is dissolved. Patterning can also be performed by providing a metal that does not dissolve in the ozone water as a resist on a metal or metal oxide that can be etched by ozone water in which only ozone is dissolved, and etching using the ozone water.

Abstract: An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper redistribution structure includes an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion. A passivation layer is on the upper insulating layer and the upper redistribution structure. An upper opening is configured to pass through the passivation layer and expose the upper pad portion. Vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion.

Abstract: Compositions and methods for enhancing adhesion between a copper conducting layer and a dielectric material during manufacture of a printed circuit board. Conditioning compositions contain a functional organic compound and preferably a transition metal ion. The functional organic compound, e.g., a purine derivative, is capable of forming a self-assembled monolayer. Adhesion promoting compositions contain an acid, preferably an inorganic acid, and an oxidant. The latter compositions may also contain a corrosion inhibitor and/or a transition metal ion selected from among Zn, Ni, Co, Cu, Ag, Au, Pd or another Pt group metal. The corrosion inhibitor may comprise a nitrogen-containing aromatic heterocyclic compound.

Abstract: A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.

Abstract: A method of removing portions of a conductive layer comprising a transparent conductive material and/or a metallic material disposed on a plastic substrate used for capacitive touchscreen devices includes providing a plastic substrate having a conductive layer disposed on a surface thereof and removing portions of the conductive layer at the surface of the plastic substrate to establish a pattern of electrically isolated conductive portions on the surface of the plastic substrate. The conductive portions or traces are electrically connected to a touchscreen controller, which is operable to determine a location of a touch or proximity of an object at or near the surface of the plastic substrate responsive to a detected change in capacitance. The removal process may comprise etching or laser ablating portions of the conductive layer at the surface of the plastic substrate.

Abstract: A method for providing electroless deposition of a metal layer on a plurality of metal patterns, wherein a dielectric surface is between some of the plurality of metal patterns and metal residue is on the dielectric surface is provided. The dielectric surface is pretreated with an alkaline solution with a pH of at least 8 comprising at least one complexing agent, wherein the complexing agent forms a metal complex with the metal residue and wherein some metal oxide residue remains. The dielectric surface is pretreated with an acidic solution, wherein the acidic solution dissolves metal oxide residue. Metal is electrolessly deposited on the plurality of metal patterns.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to optimization profile generation and provide a method, system and computer program product for user guided generation of network link optimization profiles. In one embodiment of the invention, a network optimization profile generation method can be provided. The method can include ranking different performance criterion for a target network, testing the target network for the different performance criterion, weighting results of the testing according to the ranking of the different performance criterion, generating a set of target network configuration parameters through optimization of the weighted results, for instance simulated annealing, and applying the set of target network configuration parameters to the target network as a profile.

Abstract: A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.

Abstract: Embodiments described herein provide methods for forming indium-gallium-zinc oxide (IGZO) devices. A substrate is provided. An IGZO layer is formed above the substrate. A copper-containing layer is formed above the IGZO layer. A wet etch process is performed on the copper-containing layer to form a source region and a drain region above the IGZO layer. The performing of the wet etch process on the copper-containing layer includes exposing the copper-containing layer to an etching solution including a peroxide compound and one of citric acid, formic acid, malonic acid, lactic acid, etidronic acid, phosphonic acid, or a combination thereof.

Abstract: Processes are described to etch metals. In an embodiment, a process may include contacting a substrate with a stripping solution to remove photoresist from the substrate to produce a stripped substrate. The stripped substrate may include a plurality of solder pillars and a plurality of metal-containing field regions disposed around the plurality of solder pillars. In an illustrative embodiment, the plurality field regions may include copper. Additionally, the process may include rinsing the stripped substrate to produce a rinsed substrate. The rinsed substrate may be substantially free of a Sn layer or a Sn oxide layer. Further, the process may include contacting the rinsed substrate with an etch solution that is capable of removing an amount of one or more metals from the plurality of field regions.

Abstract: An etchant composition includes ammonium persulfate (((NH4)2)S2O8), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water.

Abstract: An etching method, having the step of applying an etching liquid onto a TiN-containing layer in a semiconductor substrate thereby etching the TiN-containing layer, the etching liquid comprising water, and a basic compound and an oxidizing agent in water thereof to be within the range of pH from 8.5 to 14, and the TiN-containing layer having a surface oxygen content from 0.1 mol % to 10 mol %.

Abstract: Provided is a plating method of a circuit substrate comprising a conductive pattern in which a metal layer containing at least silver and copper is exposed on an outer surface. The plating method comprises: step (A) of treating the circuit substrate with a first liquid agent containing an oxidizing agent; step (B) of treating the circuit substrate after the step (A) with a second liquid agent which dissolves copper oxide, and thereby removing copper oxide from the conductive pattern's surface; step (C) of treating the circuit substrate after the step (B) with a third liquid agent whose rate of dissolving silver oxide (I) at 25° C. is 1000 times or more faster than its rate of dissolving copper (0) at 25° C., and thereby removing silver oxide from the conductive pattern's surface; and step (D) of performing electroless plating on the conductive pattern of the circuit substrate after the step (C).

Abstract: Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures.

Abstract: Disclosed are a test piece and the manufacturing method thereof The test piece includes an insulating substrate and a circuit pattern structure formed on the insulating substrate, wherein circuit pattern structure includes a first metal pattern layer, a second metal pattern layer, a third metal pattern layer, a fourth metal pattern layer, and a fifth metal pattern layer. The first metal pattern layer, the second metal pattern layer, the third metal pattern layer, the fourth metal pattern layer, and the fifth metal pattern layer have same pattern shapes and positions thereof are overlapping in a plane. The first metal pattern layer and the second metal pattern layer are nano-metal films formed by vacuum coating, therefore, the test piece has excellent uniformity of film and low resistance to provide a stable test current to prevent the judging mistakes and to improve the test efficiency.

Abstract: Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl3, antimony alkylamines, and antimony alkoxides, such as Sb(OEt)3. The oxygen source may be, for example, ozone. In some embodiments the antimony oxide thin films are deposited in a batch reactor. The antimony oxide thin films may serve, for example, as etch stop layers or sacrificial layers.

Abstract: A method includes passing a chemical solution through a metal-ion absorber, wherein metal ions in the metal-ion absorber are trapped by the metal-ion absorber. The chemical solution exiting out of the metal-ion absorber is then used to etch a metal-containing region, wherein the metal-containing region includes a metal that is of a same element type as the metal ions.

Abstract: The present invention provides an etching liquid for a multilayer thin film containing a copper layer and a titanium layer, and a method of using it for etching a multilayer thin film containing a copper layer and a titanium layer, that is, an etching liquid for a multilayer thin film containing a copper layer and a titanium layer, which comprises (A) hydrogen peroxide, (B) nitric acid, (C) a fluoride ion source, (D) an azole, (E) a quaternary ammonium hydroxide and (F) a hydrogen peroxide stabilizer and has a pH of from 1.5 to 2.5, and a etching method of using it.

Abstract: A thin film transistor including an oxide semiconductor with favorable electrical characteristics is provided. The thin film transistor includes a gate electrode provided over a substrate, a gate insulating film provided over the gate electrode, an oxide semiconductor film provided over the gate electrode and on the gate insulating film, a metal oxide film provided on the oxide semiconductor film, and a metal film provided on the metal oxide film. The oxide semiconductor film is in contact with the metal oxide film, and includes a region whose concentration of metal is higher than that of any other region in the oxide semiconductor film (a high metal concentration region). In the high metal concentration region, the metal contained in the oxide semiconductor film may be present as a crystal grain or a microcrystal.

Abstract: Methods and formulations for the selective etching of etch stop layers deposited above metal-based semiconductor layers used in the manufacture of TFT-based display devices are presented. The formulations are based on an alkaline solution. Methods and formulations for the selective etching of molybdenum-based and/or copper-based source/drain electrode layers deposited above metal-based semiconductor layers used in the manufacture of TFT-based display devices are presented. The formulations are based on an alkaline solution.

Abstract: In a method for removing metal at the edge of a wafer, including from a notch in the edge of the wafer, water is dripped or otherwise supplied onto the up-facing metal-plated front side of the wafer, while rotating the wafer. A metal etchant, such as sulfuric acid, is provided onto the back side of the wafer, at a flow rate multiple times greater than the water flow rate. The etchant flows over the edge of the wafer and the notch, and onto an annular edge on the front side of the wafer. The metal plated in the notch is removed, even if the notch has a radial depth greater than the width of the exclusion zone. The flow rates of the water and the etchant, and the rotation speed may be adjusted to provide a static water film, with the etchant diffusing into the outer edge of the water film.

Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.

Abstract: High field-effect mobility is provided for a semiconductor device including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a transistor in which a stack of oxide semiconductor layers is provided over a gate electrode layer with a gate insulating layer provided therebetween, an oxide semiconductor layer functioning as a current path (channel) of the transistor and containing an n-type impurity is sandwiched between oxide semiconductor layers having lower conductivity than the oxide semiconductor layer. In the oxide semiconductor layer functioning as the channel, a region on the gate insulating layer side contains the n-type impurity at a higher concentration than a region on the back channel side. With such a structure, the channel can be separated from the interface between the oxide semiconductor stack and the insulating layer in contact with the oxide semiconductor stack, so that a buried channel can be formed.

Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.

Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.

Abstract: A post metal chemical-mechanical planarization (CMP) cleaning process for advanced interconnect technology is provided. The process, which follows CMP, combines an acidic clean and a basic clean in sequence. The process can achieve a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. The process also eliminates the circular ring defects that occur intermittently during roller brush cleans within a roller brush clean module.

Abstract: Provided are methods for processing semiconductor substrates having titanium nitride (TiN) structures as well as aluminum (Al) structures and, in some embodiments, other structures, such as silicon germanium (SiGe), tantalum nitride (TaN), hafnium oxide (HfOx), silicon nitride (SiN), and/or silicon oxide (SiO2) structures. Etching solutions and processing conditions described herein provide high etching selectivity of titanium nitride relative to these other materials. As such, the titanium nitride structures can be removed (partially or completely) without significant damage to these other structures. In some embodiments, the etching rate of titanium nitride is at least about 200 Angstroms per minute and even at least about 350 Angstroms per minute, while the etching rate of aluminum and/or other materials is less than 15 Angstroms per minute. An etching solution may be kept at 40° C. to 65° C. and may include ammonium hydroxide and hydrogen peroxide (between 1:600 and 1:3,000 by weight).

Abstract: Provided are methods for processing semiconductor substrates having titanium nitride (TiN) structures as well as aluminum (Al) structures and, in some embodiments, other structures, such as silicon germanium (SiGe), tantalum nitride (TaN), hafnium oxide (HfOx), silicon nitride (SiN), and/or silicon oxide (SiO2) structures. Etching solutions and processing conditions described herein provide high etching selectivity of titanium nitride relative to these other materials. As such, the titanium nitride structures can be removed (partially or completely) without significant damage to these other structures. In some embodiments, the etching rate of titanium nitride is at least about 200 Angstroms per minute and even at least about 350 Angstroms per minute, while the etching rate of aluminum and/or other materials is less than 15 Angstroms per minute. An etching solution may be kept at 40° C. to 65° C. and may include ammonium hydroxide and hydrogen peroxide (between 1:600 and 1:3,000 by weight).

Abstract: A method of removing non-noble metal oxides from material (e.g., semiconductor material) used to make a microelectronic device includes providing the material comprising traces of the conducting non-noble metal oxides; applying a chemical mixture (or chemical solution) to the material; removing the traces of the non-noble metal oxides from the material; and removing the chemical mixture from the material. The non-noble metal oxides comprise MoOx, wherein x is a positive number between 0 and 3. The chemical solution comprises any one of HNO3-based chemicals, H2SO4-based chemicals, HCl-based chemicals, or NH4OH-based chemicals.

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Abstract: A method of the invention includes reducing stiction of a MEMS device by providing a conductive path for electric charge collected on a bump stop formed on a substrate. The bump stop is formed by depositing and patterning a dielectric material on the substrate, and the conductive path is provided by a conductive layer deposited on the bump stop. The conductive layer can also be roughened to reduce stiction.

Abstract: A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate.

Abstract: An etching agent for a semiconductor substrate, which is capable of etching a titanium (Ti)-based metal film on a semiconductor substrate and an etching method using the etching agent, and relates to a liquid for preparing the etching agent for a semiconductor substrate composed of a solution comprising (A) hydrogen peroxide, (B) a phosphonic acid chelating agent having a hydroxyl group, (C) a basic compound, and (D-1) a copper anticorrosive. An etching method for etching a titanium (Ti)-based metal film on a semiconductor substrate using the etching agent. A solution comprising (B) a phosphonic acid chelating agent having a hydroxyl group, (C) a basic compound, and (D-1) a copper anticorrosive.

Abstract: Embodiments of the present invention include diffusion barriers, methods for forming the barriers, and semiconductor devices utilizing the barriers. The diffusion barrier comprises a self-assembled monolayer (SAM) on a semiconductor substrate, where one surface of the SAM is disposed in contact with and covalently bonded to the semiconductor substrate, and one surface of the monolayer is disposed in contact with and covalently bonded to a metal layer. In some embodiments, the barrier comprises an assembly of one or more monomeric subunits of the following structure: Si—(CnHy)-(LM)m where n is from 1 to 20, y is from 2n?2 to 2n, m is 1 to 3, L is a Group VI element, and M is a metal, such as copper. In some embodiments, (CnHy) can be branched, crosslinked, or cyclic.

Abstract: A method for chemical mechanical polishing of a substrate comprising tungsten using a nonselective chemical mechanical polishing composition.

Abstract: Disclosed herein is an aqueous alkaline etching solution comprising water and an alkaline material being selected from the group consisting of ammonium hydroxide, ammonium phosphate, ammonium carbonate, quaternary ammonium hydroxide, quaternary ammonium phosphate, quaternary ammonium carbonate, an alkali metal hydroxide, an alkaline earth metal hydroxide, or a combination comprising at least one of the foregoing alkaline materials; the aqueous alkaline solution being operative to etch aluminum oxide at a rate greater than or equal to about 2:1 over a rate at which it etches a metal oxide semiconductor to be protected; wherein the aqueous etching solution has a pH of 8 to 13.

Abstract: Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures.

Abstract: A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes the steps of a) providing a blank printed wiring member comprising a copper foil laminated to a dielectric substrate; b) masking the blank printed wiring member to protect regions of the copper foil; c) removing copper in unprotected regions of the blank printed wiring member to form a patterned printed wiring member including contact pads and connector pads; d) depositing a nickel coating on the patterned printed wiring member using an electroless nickel deposition process; e) depositing a gold layer on the nickel coating using an electroless gold deposition process; and f) depositing palladium on the gold layer using an electroless palladium deposition process to improve wear resistance of the connector pads while preserving bondability of the contact pads.

Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Abstract: A reaction block having a plurality of reaction chambers defined therein is provided. A bottom surface of each of the reaction chambers is configured to provide a seal for a corresponding reaction region on the substrate and around a periphery of the substrate. The reaction block includes a plurality of inlet channels and provides a gap between a top surface of the substrate and a bottom surface of the reaction block. The gap accepts a fluid from the inlet channels, wherein the reaction block includes a plurality of vacuum channels having access to the bottom surface of the reaction block to remove the fluid from the gap. A method of selectively etching a substrate for combinatorial processing is also provided.

Abstract: A method of depositing a non-continuous coating of a first material on a substrate, comprising: a) the formation of a mask on this substrate, by forming at least two mask layers, and etching of at least one cavity in these layers, this cavity having an outline such that a coating, deposited on the substrate, through the cavities of the mask, has at least one discontinuity over said outline of the cavity; b) the deposition of the first material on the substrate, through the cavities of the mask, the coating thus deposited having at least one discontinuity over the outline of said cavity; and c) the mask is removed.