Controlled Atmosphere Patents (Class 438/909)
  • Patent number: 11749682
    Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mrunal A. Khaderbad, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 11718889
    Abstract: A method for producing a hot-dip galvanized steel sheet includes supplying humidified gas to the soaking zone 12 in a manner such that: in passes in which the steel sheet moves upward, the humidified gas is supplied from first humidified gas supply ports 40A to 40E provided at positions higher by 1.0 m or more and 5.0 m or less than the centers of lower hearth rolls 54 and overlapping the steel sheet in the passes when viewed from the side of the soaking zone; and in passes in which the steel sheet moves downward, the humidified gas is supplied from second humidified gas supply ports 42A to 42E provided at positions lower by 1.0 m or more and 5.0 m or less than the centers of the upper hearth rolls 52 and overlapping the steel sheet in the passes when viewed from the side of the soaking zone.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 8, 2023
    Assignee: JFE STEEL CORPORATION
    Inventors: Gentaro Takeda, Hideyuki Takahashi, Tetsuya Iwata, Koji Sawamura
  • Patent number: 11677042
    Abstract: Disclosed herein are methods, systems, and apparatuses for an light emitting diode (LED) array apparatus. In some embodiments, the LED array apparatus may include a plurality of mesas etched from a layered epitaxial structure. The layered epitaxial structure may include a P-type doped semiconductor layer, a active layer, and an N-type doped semiconductor layer. The LED array apparatus may also include one or more regrowth semiconductor layers, including a first regrowth semiconductor layer, which may be grown epitaxially over etched facets of the plurality of mesas. In some cases, for each mesa, the first regrowth semiconductor layer may overlay etched facets of the P-type doped semiconductor layer, the active layer, and the N-type doped semiconductor layer, around an entire perimeter of the mesa.
    Type: Grant
    Filed: March 29, 2020
    Date of Patent: June 13, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventors: Markus Broell, Michael Grundmann, David Hwang, Stephan Lutgen, Brian Matthew Mcskimming, Anurag Tyagi
  • Patent number: 8859441
    Abstract: The present invention provides a system and method for manufacturing a semiconductor device including a substrate and a high-? dielectric layer on the substrate. The system comprises a modular track; a substrate-forming chamber connected with the modular track for forming the substrate; and an atomic layer deposition (ALD) chamber connected with the modular track for providing the high-? dielectric layer.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: October 14, 2014
    Inventors: Ming-Hwei Hong, Ray-Nien Kwo, Tun-Wen Pi, Mao-Lin Huang, Yu-Hsing Chang, Pen Chang, Chun-An Lin, Tsung-Da Lin
  • Patent number: 8771535
    Abstract: A sample contamination method according to an embodiment includes spraying a chemical solution containing contaminants into a casing, carrying a semiconductor substrate into the casing filled with the chemical solution by the spraying, leaving the semiconductor substrate in the casing filled with the chemical solution for a predetermined time, and carrying the semiconductor substrate out of the casing after the predetermined time passes.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Yamada, Makiko Katano, Ayako Mizuno, Eri Uemura, Asuka Uchinuno, Chikashi Takeuchi
  • Patent number: 8696921
    Abstract: In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Byung-Lyul Park, Jong-Myeong Lee, Zung-Sun Choi, Hye-Kyung Jung
  • Patent number: 8657942
    Abstract: A trap device includes means for separating a liquid compound from a waste stream exhaust from a process chamber, means for collecting the liquid compound separated from the waste stream, means for selectively isolating the collected liquid compound from the waste stream, and means for evaporating the collected liquid compound to return the compound in gaseous form to the waste stream. This can enable a volatile liquid to be collected at a defined location, isolated from the waste stream, and, when so desired, returned to the waste stream in the form of a gas for subsequent abatement.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: February 25, 2014
    Assignee: Edwards Limited
    Inventors: Christopher John Shaw, Graeme Huntley, Andrew James Seeley
  • Patent number: 8597401
    Abstract: An exhausting method includes determining an exhaust flow rate of a process gas to be a predetermined value that is less than or equal to a gas flow rate corresponding to a maximum process capability of a purification system when the process gas is diluted to a lower explosive limit; calculating a pressure drop amount per unit time to maintain the determined exhaust flow rate of the process gas, based on a relation between the exhaust flow rate and the pressure drop amount per unit time; and evacuating an inside of the chamber to maintain the determined exhaust flow rate, while controlling the pressure through an automatic pressure control valve by setting a target pressure value to be updated as a control value of the automatic pressure control valve at every predetermined time interval so as to achieve a calculated pressure drop amount per unit time.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: December 3, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Norihiko Amikura, Risako Miyoshi
  • Patent number: 8575039
    Abstract: A surface treating method for treating a surface of a substrate inside a process chamber includes the steps of generating an atmosphere containing no moisture in the process chamber, heating the substrate inside the atmosphere containing no moisture in the process chamber; and causing a reaction between the substrate and an adhesion accelerating agent by feeding the adhesion accelerating agent gas into the process chamber.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 5, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuya Yamaguchi, Hiroyuki Hashimoto
  • Patent number: 8485126
    Abstract: A coating apparatus including a coating part which applies a liquid material including an oxidizable metal on a substrate; a chamber having a coating section in which the coating part applies the liquid material on the substrate and a transport section into which the liquid material is transported; an adjusting part which adjusts at least one of oxygen concentration and humidity inside the chamber; and a control part which stops an operation of the coating part in response to the entrance of foreign object into the chamber.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: July 16, 2013
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Hidenori Miyamoto, Kenji Maruyama, Tadahiko Hirakawa, Koichi Misumi
  • Patent number: 8216950
    Abstract: A semiconductor device includes an operating layer made of a semiconductor and a silicon nitride film formed on the operating layer with the use of a mixed gas that includes mono-silane gas, hydrogen gas, and nitrogen gas, by a plasma CVD apparatus, under a condition that a flow rate of the hydrogen gas is 0.2 percent to 5 percent to an overall flow rate.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: July 10, 2012
    Assignee: Eudyna Devices Inc.
    Inventor: Norikazu Iwagami
  • Patent number: 8198103
    Abstract: A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Dalton, Wesley C. Natzle, Paul W. Pastel, Richard S. Wise, Hongwen Yan, Ying Zhang
  • Patent number: 8119547
    Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: February 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiaki Kobayashi
  • Patent number: 8025736
    Abstract: Semiconductor device fabrication equipment performs a PEOX (physical enhanced oxidation) process, and includes a remote plasma generator for cleaning a process chamber of the equipment. After a PEOX process has been preformed, a purging gas is supplied into the process chamber to purge the process chamber, and the remote plasma generator produces plasma using a first cleaning gas. Accordingly, a reactor of the remote plasma generator is cleaned by the first cleaning gas plasma. Subsequently, the purging gas is supplied to purge the process chamber, and the remote plasma generator produces plasma using a second cleaning gas to remove the first cleaning gas plasma from the remote plasma generator and the process chamber. Finally, full flush operations are performed to remove any gases remaining in the process chamber.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: September 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Hwan Chin, Kyoung-In Kim, Hak-Su Jung, Kyoung-Min An
  • Patent number: 8012886
    Abstract: A method is provided for treating a leadframe comprising copper or copper alloy to enhance adhesion of molding compound to it. The leadframe is oxidized in an oxidation treatment bath to form copper oxide on the surface of the leadframe. It is then dipped in a complexing or chelating agent to enhance the purity of the copper oxide formed. Thereafter, the leadframe is cleaned with an acid to remove any contaminants remaining on the leadframe.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: September 6, 2011
    Assignee: ASM Assembly Materials Ltd
    Inventors: Yiu Fai Kwan, Tat Chi Chan, Wai Chan, Chi Chung Lee
  • Patent number: 7993820
    Abstract: A liquid film applicator means can apply a photosensitive lyophobic film 18 to a substrate 16. An exposure unit 10 is placed on the back side of the substrate and forms the lyophobic film applied on the substrate into a pattern in alignment with gate electrodes 13. A dropping unit 55 drops a test liquid to a surface of the substrate having a pattern of the lyophobic film formed by the exposure means. A measuring means 58 detects the droplet dropped by the dropping unit. A determining means determines whether the pattern of the lyophobic film formed by the exposure means is proper or not based on the droplet detected by the detecting means.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: August 9, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Inoue, Masahiko Ando, Shuji Imazeki
  • Patent number: 7968459
    Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Joel P. DeSouza, Zhibin Ren, Alexander Reznicek, Devandra K. Sadana, Katherine L. Saenger, Ghavam Shahidi
  • Patent number: 7943510
    Abstract: A method of processing a substrate with a conductive film formed thereover and method of forming a micromagnetic device. In one embodiment, the method of processing the substrate includes reducing a temperature of the substrate to a stress-compensating temperature, and maintaining the temperature of the substrate at the stress-compensating temperature for a period of time. The method also includes increasing the temperature of the substrate above the stress-compensating temperature.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: May 17, 2011
    Assignee: Enpirion, Inc.
    Inventors: Ken Takahashi, Trifon M. Liakopoulos
  • Patent number: 7857880
    Abstract: A semiconductor manufacturing process facility requiring use therein of air exhaust for its operation, such facility including clean room and gray room components, with the clean room having at least one semiconductor manufacturing tool therein, and wherein air exhaust is flowed through a region of the clean room. The facility includes an air exhaust treatment apparatus arranged to (i) receive air exhaust after flow thereof through said region of said clean room, (ii) produce a treated air exhaust, and (iii) recirculate the treated air exhaust to an ambient air environment in the facility, e.g., to the gray room of the facility.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: December 28, 2010
    Assignee: Advanced Technology Materials, Inc.
    Inventors: W. Karl Olander, Joseph D. Sweeney, Luping Wang
  • Patent number: 7851233
    Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a wafer; measuring the wafer for wafer data after the first process; securing the wafer on an E-chuck in a processing chamber; collecting sensor data from a sensor embedded in the E-chuck; adjusting clamping forces to the E-chuck based on the wafer data and the sensor data; and thereafter performing a second process to the wafer secured on the E-chuck in the processing chamber.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: December 14, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jo Fei Wang, Sunny Wu, Jong-I Mou
  • Patent number: 7622782
    Abstract: A pressure sensor includes a base substrate silicon fusion bonded to a cap substrate with a chamber disposed between the base substrate and the cap substrate. Each of the base substrate and the cap substrate include silicon. The base substrate includes walls defining a cavity and a diaphragm portion positioned over the cavity, wherein the cavity is open to an environment to be sensed. The chamber is hermetically sealed from the environment.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: November 24, 2009
    Assignee: General Electric Company
    Inventors: Stanley Chu, Sisira Kankanam Gamage, Hyon-Jin Kwon
  • Patent number: 7611579
    Abstract: A system for synthesizing nanostructures using chemical vapor deposition (CVD) is provided. The system includes a housing, a porous substrate within the housing, and on a downstream surface of the substrate, a plurality of catalyst particles from which nanostructures can be synthesized upon interaction with a reaction gas moving through the porous substrate. Electrodes may be provided to generate an electric field to support the nanostructures during growth. A method for synthesizing extended length nanostructures is also provided. The nanostructures are useful as heat conductors, heat sinks, windings for electric motors, solenoid, transformers, for making fabric, protective armor, as well as other applications.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: November 3, 2009
    Assignee: Nanocomp Technologies, Inc.
    Inventors: David Lashmore, Joseph J. Brown, Robert C. Dean, Jr., Peter L. Antoinette
  • Patent number: 7569484
    Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: August 4, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu
  • Patent number: 7514306
    Abstract: A method for manufacturing a semiconductor device, includes: a) spraying a combusted gas onto a member containing a metal element, the combusted gas being obtained by combusting a mixed gas that at least includes a gas containing a hydrogen atom and an oxygen gas; b) spraying the combusted gas onto the amorphous semiconductor film placed on a substrate having an insulating surface thereof; and c) adding the metal element to at least a vicinity of a surface of the amorphous semiconductor film to enhance re-crystallization of a semiconductor.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: April 7, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Sumio Utsunomiya
  • Patent number: 7399708
    Abstract: Methods are provided for cleaning a microelectronic device, and one method includes providing a substrate having a patterned SOG/anti-reflective material; performing a process to cure the patterned SOG/anti-reflective material; and performing a cleaning process to remove the cured SOG/anti-reflective material. An apparatus for cleaning a microelectronic device is provided that includes a processing chamber; means for performing a SOG/anti-reflective material curing process within the processing chamber, means for performing a cleaning process within the processing chamber and means for venting the processing chamber.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: July 15, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Paul Schilling
  • Patent number: 7390758
    Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: June 24, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Yoshiaki Kobayashi
  • Patent number: 7329308
    Abstract: The present invention relates to systems and methods for controlling humidity and temperature in gases or air streams used in semiconductor processing systems. These systems and methods can be used in combination with systems and methods for contaminant detection and removal.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: February 12, 2008
    Assignee: Entegris, Inc.
    Inventors: William M. Goodwin, Oleg P. Kishkovich, Anatoly Grayfer
  • Patent number: 7172981
    Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: February 6, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Yoshiaki Kobayashi
  • Patent number: 7163849
    Abstract: Upon formation of an impurity-added silicon film by a low-pressure CVD apparatus, diffusion of an impurity from another similar silicon film, which has already been formed over the inside walls of the deposition chamber, is suppressed in the following manner. After insertion of a semiconductor substrate, having a gate oxide film (insulating film) formed thereover, into the deposition chamber of a CVD apparatus (first film forming apparatus), the inside of the deposition chamber is heated while minimizing, relative to a time A required for heating of the inside of the deposition chamber under atmospheric pressure, a time B required for the subsequent heating in the deposition chamber under a pressure adjusted to vacuum or not greater than atmospheric pressure. The formation of an impurity-added silicon film is then started. At this time, the relation between A and B is controlled to satisfy the following equation: 0.1×B?A?13×B.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: January 16, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Hiroaki Kikuchi, Toshiaki Sawada, Hirohiko Yamamoto
  • Patent number: 7135418
    Abstract: Methods of forming conformal films that reduce the amount of metal-containing precursor and/or silicon containing precursor materials required are described. The methods increase the amount of film grown following each dose of metal-containing and/or silicon-containing precursors. The methods may involve introducing multiple doses of the silicon-containing precursor for each dose of the metal-containing precursor and/or re-pressurizing the process chamber during exposure to a dose of the silicon-containing precursor. The methods of the present invention are particularly suitable for use in RVD processes.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: November 14, 2006
    Assignee: Novellus Systems, Inc.
    Inventor: George D. Papasouliotis
  • Patent number: 7118683
    Abstract: The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or more elements selected from Group VIII of the periodic table is provided within a reaction chamber; and a substrate is provided within the reaction chamber. The substrate has both a silicon-oxide-containing composition and at least one organic substance thereover. The silicon-oxide-containing composition is plasma etched within the reaction chamber. The plasma etching of the silicon-oxide-containing composition has increased selectivity for the silicon oxide of the composition relative to the at least one organic substance than would plasma etching conducted without the material in the chamber. The invention also encompasses a plasma reaction chamber assembly. The assembly comprises at least one interior wall, and at least one liner along the at least one interior wall. The liner comprises one or more of Ru, Fe, Co, Ni, Rh, Pd, Os, W, Ir, Pt and Ti.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Max F. Hineman, Li Li
  • Patent number: 7109129
    Abstract: Methods of forming conformal films that reduce the amount of metal-containing precursor and/or silicon containing precursor materials required are described. The methods increase the amount of film grown following each dose of metal-containing and/or silicon-containing precursors. The methods may involve introducing multiple doses of the silicon-containing precursor for each dose of the metal-containing precursor and/or re-pressurizing the process chamber during exposure to a dose of the silicon-containing precursor. The methods of the present invention are particularly suitable for use in RVD processes.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: September 19, 2006
    Assignee: Novellus Systems, Inc.
    Inventor: George D. Papasouliotis
  • Patent number: 7090716
    Abstract: The present invention is directed toward a method for reducing pattern distortions in imprinting layers by reducing gas pockets present in a layer of viscous liquid deposited on a substrate. To that end, the method includes varying a transport of the gases disposed proximate to the viscous liquid. Specifically, the atmosphere proximate to the substrate wherein a pattern is to be recorded is saturated with gases that are either highly soluble, highly diffusive, or both with respect to the viscous liquid being deposited. Additionally, or in lieu of saturating the atmosphere, the pressure of the atmosphere may be reduced.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: August 15, 2006
    Assignees: Molecular Imprints, Inc., Board of Regents, The University of Texas System
    Inventors: Ian M. McMackin, Nicholas A. Stacey, Daniel A. Babbs, Duane J. Voth, Michael P. C. Watts, Van N. Truskett, Frank Y. Xu, Ronald D. Voisin, Pankaj B. Lad
  • Patent number: 7064084
    Abstract: To provide a method for the formation of oxide films to form with advantage a high-quality oxide film having excellent uniformity in film thickness and film quality over the entire wafer. The method for the formation of oxide films comprises: the pretreatment process of forming a protective oxide film on the surface of a wafer positioned in a reaction vessel by performing oxidation treatment with radical oxidative species or an atmosphere containing radical oxidative species under depressurized conditions; and the oxide-film-formation process of forming an oxide film on the wafer by performing oxidation treatment at a predetermined temperature under depressurized conditions. The oxide-film-formation process is preferably performed following the pretreatment process in a continuous manner in the reaction vessel in which the pretreatment process is performed.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: June 20, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Shingo Hishiya, Koji Akiyama, Yoshikazu Furusawa, Kimiya Aoki
  • Patent number: 7049154
    Abstract: A vapor phase growth method for growing a semiconductor single crystal thin film on a front surface of a semiconductor single crystal substrate (1) while introducing gas into a reaction chamber (11), has a step of performing heating output power control in a gas introduction region (R1) according to a temperature detected in a region other than the gas introduction region (R1) in the reaction chamber (11).
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: May 23, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Hisashi Kashino
  • Patent number: 6977225
    Abstract: A new process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: December 20, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Ravi Iyer, Sujit Sharan
  • Patent number: 6962878
    Abstract: A method for reducing the dimension of a patterned organic photoresist area by reducing the pressure of a reactive environment surrounding the patterned photoresist to cause outgasing. The outgased materials CxHyOz are then decomposed in the reactive environment leaving the outgased photoresist porous. The environment surrounding the patterned photoresist is then increased to atmospheric pressure, which compresses or shrinks the porous photoresist. Photoresist lines having a dimension as small as about 0.085 ?m can be obtained.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: November 8, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Chen Su, Chao-Tzung Tsai
  • Patent number: 6933236
    Abstract: A method for forming a photoresist pattern with minimally reduced transformations through the use of ArF photolithography, including the steps of: forming an organic anti-reflective coating layer on a an etch-target layer already formed on a substrate; coating a photoresist for ArF on the organic anti-reflective coating layer; exposing the photoresist with ArF laser; forming a first photoresist pattern by developing the photoresist, wherein portions of the organic anti-reflective coating layer are revealed; etching the organic anti-reflective coating layer with the first photoresist pattern as an etch mask and forming a second photoresist pattern by attaching polymer to the first photoresist pattern, wherein the polymer is generated during etching the organic anti-reflection coating layer with an etchant including O2 plasma; and etching the etch-target layer by using the second photoresist pattern as an etch mask.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: August 23, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Kwon Lee, Sang-Ik Kim, Weon-Joon Suh
  • Patent number: 6933249
    Abstract: A manufacturing method for semiconductor devices that can improve uniformity in the surface of a silicon nitride film or a nitride film to be formed and improve production efficiency is provided. A step of forming a first film that is a silicon oxide film or a silicon oxynitride film on a silicon substrate, a step of forming a second film that is a tetrachlorosilane monomolecular layer, and a step of forming a third film that is a silicon nitride monomolecular layer by performing a nitriding process on the second film are included. A silicon nitride film having a predetermined film thickness is formed by repeating the step of forming the second film and the step of forming the third film for a predetermined number of times. In a manufacturing apparatus, a plurality of silicon substrates are arranged on a stair-like wafer boat, and a process gas is supplied toward the upper side of a reaction tube from a process gas supply pipe.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: August 23, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Shin Yokoyama, Anri Nakajima, Yoshihide Tada, Genji Nakamura, Masayuki Imai, Tsukasa Yonekawa
  • Patent number: 6929985
    Abstract: A material not releasing gaseous organic substances during use is used as a filter medium and a sealing material for tightly sealing between the medium and a frame. Specifically, a synthetic paraffin not containing an aliphatic hydrocarbon having not more than 19 carbon atoms or less is used as a non-silicone type water repellent contained in a treatment agent for forming fibers into a cloth-like filter medium. A carboxylic acid ester having 400 or more molecular weight is used as a plasticizer and a phenolic compound having 300 or more molecular weight is used as an antioxidant to be added to the treatment agent and the sealing material. This enables that the gaseous organic substances are not present in a clean room, a semiconductor production apparatus or the like.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: August 16, 2005
    Assignee: Taisei Corporation
    Inventors: Sadao Kobayashi, Masayuki Imafuku, Yoshihide Wakayama
  • Patent number: 6903030
    Abstract: A supply system in a heat-treating apparatus for a semiconductor process has a combustor (12), heating unit (13), and gas distributor (14). The combustor (12) has a combustion chamber (59) disposed outside a process chamber (21). The combustor (12) generates water vapor by reaction of hydrogen gas and oxygen gas in the combustion chamber (59), and supplies it to the process chamber (21). The heating unit (13) has a heating chamber (61) disposed outside the process chamber (21). The heating unit (13) selectively heats a gas not passing through the combustion chamber (59) to a temperature not lower than an activating temperature of the gas, and supplies it to the process chamber (21). The gas distributor (14) selectively supplies the hydrogen gas and oxygen gas to the combustion chamber (59), and selectively supplies a reactive gas and inactive gas to the heating chamber (61).
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: June 7, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Katsutoshi Ishii, Yutaka Takahashi, Harunari Hasegawa
  • Patent number: 6890866
    Abstract: A method for manufacturing a semiconductor device having a semiconductor substrate with a contact hole filled by an aluminum-containing thin film. This manufacturing method includes a step of forming a silicon-containing thin film so as to fill the contact hole on the surface of the semiconductor substrate, a step of removing the part of the silicon-containing thin film outside the contact hole, a step of forming an aluminum-containing thin film on the surface of the semiconductor substrate after completing the step of removing the part of the silicon-containing substrate, and a step of heating the semiconductor substrate on which the aluminum-containing thin film is formed to such a temperature as to cause silicon to diffuse with respect to aluminum.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: May 10, 2005
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 6867152
    Abstract: A rapid vapor deposition (RVD) method conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film has a low dielectric constant, low wet etch rate, low film shrinkage and low stress hysteresis, appropriate for various integrated circuit dielectric gap fill applications such as shallow trench isolation. The method includes the following two principal operations: depositing a thin conformal and saturated layer of aluminum-containing precursor over some or all of the substrate surface; and exposing the saturated layer of aluminum-containing precursor to a silicon-containing precursor gas to form a dielectric layer. In some cases, the substrate temperatures during contact with silicon-containing precursor are greater than about 250 degree Celsius to produce an improved film. In other cases, post-deposition anneal process may be used to improve properties of the film.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: March 15, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Dennis M. Hausmann, Adrianne K. Tipton, Patrick A. Van Cleemput, Bunsen Nie, Francisco J. Juarez, Teresa Pong
  • Patent number: 6841056
    Abstract: A process tool for electrochemically treating a substrate is configured to reduce the oxygen concentration and/or the sulfur dioxide concentration in the vicinity of the substrate so that corrosion of copper may be reduced. In one embodiment, a substantially inert atmosphere is established within the process tool including a plating reactor by providing a continuous inert gas flow and/or by providing a cover that reduces a gas exchange with the ambient atmosphere. The substantially inert gas atmosphere may also be maintained during further process steps involved in electrochemically treating the substrate including required transportation steps between the individual process steps.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: January 11, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Axel Preusse
  • Patent number: 6838359
    Abstract: A method of manufacturing a semiconductor device, which method comprises the step of epitaxially growing a stack comprising an n-type doped layer of a semiconductor material followed by at least one further layer of a semiconductor material, the stack being grown in one continuous cycle.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: January 4, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Wiebe Barteld De Boer
  • Patent number: 6833306
    Abstract: Semiconductor device annealing process with deuterium at superatmospheric pressures to improve reduction of the effects of hot carrier stress during device operation, and devices produced thereby.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: December 21, 2004
    Assignee: Board of Trustees of the University of Illinois
    Inventors: Joseph W. Lyding, Karl Hess, Jinju Lee
  • Patent number: 6809035
    Abstract: A rapid thermal processor, having a process chamber, including a stable heat source in the form of a heatable mass. Heat is provided to the heatable mass using a series of heating devices. The temperature of the heatable mass establishes the temperature of a semiconductor wafer placed in contact or in close proximity to the heatable mass. To reduce thermal gradients, the heatable mass can be included in an insulative compartment made of an insulating material, such as opaque quartz and the like. The top of the insulative compartment can include an access portion to allow the semiconductor wafer to be placed on the heatable mass disposed therein. During processing, the wafer may be further exposed to a high intensity radiation energy source for a short duration of time.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: October 26, 2004
    Assignee: WaferMasters, Inc.
    Inventor: Woo Sik Yoo
  • Patent number: 6787377
    Abstract: The invention is a method of determining a set temperature profile for a method of controlling respective substrate temperatures of a plurality of groups in accordance with respective corresponding set temperature profiles, in a method of heat processing a plurality of substrates that are classified into the plurality of groups.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: September 7, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Wenling Wang, Koichi Sakamoto, Fujio Suzuki, Moyuru Yasuhara
  • Patent number: 6782907
    Abstract: A gas recirculation flow control method and apparatus for use in an evacuation system having a vacuum chamber into which a gas is introduced, a first vacuum pump for exhausting the gas from the vacuum chamber and reducing the pressure in the vacuum chamber to a desired pressure, a second vacuum pump for performing evacuation to lower the back pressure of the first vacuum pump below an allowable back pressure, and a gas recirculation line for returning a part of gas exhausted from the first vacuum pump to the vacuum chamber.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: August 31, 2004
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kawasaki, Tokuhisa Ohiwa, Itsuko Sakai
  • Patent number: 6689699
    Abstract: There is disclosed a semiconductor processing apparatus comprising a process chamber treating a substrate, a process gas feeder feeding a process gas to the process chamber, a first vacuum pump exhausting the process chamber, a second vacuum pump inhaling gas on an exhaust side of the first vacuum pump, and a circulation path circulating at least a part of the process gas exhausted from the process chamber via the first vacuum pump into the process chamber, wherein the circulation path is provided with a dust trapping mechanism, the dust trapping mechanism being capable of substantially maintaining a conductance of the circulation path before and after the capture of dust.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: February 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Itsuko Sakai, Takayuki Sakai, Tokuhisa Ohiwa