Abstract: Wirebonds are formed to couple an opto-electronic device chip having two or more opto-electronic devices to a signal processing chip. Two or more mutually adjacent wirebond groups, each corresponding to one of the opto-electronic devices, are formed. For example, each wirebond group can include a first wirebond coupling a P-terminal of the opto-electronic device of the wirebond group to the signal processing chip, a second wirebond coupling an N-terminal of the opto-electronic device of the wirebond group to the signal processing chip, and a third wirebond coupling the opto-electronic device chip to the signal processing chip.

Abstract: Semiconductor structures (52-9, 52-11, 52-12) and methods (100-300) are provided for a semiconductor devices employing strained (70) and relaxed (66) semiconductors, The method comprises, forming (106, 208, 308) on a substrate (54, 56, 58) first (66-1) and second (66-2) regions of a first semiconductor material (66) of a first conductivity type and a first lattice constant spaced apart by a gap or trench (69), filling (108, 210, 308) the trench or gap (69) with a second semiconductor material (70) of a second, conductivity type and a second different lattice constant so that the second semiconductor material (70) is strained with respect to the first semiconductor material (66) and forming (110, 212, 312) device regions (80, 88, S, G, D) communicating with the first (66) and second (70) semiconductor materials and adapted to provide device current (87, 87?) through at least part of the strained second semiconductor material (70) in the trench (69).

Abstract: Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70-2, 70-3, 70-4, etc.) of a first semiconductor material (70) of a first conductivity type, forming (52-9) second spaced-apart regions (74-1, 74-2, 74-3, etc.) of a second semiconductor material (74) of opposite conductivity type interleaved with the first space-apart regions (70-1, 70-2, 70-3, 70-4, etc.) with PN junctions therebetween, thereby forming a superjunction structure, wherein the second regions have higher mobility than the first regions for the same carrier type. Other regions (88) are provided in contact with the superjunction structure (81) to direct control current flow therethrough. In a preferred embodiment, the first material (70) is relaxed SiGe and the second material (74) is strained silicon.

Abstract: A semiconductor junction device includes a substrate of low resistivity semiconductor material having a preselected polarity. A tapered recess extends into the substrate and tapers inward as it extends downward from an upper surface of the substrate. A semiconductor layer is disposed within the recess and extends above the upper surface of the substrate. The semiconductor layer has a polarity opposite from that of the substrate. A metal layer overlies the semiconductor layer.

Abstract: A method of making a bi-directional transient voltage suppression device is provided, which comprises: (a) providing a p-type semiconductor substrate; (b) epitaxially depositing a lower semiconductor layer of p-type conductivity; (c) epitaxially depositing a middle semiconductor layer of n-type conductivity over the lower layer; (d) epitaxially depositing an upper semiconductor layer of p-type conductivity over the middle layer; (e) heating the substrate, the lower epitaxial layer, the middle epitaxial layer and the upper epitaxial layer; (f) etching a mesa trench that extends through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (g) thermally growing an oxide layer on at least those portions of the walls of the mesa trench that correspond to the upper and lower junctions of the device.

Abstract: A semiconductor system (200), particularly a diode, having a p-n junction is proposed, that is formed as a chip having an edge area, which includes a first layer (2) of a first conductivity type and a second layer (1, 3) of a second conductivity type; the second layer (1, 3) including at least two sublayers (1, 3); both sublayers (1, 3) forming a p-n junction with the first layer (2); the p-n junction of the first layer (2) with the first sublayer (3) being provided exclusively in the interior of the chip, and the p-n junction between the first layer (2) and the second sublayer (1) being provided in the edge area of the chip; for each cross-section of the chip area parallel to the chip plane, the first sublayer (3) corresponding only to a part of such a cross-section.

Abstract: One aspect of the present invention is a to provide a process for manufacturing a pn junction diode, includes providing a semiconductor wafer having an n-type cathode layer formed thereon. Then, a p-type anode layer is formed on the n-type cathode layer so that a pn junction interface is formed between the n-type cathode layer and the p-type anode layer. Next, a cathode and anode electrodes are formed on the semiconductor wafer and the p-type anode layer, respectively. Lastly, first and second ions having average projection ranges Rp different from each other are simultaneously implanted up to the cathode layer so that one or more first and second implanted regions are formed alternately and overlapped side by side, thereby forming a lattice-defect region having a substantially uniform thickness beneath and adjacent to the pn junction interface.

Abstract: A fabrication method for a horizontal direction semiconductor PN junction array which can be achieved when an epitaxial layer is grown by a metalorganic chemical vapor deposition (MOCVD method) by introducing (or doping) a small amount of CCl.sub.4 or CBr.sub.4 gas, includes forming a recess on an N type GaAs substrate by using a non-planar growth, performing a growth method of a P type epitaxial layer on the N type GaAs substrate by a metalorganic chemical vapor deposition method, and forming a horizontal direction PN junction array of P-GaAs/N-GaAs or P-AlGaAs/N-GaAs by introducing a gas comprising CCl.sub.4 or CBr.sub.4 .

Abstract: Zener diode with high stability in time and low noise for integrated circuits and provided in an epitaxial pocket insulated from the rest of a type N epitaxial layer grown on a substrate of type P semiconductor material.In said pocket are included a type N+ cathode region and a type P anode region enclosing it.The cathode region has a peripheral part surrounding a central part extending in the anode region less deeply than the peripheral part.