Abstract: A method of patterning conductive lines (252) of a memory array integrated circuit (200) using a hard mask (244) and reactive ion etching (RIE). Using a hard mask (244) prevents oxidation of underlying conductive lines (210).

Abstract: An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.

Abstract: This is a method for masking a structure 12 for patterning micron and submicron features, the method comprises: forming at least one monolayer 32 of adsorbed molecules on the structure; prenucleating portions 46,48 of the adsorbed layer by exposing the portions corresponding to a desired pattern 36 of an energy source 42; and selectively forming build-up layers 66,68 over the prenucleated portions to form a mask over the structure to be patterned. Other methods are also disclosed.

Abstract: Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a substrate having a pit pattern. In another approach, the substrate is produced by etching. A series of stacked layers having desired electrical characteristics is applied to the substrate and planarized in a manner that creates electrical devices and connections therebetween. The microelectronic devices can include a series of row and columns and are used to store data at their intersection.

Abstract: In the construction of electronic devices with one or more flip chips and, in some cases, one or more leadless components, mounted on a substrate, the interconnections are made with conductive adhesive deposited using specialized masks. A magnetic metal mask fabricated of a membrane of magnetic material is placed temporarily onto the face of a semiconductor wafer or of a circuit or other substrate. When properly positioned with respect to the wafer or substrate, such as by relational guide holes, the mask is held in place by the magnetic forces produced by a controllable electromagnet. Contact pad openings in the magnetic metal mask are formed by suitable means such as laser cutting or photo-etching. The magnetic metal mask may include a flexible interface layer on the side facing the wafer or substrate to assure tight sealing thereto, so as to reduce smearing and bridging of the conductive adhesive paste and avoid bridging between contact pads that might otherwise occur during deposition of the paste.

Abstract: An object of the present invention is forming a concave portion (including a penetration hole) in a semiconductor substrate by a sandblast method without causing a defect such as a chip or a crack in processing ends of the concave portion. In order to achieve the object, in a semiconductor wafer in which a plurality of semiconductor chips are formed, a metal film is formed on the semiconductor substrate at least in a region of a predetermined range in an inside and an outside of an circumferential portion except for a central portion and its vicinity of a region in that the concave portion (including the penetration hole) of the respective semiconductor chips is to be formed. Then, the entire surface of the semiconductor wafer including the metal film is masked except for the region in that the concave portion of the respective semiconductor chips is to be formed. With this state, the concave portion is formed in the respective semiconductor chips formed on the semiconductor wafer by the sandblast method.

Abstract: A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.

Abstract: A method structures a chemical amplification photoresist layer, in which a photoresist layer of the chemically amplified type is brought into contact, before or after the exposure for structuring, with a base which is capable of diffusing into the photoresist layer. As a result of this treatment with the base, greater steepness and less roughness of the resist profiles are achieved in the subsequent development step.

Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), an optional etch stop layer (16) formed on a surface (14) of the substrate (12), and a patterning layer (20) formed on a surface (18) of the etch stop layer (16). The template (10) is used in the fabrication of a semiconductor device (30) for affecting a pattern in device (30) by positioning the template (10) in close proximity to semiconductor device (30) having a radiation sensitive material formed thereon and applying a pressure to cause the radiation sensitive material to flow into the relief image present on the template.

Abstract: A method for patterning a layer of a microelectronic device includes the step of forming an etching mask on the layer to be etched opposite the microelectronic substrate. The etching mask defines exposed portions of the material layer and the etching mask has a notch in the sidewall thereof adjacent the material layer. The exposed portions of the material layer are then etched. More particularly, the step of forming the etching mask can include the steps of forming a first patterned mask layer on the layer to be etched and forming a second patterned mask layer on the first patterned mask layer wherein the second patterned mask layer extends beyond the first patterned mask layer thereby defining the notch in the sidewall of the etching mask.

Abstract: A semiconductor memory device includes a memory cell capacitor for storing information, wherein the memory cell capacitor includes a capacitor insulation film of a double oxide on a lower electrode. The lower electrode has a layered structure of Ir/IrO2/Ir or Ru/RuO2/Ru acting as a diffusion barrier of oxygen or Pb. Further, the use of a Pt—Ir alloy is disclosed for the lower electrode.

Abstract: A resin sealing film is formed on a silicon substrate by using a printing mask and a squeegee. The side surface in the tip portion of the squeegee is substantially V-shaped, and the printing is performed by pushing the tip portion of the squeegee into the gap between adjacent bump electrodes. As a result, the sealing film is formed in a manner to be depressed in the region between adjacent bump electrodes so as to facilitate the swinging movement of the bump electrodes. It follows that, in a temperature cycle test performed after the silicon substrate is mounted to a circuit substrate, the stress derived from the difference in thermal expansion coefficient between the silicon substrate and the circuit substrate is absorbed by the bump electrode.

Abstract: A semiconductor device with an improved speed response has a linear ridge pattern including an active layer, a cladding layer, a current blocking layer, and a contact layer on a semiconductor substrate. The insulating layer may be formed in a pattern having a high resistance to dry etching along a longitudinal side of the ridge pattern.

Abstract: A method of fabricating a bottom anti-reflectivity coating (BARC) layer. The method of the invention comprises performing a pre-bake process on a provided titanium nitride layer. Amine ions absorbed into the surface of the titanium nitride layer are thus removed by the high temperature of the pre-bake process. A BARC layer is formed on the titanium nitride layer. A bake step is performed to remove a solvent, which is used for coating the BARC layer. A photoresist layer is coated on the BARC layer. Then, a soft-bake step is performed to remove a solvent, which is used for coating the photoresist layer. A photomask with a pattern is provided over the photoresist layer. An exposure step is performed to transfer the pattern to the photoresist layer. A development step is performed to remove a part of the photoresist layer so that the pattern is shown within the photoresist layer. A hard-bake step is performed to minimize the solvent in the photoresist layer.

Abstract: A manufacturable GaAs VFET process includes providing a doped GaAs substrate with a lightly doped first epitaxial layer thereon and a heavily doped second epitaxial layer positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of elongated, spaced apart source areas. Using the patterned conductive layer, a plurality of gate trenches are etched into the first epitaxial layer adjacent the source areas. The bottoms of the gate trenches are implanted and activated to form gate areas. A gate contact is deposited in communication with the implanted gate areas, a source contact is deposited in communication with the patterned conductive layer overlying the source areas, and a drain contact is deposited on the rear surface of the substrate.

Abstract: A passivating layer (220) is formed overlying portions of a mask (200). The mask (200) is used to pattern a semiconductor device substrate (62). In accordance with one embodiment of the present invention, the passivating layer (220) is removed prior to patterning the semiconductor device substrate (62). In yet another embodiment, the passivating layer (220) is cleaned prior to patterning the semiconductor device substrate (62) and then left to remain overlying portions of the mask (200) during the patterning process.

Abstract: Method for fabricating a nonvolatile ferroelectric memory, including the steps of (1) forming an insulating layer, a semiconductor layer, an etch stop layer, a lower electrode, a ferroelectric layer, and an upper electrode on a substrate in succession, (2) forming an etch mask pattern of a required form on the upper electrode, (3) using the etch mask pattern as a mask in subjecting the upper electrode, the ferroelectric layer, the lower electrode, the etch stop layer, the semiconductor layer, and the insulating layer to en bloc etching, to expose the substrate, and (4) removing the etch mask pattern, and forming source/drain regions in the exposed substrate, whereby providing a simple fabrication process and permitting to minimize an alignment allowance.

Abstract: In one embodiment, a masking chuck (68) is placed in contact with an integrated circuit structure (70) that contains conductive members (90). The masking chuck (68) is used to deposit a dielectric layer (92) on the integrated circuit structure (70). The dielectric layer (92) is then cured, and the masking chuck (68) is separated from the integrated circuit structure (68) to define openings (96) within the dielectric layer (92) which expose a portion of the underlying conductive members (90). A conductive layer (100) is then deposited in the openings (96), and polished to form conductive members (102) within the openings (96), which are electrically shorted to the underlying conductive members (90).

Abstract: A semiconductor device having a controlled drive current strength is produced by varying gate electrode length to accommodate any variation in insulating layer thickness from a desired value. After formation of the gate insulating layer on a substrate, the thickness is measured and compared to a desired value. Based on any differences between the measured and desired values, the length of the gate electrode is determined in order to counteract the variation in gate insulating layer thickness. This results in a change in channel length that counteracts the effect of the variation in insulating layer thickness on the drive current strength. The present process permits close control over the drive current strength of semiconductor devices. This also can provide decreased variation within and between lots and corresponding increases in productivity.

Abstract: A new method of preventing passivation keyhole damage and resist extrusion by a resist crosslinking mechanism is described. Semiconductor device structures are formed in and on a semiconductor substrate and covered by an insulating layer. Metal lines are formed overlying the insulating layer wherein there is a gap between two of the metal lines. A passivation layer is deposited overlying the metal lines. A negative tone photoresist material is coated over the passivation layer. The photoresist is exposed to light through a mask wherein the mask is clear overlying the metal lines in an active area and wherein the mask is opaque overlying a metal line in a bonding pad area where a bonding pad is to be formed. The portion of the negative tone photoresist underlying the clear mask is exposed to light whereby crosslinks are formed within the exposed photoresist and wherein the portion of the photoresist underlying the opaque mask is unexposed.

Abstract: The object of the present invention is to provide a method of manufacturing an improved semiconductor device in which overlay-accuracy can be enhanced even when a halftone mask is used. An oxide film is formed on an antireflection film. Resist films are selectively irradiated with light using a halftone phase shift mask. Subsequently, it is developed to form resist patterns for a connecting hole and an overlay mark. According to the, present invention, the provision of an antireflection film under an oxide film prevents formation of a ghost pattern in an overlay mark portion.

Abstract: A structure is provided comprising a semiconductor substrate, a gate oxide layer on the substrate, and a polysilicon layer on the gate oxide layer. A masking layer is formed on the polysilicon layer. The masking layer is then patterned into a mask utilizing conventional photolithographic techniques, but without patterning the polysilicon layer. The photoresist layer is then removed, whereafter the mask, which is patterned out of the masking layer, is utilized for patterning the polysilicon layer. The use of a carbon free mask for patterning the polysilicon layer, instead of a conventional photoresist layer containing carbon, results in less breakthrough through the gate oxide layer when the polysilicon layer is patterned. Less breakthrough through the gate oxide layer allows for the use of thinner gate oxide layers, and finally fabricated transistors having lower threshold voltages.

Abstract: A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region.

Abstract: A method for depositing copper on a titanium-containing surface of a substrate is provided. The method includes forming a patterned catalyst material on the substrate, such that the titanium-containing surface is exposed in selected regions. The catalyst material has an oxidation half-reaction potential having a magnitude that is greater than a magnitude of a reduction half-reaction potential of titanium dioxide. Copper is then deposited from an electroless solution onto the exposed regions of the titanium-containing surface.

Abstract: A method of forming an asymmetric transistor and an asymmetric transistor. The method includes patterning a first spacer material and a second spacer material over a gate electrode material on a substrate with one side of the second spacer material adjacent to a first spacer material. The gate electrode material is patterned according to the first spacer material and the second material. Junction regions are formed in the substrate adjacent to the gate electrode material. One of the first spacer material and the second spacer material is then removed and the gate electrode material is patterned into a gate electrode according to the other of the first spacer and the second spacer material. Finally, second junction regions are formed in the substrate adjacent to gate electrode.

Abstract: A method for patterning a layer of a microelectronic device includes the step of forming an etching mask on the layer to be etched opposite the microelectronic substrate. The etching mask defines exposed portions of the material layer and the etching mask has a notch in the sidewall thereof adjacent the material layer. The exposed portions of the material layer are then etched. More particularly, the step of forming the etching mask can include the steps of forming a first patterned mask layer on the layer to be etched and forming a second patterned mask layer on the first patterned mask layer wherein the second patterned mask layer extends beyond the first patterned mask layer thereby defining the notch in the sidewall of the etching mask.

Abstract: A multipurpose cap layer serves as a bottom anti-reflective coating (BARC) during the formation of a resist mask, a hardmask during subsequent etching processes, a hardened surface during subsequent deposition and planarization processes, and optionally as a diffusion barrier to mobile ions from subsequently deposited materials.

Abstract: The present invention is a process for making complex structures with nanoscale resolution in parallel by placing an NCG replica-based mask (or other suitable mask) in close proximity to a substrate and controlling, with nanoscale accuracy and precision, the relative movement of the mask and substrate while sequentially or concurrently carrying out a patterning process or processes. Another aspect of the invention is a diamond film with submicron and/or nanoscale features, that can be made by the method of the invention.

Abstract: In a method of manufacturing semiconductor device, an aluminum film and a barrier metal film are formed on a semiconductor substrate and then an interlayer insulation film 15 is formed over the aluminum film and the barrier metal film. Then a PVD-Al film is formed over the entire upper surface of the interlayer insulation film by PVD, whereupon the PVD-Al film the interlayer insulation film are etched to open via holes, exposing part of the upper surface of the barrier metal film. Subsequently, via plugs are formed by filling metal, which includes aluminum, in the via holes by selective CVD with masking by a native oxide film formed on the upper surface of the PVD-Al film whereupon the native oxide film is removed by etching. Then a CVD-Al is formed over the entire upper surface of the PVD-Al film and the via plugs by CVD.

Abstract: A method of fabricating on chip metal-to-metal capacitors (MMCAP) uses planar processing with a flexible choice of dielectric, thickness and capacitor shape. The method provides a simpler process which has a better yield and more reliable structure by creating a metal-to-metal capacitor on a planar surface, not in deep trenches. In addition to the process simplicity, the method also allows the use of any dielectric materials which are needed by the product designer; e.g., higher or lower dielectric constant and also not limited by high etch rate difference. Because the inventive process is a planar process, there are no corners in the bottom of deep trenches to cause yield and reliability problems. The capacitor area can be adjusted to any shape because there are no edge effects.

Abstract: A process for forming an etch mask having a discontinuous regular pattern utilizes beads, each of which has a substantially unetchable core covered by a removable spacer coating. Beads which have a core and a spacer coating are dispensed as a hexagonally-packed monolayer onto a thermo-adhesive layer, which is on a target layer. The beads are kept in place by a bead confinement wall. Following a vibrational step which facilitates hexagonal packing of the beads, the resultant assembly is heated so that the beads adhere to the adhesive layer. Excess beads are then discarded. Spacer shell material is then removed from each of the beads, leaving core etch masks. The core-masked target layer is then plasma etched to form a column of target material directly beneath each core. The cores and any spacer material underneath the cores are removed. The resulting circular island of target material may be used as an etch mask during wet isotropic etching of an underlying layer.

Abstract: In a mask imaging method (by shooting a laser beam) for forming holes in a resin layer of a printed board, a sectional shape is reshaped by beam reshaping optics. Light path holes corresponding to the holes to be formed in the resin layer are used. The reshaped laser beam shoots the light path holes formed in the mask individually at once. Simultaneous passage of the laser beam through the light path holes formed in the mask is allowed, to form the holes in the resin layer. Exposure of the periphery and inside of a hole to the laser beam results in removal of a decomposition residue and/or processing residue.

Abstract: A barrier metal film, Al alloy film and anti-reflective film are sequentially deposited on a surface to form an interconnect pattern by a photolithography technique. An overhanging portion of the anti-reflective film is etched away by a plasma of a Cl.sub.2 /BCl.sub.3 -mixed gas. Then an insulating interlayer is deposited on a resultant semiconductor structure.

Abstract: A formation method of a contact/through hole is provided, which is able to form a contact or through hole without raising such problems related to a resist mask. After forming a dielectric layer on a semiconductor substructure having a lower electrical conductor, a metal layer is formed on the dielectric layer. A patterned resist film is formed on the metal layer. Then, the metal layer is selectively etched using a patterned resist film as a mask to transfer the pattern of the resist film to the metal layer, forming a hole pattern to penetrate the metal layer. The patterned resist film is removed from the etched metal layer. The dielectric layer is selectively etched using the etched metal layer as a mask to thereby transfer the hole pattern of the metal layer to the dielectric layer. Thus, a contact/through hole is formed to penetrate the dielectric layer and to extend to the lower electrical conductor.

Abstract: A method for forming HSG polysilicon with reduced dielectric bridging and increased capacitance. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a reduced temperature to cause a nucleation of the second polysilicon layer. Grains are formed on the surface of the second polysilicon layer as a result of the nucleation. Next a wet etch is performed to remove portions of the polysilicon grains and portions of the first polysilicon layer. The duration of the wet etch is controlled to retain a roughened surface area. The size of the grains decreases during the wet etch and the distance between the grains increases. A dielectric layer is deposited to overlie the rough polysilicon following the wet etch. The thickness of the dielectric layer tends to be uniform thereby reducing bridging of the dielectric between the grains of the of the polysilicon.

Abstract: A new method of etching metal lines using fluorine-doped silicate glass as a hard mask is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A metal layer is deposited overlying the insulating layer. A layer of fluorine-doped silicate glass is deposited overlying the metal layer wherein the fluorine-doped silicate glass layer acts as a hard mask. The hard mask is covered with a layer of photoresist. The photoresist layer is exposed to actinic light and developed and patterned to form the desired photoresist mask. The hard mask is etched away where it is not covered by the photoresist mask leaving a patterned hard mask.

Abstract: An engraved recess (4) is formed in a resin stencil (1) at a position on a surface of the resin stencil where the resin stencil, when registered with a circuit board, agrees with a fiducial mark of the circuit board. The recess is formed by a laser (3) and serves as a fiducial mark.

Abstract: A method of fabricating nanometric structures on a substrate by dry etching includes setting the substrate at a temperature at which condensation of etching gas products of etching gas decomposed, recombined and reacted, or products of reactions between the etching gas and substrate material starts to occur, forming condensates at specific locations on the substrate. The condensates form an etching mask for the dry etching process.

Abstract: In a method for manufacturing a semiconductor device having a sharp step portion, a mask pattern to perform a patterning process of a photoresist layer is formed so that the dimension of the mask pattern is set to be larger than a design value of the corresponding wiring pattern only at a region where the thickness of the photoresist layer is different from that at a flat portion, and the mask pattern dimension at the flat portion which is away from the step portion is set to a design value of the corresponding wiring pattern. By using the mask pattern thus formed, the wiring dimension in the vicinity of the step portion can be prevented from becoming smaller than that at the flat portion under the condition that the wiring dimension of the design value can be obtained at the flat portion, so that the wirings can be formed according to the design value at any place containing the portion in the vicinity of the step portion and the flat portion.

Abstract: A composite body includes a semiconductor substrate having an oxide layer formed thereon and a nitride layer formed over the oxide layer. First and second deep trench configurations are formed in the composite body. To form a shallow isolation trench between the first and second deep trench configurations, intrinsic polysilicon upper layers of the first and second deep trench configurations and the nitride layer are planarized. A titanium layer is formed over the planarized composite body and caused to react with the intrinsic polysilicon upper layers to form first and second titanium silicide caps over the first and second deep trench configurations. A masking layer is formed over the composite body such that an opening exposes the region between the first and second deep trench configurations. An etching step that is selective to titanium silicide is then performed with the first and second deep trench caps serving as masks.

Abstract: An auxiliary device is constituted by a U-bolt-shaped, pincer-like implement which, during the fabrication of semiconductor devices with a mesa structure from a starting substrate forming a wafer, serves to transfer the outline geometry of the individual semiconductor devices from one side of the wafer to the back of the wafer. The implement has at least one tracer at the end of one of its arms for engaging a sawed groove and for guiding the implement along the sawed groove on one side of the wafer. At the end of the other arm, a marking device with at least one marking stylus is provided whereby the course of the at least one sawed grooved can be transferred from the front side of the wafer to the back, and scribed there in the form of auxiliary lines.

Abstract: This invention relates to methodology to resolve the problem of low drain/source breakdown voltage (BVdss) in small geometry devices with thin gate oxide. Improved drain diffusion profile implanting through disjoint NSD/NWELL windows in the extended drain region, This provides essentially an improved lightly diffused (LDD) structure. Further this invention relates to alternative methods to resolve the problem of low drain/source breakdown voltage in other structures which can be achieved by for example, building a number of side wall oxide layers, impurity compensation or oxygen implantation. The improved LDD structure to which this invention relates has a number of advantages when compared with other solutions. It enables high voltage transistors to be fabricated with high drive capability, without additional process steps being required to implement the structure. The inventions will find applications wherever a high voltage capability is required to interface with the outside world.

Abstract: A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed.

Abstract: A method for forming an upper metal wiring which is in contact with an under conductive layer in a highly integrated semiconductor device. The method includes the steps of forming a metal wiring layer on a lower insulating film, forming a contact hole in the insulating film to expose an under conductive layer, and growing a metal layer in the contact hole to fill up the contact hole, so that the metal wiring layer can be in contact with the lower conductive layer.

Abstract: A method for controlling the spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) to obtain a relatively high gain (.beta.) with a low-parasitic base resistance. In a first method, after the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is patterned with a photoresist using conventional lithography. Subsequently, the sacrificial layer is etched to produce an undercut. The emitter layer is then etched and a photoresist is applied over the first photoresist used to pattern the emitter mesa, as well as the entire device. The top layer of photoresist is patterned with a conventional process for lift-off metalization, such that the final resist profile has a re-entrant slope. The base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa.

Abstract: A method is provided for suppressing or eliminating void formation during the manufacture of integrated circuits. TEOS is deposited and etched to form recesses that assist in eliminating or suppressing void formation. The recesses may be located in an interlevel layer, or within the oxide layer just beneath the passivation layer.

Abstract: A semiconductor processing method of forming a static random access memory cell having an n-channel access transistor includes, providing a bulk semiconductor substrate; patterning the substrate for definition of field oxide regions and active area regions for the n-channel access transistor; subjecting the patterned substrate to oxidizing conditions to form a pair of field oxide regions and an intervening n-channel access transistor active area therebetween, the field oxide regions having respective bird's beak regions extending into the n-channel access transistor active area, the n-channel access transistor active area defining a central region away from the bird's beak regions; and conducting a p-type V.sub.T ion implant into the n-channel active area using the field oxide bird's beak regions as an implant mask to concentrate the V.sub.T implant in the central region of the active area.

Abstract: The present invention relates to a method for producing a semiconductor device having a semiconductor layer of SiC. The method comprises the steps of a) applying a mask on at least a portion of the SiC layer to coat a first portion of the SiC layer leaving a second portion thereof uncoated, b) applying a heat treatment to the SiC layer, and c) supplying dopants to the SiC layer during the heat treatment for diffusion of the dopants into the SiC layer at the second portion thereof for doping the SiC layer. The mask is made of crystalline AIN as the only component or AIN as a major component of a crystalline alloy constituting the material.

Abstract: An implant mask (14) and an etch mask (16) are utilized in forming a silicon carbide JFET (10). A source opening (17) and a drain opening (18) are formed in the masks (14,16). The etch mask (16) is removed, and a source area (19) and a drain area 21 are implanted through the openings (17,18) and source and drain contact (23, 24) are formed. A protective layer (26) is used to form source and drain contacts (23,24). A gate contact (27) is utilized to ensure the gate (28) is self-aligned to the gate contact (27).

Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.