Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.

Abstract: A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwiched by insulating layers (6,6?), wherein the material of the insulating layers (6,6?) has preferably a high dielectric constant. In a FET the quantum wells (4,9) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.

Abstract: A method of manufacturing a single-electron transistor device is provided. The method includes forming a thinned region in a silicon substrate, the thinned region offset by a non-selected region. The method also includes forming at least one quantum island from the thinned region by subjecting the thinned region to an annealing process. The non-selected region is aligned with the quantum island and tunnel junctions are formed between the quantum island and the non-selected region. The present invention also includes a single-electron device, and a method of manufacturing an integrated circuit that includes a single-electron device.

Abstract: An aspect relates to a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The creation of the nucleation sites includes implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures are grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures include at least one of nanocrystals, nanowires and nanotubes. According to various nanocrystal embodiments, the nanocrystals are positioned within a gate stack and function as a floating gate for a nonvolatile device. Other aspects and embodiments are provided herein.

Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.

Abstract: Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide.

Abstract: A quantum dot (22) is formed on a GaAs substrate (20). In the quantum dot (22), a single electron exists. A cap layer (26) is formed on a surrounding area of the quantum dot (22), and a barrier layer (28) is formed thereon. A quantum dot (30) for detection is formed on the barrier layer (28). Then, a cap layer (34) covering the quantum dot (30) and the like is formed.

Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.

Abstract: A composition and method for fabricating and tuning a dopant based core-shell semiconductor having a quantum dot core with an excitation band-gap are provided. A quantum dot core composed of an alloy of cadmium sulfide (CdS) and zinc sulfide (ZnS) as semi-conductor materials include a dopant of manganese (Mn) added to the core and an outer shell of zinc sulfide (ZnS). The dopant based core/shell quantum dot semiconductor of the present invention allows the fine tuning of an excitation band-gap, covering a wide range (from 2.4 eV to ˜4 eV). When doped with Mn, these alloy Qdots emit bright yellow/orange light. Tuning of the excitation band is accomplished by changing the alloy composition of the core. Based on photophysical studies a new core/shell/shell model is provided, in place of the traditional core/shell model. Due to the interfacial diffusion of the cations from the core and shell an intermediate alloy layer is formed providing an inner shell; this inner shell layer is the real host of the dopant ions.

Abstract: A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (24) is in the form of a nanotube. An insulated gate (32) is provided adjacent to the channel region (24) for controlling conduction i ni the channel region between the source and drain regions.

Abstract: A quantum dot semiconductor device includes an active layer having a plurality of quantum dot layers each including a composite quantum dot formed by stacking a plurality of quantum dots and a side barrier layer formed in contact with a side face of the composite quantum dot. The stack number of the quantum dots and the magnitude of strain of the side barrier layer from which each of the quantum dot layers is formed are set so that a gain spectrum of the active layer has a flat gain bandwidth corresponding to a shift amount of the gain spectrum within a desired operation temperature range.

Abstract: In a method and system for controllable electrostatic-directed deposition of nanoparticles from the gas phase on a substrate patterned to have p-n junction(s), a bias electrical field is reversely applied to the p-n junction, so that uni-polarly charged nanoparticles are laterally confined on the substrate by a balance of electrostatic, van der Waals and image forces and are deposited on a respective p-doped or n-doped regions of the p-n junction when the applied electric field reaches a predetermined strength. The novel controllable deposition of nanoparticles employs commonly used substrate architectures for the patterning of an electric field attracting or repelling nanoparticles to the substrates and offers the opportunity to create a variety of sophisticated electric field patterns which may be used to direct particles with greater precision.

Abstract: A quantum-well photoelectric device, such as a quantum cascade laser, is constructed of monocrystalline nanoscale membranes physically removed from a substrate and mechanically assembled into a stack.

Abstract: A method of fabricating a semiconductor device having high output power and excellent long-term reliability by preventing thermal adverse influence exerted at the time of window structure formation is provided. The method comprises a 1st step of forming predetermined semiconductor layers 2 to 9 containing at least an active layer 4b consisting of a quantum well active layer on a semiconductor substrate 1; a 2nd step of forming a first dielectric film 10 on a first portion of the surface of the semiconductor layers 2 to 9; a 3rd step of forming a second dielectric film 12 made of the same material as that of the first dielectric film 10 and having a density lower than that of the first dielectric film 10 on a second portion of the surface of the semiconductor layers 2 to 9; and a 4th step of heat-treating a multilayer body containing the semiconductor layers 2 to 9, the first dielectric film 10, and the second dielectric film 12 to disorder the quantum well layer below the second dielectric film 12.

Abstract: A composition and method for fabricating and tuning a dopant based core-shell semiconductor having a quantum dot core with an excitation band-gap are provided. A quantum dot core composed of an alloy of cadmium sulfide (CdS) and zinc sulfide (ZnS) as semi-conductor materials include a dopant of manganese (Mn) added to the core and an outer shell of zinc sulfide (ZnS). The dopant based core/shell quantum dot semiconductor of the present invention allows the fine tuning of an excitation band-gap, covering a wide range (from 2.4 eV to ˜4 eV). When doped with Mn, these alloy Qdots emit bright yellow/orange light. Tuning of the excitation band is accomplished by changing the alloy composition of the core. Based on photophysical studies a new core/shell/shell model is provided, in place of the traditional core/shell model. Due to the interfacial diffusion of the cations from the core and shell an intermediate alloy layer is formed providing an inner shell; this inner shell layer is the real host of the dopant ions.

Abstract: Provided is a method of forming quantum dots, including: forming a buffer layer on an InP substrate so as to be lattice-matched with the InP substrate; and sequentially alternately depositing In(Ga)As layers and InAl(Ga)As or In(Ga, Al, As)P layers that are greatly lattice-mismatched with each other on the buffer layer so as to form In(Ga, Al)As or In(Ga, Al, P)As quantum dots.

Abstract: A fabricating method of Single Electron Transistor includes processing steps as follows: first, deposit the sealing material of gas molecule or atom state on the top-opening of the nano cylindrical pore, which having formed on the substrate, so that the diameter of said top-opening gradually reduce to become a reduced nano-aperture, whose opening diameter is smaller than that of said top-opening; then, keep the substrate in horizontal direction and tilt or rotate said substrate into tilt angle or rotation angle in coordination with tilt angle with the reduced nano-aperture as center respectively, and pass the deposit material of gas molecular or atom state through the reduced nano-aperture respectively. Thereby a Single Electron Transistor including island electrode, drain electrode, source electrode and gate electrode of nano-quantum dot with nano-scale is directly fabricated on the surface of said substrate.

Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.

Abstract: The present invention is a method of manufacturing a quantum dot array having a plurality of columnar parts including a quantum dot on a substrate, the method comprising the steps of obliquely vapor-depositing a material constituting a first barrier layer to become an energy barrier against the quantum dot onto a surface of the substrate, so as to form a plurality of first barrier layers; obliquely vapor-depositing a material constituting the quantum dot with respect to the surface of the substrate, so as to form the quantum dots on the first barrier layers; and obliquely vapor-depositing a material constituting a second barrier layer to become an energy barrier against the quantum dot with respect to the surface of the substrate, so as to form the second barrier layers on the quantum dots.

Abstract: A method for forming at least one quantum dot at at least one predetermined location on a substrate is disclosed. In one aspect, the method comprises providing a layer of semiconductor material on an insulating layer on the substrate. The layer of semiconductor material is patterned so as to provide at least one line of semiconductor material having a width (wL) and having a local width variation at at least one predetermined location where the at least one quantum dot has to be formed. The local width variation has an amplitude (A) of between about 20 nm and 35 nm higher than the width wL of the at least one line. The at least one line is patterned to form at least one quantum dot. A design for a lithographic mask for use with the method and a method for making such a design are also disclosed.

Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

Abstract: Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals (13). It consists in: exposing with a beam of electrons (11) at least one zone (12) of a semiconductor film (1) lying on an electrically insulating support (2), the exposed zone (12) contributing to defining at least one dewetting zone (10) of the film (1), annealing the film (1) at high temperature in such a way that the dewetting zone (10) retracts giving the zone of one or several nanocrystals (13).

Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Abstract: A nanofluidic channel fabricated in fused silica with an approximately 500 nm square cross section was used to isolate, detect and identify individual quantum dot conjugates. The channel enables the rapid detection of every fluorescent entity in solution. A laser of selected wavelength was used to excite multiple species of quantum dots and organic molecules, and the emission spectra were resolved without significant signal rejection. Quantum dots were then conjugated with organic molecules and detected to demonstrate efficient multicolor detection. PCH was used to analyze coincident detection and to characterize the degree of binding. The use of a small fluidic channel to detect quantum dots as fluorescent labels was shown to be an efficient technique for multiplexed single molecule studies. Detection of single molecule binding events has a variety of applications including high throughput immunoassays.

Abstract: Methods for obtaining codes to be implemented in coding nanoscale wires are described. The methods show how to code a reduced number of nanoscale wires through the use of rotation group codes. The methods further show how to generate different code permutations through random misalignment and how to promote uniform code probability selection.

Abstract: The present invention provides a nitride semiconductor device. The nitride semiconductor device comprises an n-type nitride semiconductor layer formed on a nitride crystal growth substrate. An active layer is formed on the n-type nitride semiconductor layer. A first p-type nitride semiconductor layer is formed on the active layer. A micro-structured current diffusion pattern is formed on the first p-type nitride semiconductor layer. The current diffusion pattern is made of an insulation material. A second p-type nitride semiconductor layer is formed on the first p-type nitride semiconductor layer having the current diffusion pattern formed thereon.

Abstract: A technique to form metallic nanodots in a two-step process involving: (1) reacting a silicon-containing gas precursor (e.g., silane) to form silicon nuclei over a dielectric film layer; and (2) using a metal precursor to form metal nanodots where the metal nanodots use the silicon nuclei from step (1) as nucleation points. Thus, the original silicon nuclei are a core material for a later metallic encapsulation step. Metallic nanodots have applications in devices such as flash memory transistors.

Abstract: A composition and method for fabricating and tuning a dopant based core-shell semiconductor having a quantum dot core with an excitation band-gap are provided. A quantum dot core composed of an alloy of cadmium sulfide (CdS) and zinc sulfide (ZnS) as semi-conductor materials include a dopant of manganese (Mn) added to the core and an outer shell of zinc sulfide (ZnS). The dopant based core/shell quantum dot semiconductor of the present invention allows the fine tuning of an excitation band-gap, covering a wide range (from 2.4 eV to ˜4 eV). When doped with Mn, these alloy Qdots emit bright yellow/orange light. Tuning of the excitation band is accomplished by changing the alloy composition of the core. Based on photophysical studies a new core/shell/shell model is provided, in place of the traditional core/shell model. Due to the interfacial diffusion of the cations from the core and shell an intermediate alloy layer is formed providing an inner shell; this inner shell layer is the real host of the dopant ions.

Abstract: Provided is an optical semiconductor device, which includes a GaAs substrate (or a semiconductor substrate) 20; an n-type contact layer (or a doping layer) 21 formed on one surface 20a of the GaAs substrate 20; an active layer 25 formed on top of the n-type contact layer 21 and including at least one quantum dot 23; a p-type contact layer (or a contact layer) 26 formed on top of the active layer 25 and being of an opposite conduction type to the n-type contact layer 21; an insulating layer 29 formed on top of the p-type contact layer 26 and including a first opening 29a whose size is such that a contact region CR of the p-type contact layer 26 lies within the first opening 29a; a p-side electrode layer 33c formed on top of the contact region CR of the p-type contact layer 26 and on top of the insulating layer 29 and including a second opening 33a lying within the first opening 29a; and a n-side electrode layer (or a second electrode layer) 37 formed on the other surface 20b of the GaAs substrate 20.

Abstract: The present invention is to fabricate a flip-chip diode which emits a white light. The diode has a film embedded with silicon quantum dots. And the white light is formed by mixing colorful lights through the film.

Abstract: A method of fabricating a semiconductor device having high output power and excellent long-term reliability by preventing thermal adverse influence exerted at the time of window structure formation is provided. The method comprises a 1st step of forming predetermined semiconductor layers 2 to 9 containing at least an active layer 4b consisting of a quantum well active layer on a semiconductor substrate 1; a 2nd step of forming a first dielectric film 10 on a first portion of the surface of the semiconductor layers 2 to 9; a 3rd step of forming a second dielectric film 12 made of the same material as that of the first dielectric film 10 and having a density lower than that of the first dielectric film 10 on a second portion of the surface of the semiconductor layers 2 to 9; and a 4th step of heat-treating a multilayer body containing the semiconductor layers 2 to 9, the first dielectric film 10, and the second dielectric film 12 to disorder the quantum well layer below the second dielectric film 12.

Abstract: The invention is a method of producing an array, or multiple arrays of quantum dots. Single dots, as well as two or three-dimensional groupings may be created. The invention involves the transfer of quantum dots from a receptor site on a substrate where they are originally created to a separate substrate or layer, with a repetition of the process and a variation in the original pattern to create different structures.

Abstract: A quantum dot manipulating method and a generation/manipulation apparatus are provided which can control the size of a large number of generated quantum dots on or below the order of percent which is required for optical applications of the dots. Quantum dots are generated by shining a dot production laser (4a) onto a solid object (3) in a quantum dot production/manipulation apparatus (1) containing superfluid helium (7) therein. A dot manipulation laser (5a) is shone onto the generated quantum dots to manipulate the quantum dots.

Abstract: A method of forming a nanostructure having the form of a tree, comprises a first stage and a second stage. The first stage includes providing one or more catalytic particles on a substrate surface, and growing a first nanowhisker via each catalytic particle. The second stage includes providing, on the periphery of each first nanowhisker, one or more second catalytic particles, and growing, from each second catalytic particle, a second nanowhisker extending transversely from the periphery of the respective first nanowhisker. Further stages may be included to grow one or more further nanowhiskers extending from the nanowhisker(s) of the preceding stage. Heterostructures may be created within the nanowhiskers. Such nanostructures may form the components of a solar cell array or a light emitting flat panel, where the nanowhiskers are formed of a photosensitive material.

Abstract: The present invention is to provide a “fabricating method for quantum dot active layer of LED by nano-lithography” for fabricating out a new active layer of LED of nano quantum dot structure in more miniature manner than that of the current fabricating facilities to have high quality LED with features in longer light wavelength, brighter luminance and lower forward bias voltage by directly using the current fabricating facilities without any alteration or redesign of the precision.

Abstract: A process for forming nanostructures comprises generating charged nanoparticles with an electrospray system in a vacuum chamber and introduction of the charged nanoparticles to a region proximate to a charge pattern, so that the particles adhere to the charge pattern in order to form the feature. Two- or three-dimensional nanostructures may be formed by rapidly creating a charge pattern of nanoscale dimensions on a substrate using a normal electron beam or a microcolumn electron beam, generating high purity nanoscale or molecular size scale building blocks of a first type that image the charge pattern using the electrospray system, and then optionally sintering the building blocks to form the feature.

Abstract: A method and device for a heterostructure self-assembled quantum dot based on inherent strain present in underlying self-assembled quantum dots for the purpose of modification and control of the properties of the self assembled quantum dots structures formed on semiconductor surfaces.

Abstract: An electronic device includes a primary nanowire of a first conductivity type, and a secondary nanowire of a second conductivity type extending outwardly from the primary nanowire. A doped region of the second conductivity type extends from the secondary nanowire into at least a portion of the primary nanowire.

Abstract: Provided is a semiconductor light emitting diode that uses a silicon nano dot and a method of manufacturing the same. The semiconductor light emitting diode includes a light emitting layer that emits light; a hole injection layer formed on the light emitting layer; an electron injection layer formed on the light emitting layer to face the hole injection layer; a metal layer that includes a metal nano dot and is formed on the electron injection layer; and a transparent conductive electrode formed on the metal layer. Amorphous silicon nitride that includes the silicon nano dot is used as the light emitting layer.

Abstract: A composite material that may be used for a thin membrane is disclosed. This composite material includes first material that has a quasi-periodic system of vertical trenches (nanotrenches) with wavelength period that may be in the range between 20 and 500 nm. These nanotrenches are formed as openings between bordering elongated elements. The nanotrenches are at least partially filled with a second material that has physical-chemical characteristics substantially different from the first material.

Abstract: A method of forming patterned thin films includes the steps of providing a porous membrane and a solution including a plurality of solid constituents and at least one surface stabilizing agent for preventing the solid constituents from flocculating out of suspension. The solution is dispensed onto a surface of the membrane. The solution is then removed by filtration through the membrane, wherein a patterned film coated membrane comprising a plurality of primarily spaced apart patterned regions are formed on the membrane. In one embodiment the method further includes the step of blocking liquid passage through selected portions of the membrane to form a plurality of open membrane portions and a plurality of blocked membrane portions before the dispensing step. The dispensing step includes ink jet printing the solution. An article having a patterned nanotube-including film thereon includes a substrate, and a patterned nanotube including film disposed on the substrate.

Abstract: A method of batch fabrication using established photolithographic techniques allowing nanoparticles or nanodevices to be fabricated and mounted into a macroscopic device in a repeatable, reliable manner suitable for large-scale mass production. Nanoparticles can be grown on macroscopic “modules” which can be easily manipulated and shaped to fit standard mounts in various devices.

Abstract: A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.

Abstract: Provided is a nonvolatile memory device and a method of manufacturing the same. The nonvolatile memory device includes a semiconductor substrate on which a source, a drain, and a channel region are formed, a tunneling oxide film formed on the channel region, a floating gate formed of a fullerene material on the tunneling oxide, a blocking oxide film formed on the floating gate, and a gate electrode formed on the blocking oxide film.

Abstract: Provided are a charge trap memory device including a substrate and a gate structure including a charge trapping layer formed of a composite of nanoparticles, and a method of manufacturing the charge trap memory device.

Abstract: By bringing a tip of an AFM into contact with the surface of a GaAs substrate or an AlGaAs substrate, for example, applying a negative bias to the tip, and applying a positive bias to the GaAs substrate or the AlGaAs substrate, a donut-shaped oxide film is formed. Then, the oxide film is removed. As a result, a ring-shaped groove is formed in the surface of the GaAs substrate or the AlGaAs substrate. The oxide film can be removed by chemical etching, ultrasonic cleaning with water, a treatment with atomic hydrogen in a vacuum, or the like. Thereafter, a semiconductor film (InAs film or InGaAs film, for example) is epitaxially grown in the groove. Then, a capping layer which covers the semiconductor film and the GaAs substrate or the AlGaAs substrate is formed.

Abstract: The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.

Abstract: Lattice mismatched epitaxy and methods for lattice mismatched epitaxy are provided. The method includes providing a growth substrate and forming a plurality of quantum dots, such as, for example, AlSb quantum dots, on the growth substrate. The method further includes forming a crystallographic nucleation layer by growth and coalescence of the plurality of quantum dots, wherein the nucleation layer is essentially free from vertically propagating defects. The method using quantum dots can be used to overcome the restraints of critical thickness in lattice mismatched epitaxy to allow effective integration of various existing substrate technologies with device technologies.

Abstract: In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.

Abstract: A practically realizable semiconductor magnetic body having a flat-band structure is disclosed. The semiconductor magnetic body is formed by semiconductor quantum dots arranged on lattice points such that electrons can transfer between neighboring quantum dots and the electron energy band contains a flat-band structure, where each quantum dot is a structure in which electrons are confined inside a region which is surrounded by high energy potential regions, and the flat-band structure is a band structure in which energy dispersion of electrons has hardly any wave number dependency.