Abstract: A plasma processing apparatus includes a stock unit, a processing unit, and an alignment chamber. The stock unit supplies and collects a conveyable tray formed with a plurality of housing holes in each of which a wafer is housed. In the processing chamber, plasma processing is executed on the wafers housed in the tray supplied from the stock unit. The alignment chamber is provided with a rotating table on which the tray before being subjected to the plasma processing is set to perform positioning of the wafers on the rotating table. A housing state determination unit of a control device determines whether or not the wafer is misaligned with respect the housing hole of the tray based on a height detected by height detecting sensors.

Abstract: An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.

Abstract: A III-nitride edge-emitting laser diode is formed on a surface of a III-nitride substrate having a semipolar orientation, wherein the III-nitride substrate is cleaved by creating a cleavage line along a direction substantially perpendicular to a nonpolar orientation of the III-nitride substrate, and then applying force along the cleavage line to create one or more cleaved facets of the III-nitride substrate, wherein the cleaved facets have an m-plane or a-plane orientation.

Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate. In an illustrative implementation, a laser diode is oriented on a GaN substrate wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001>direction predominantly towards either the <11 20> or the <1 100> family of directions. For a <11 20> off-cut substrate, a laser diode cavity may be oriented along the <1 100> direction parallel to lattice surface steps of the substrate in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For a <1 100> off-cut substrate, the laser diode cavity may be oriented along the <1 100> direction orthogonal to lattice surface steps of the substrate in order to provide a cleaved laser facet that is aligned with the surface lattice steps.

Abstract: A semiconductor light-emitting device is disclosed. The semiconductor light-emitting device comprises a multilayer epitaxial structure disposed on a semiconductor substrate. The semiconductor substrate has a predetermined lattice direction perpendicular to an upper surface thereof, wherein the predetermined lattice direction is angled toward [0 11] or [01 1] from [100], or toward [011] or [0 11] from [ 100] so that the upper surface of the semiconductor substrate comprises at least two lattice planes with different lattice plane directions. The multilayer epitaxial structure has a roughened upper surface perpendicular to the predetermined lattice direction. The invention also discloses a method for fabricating a semiconductor light-emitting device.

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane <110> direction of the (011) DSB layer is aligned with an in-plane <110> direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane <100> directions of the (001) base substrate, followed by recrystallization using the base substrate as a template.

Abstract: The semiconductor device 1 comprises a housing 12 which has a recess 24 in the front surface 1; a pair of lead electrodes 20 which have the distal ends 34 exposed in the recess 24, protrude from the external surface of the housing 12, and are bent along the bottom surface 16 of the housing 12; and a semiconductor element 36 which is housed in the recess 24 and is electrically connected to the pair of lead electrodes 20. The housing 12 has grooves 30 which are formed on the pair of side surfaces 18 which adjoin the front surface 14 and the bottom surface 16 on the right and left sides so as to penetrate the housing 12 from the top surface 28 toward the bottom surface 16 of the housing 12. The grooves 30 preferably have width substantially equal to the thickness of the lead electrode 20. The grooves 30 are more preferably formed to be flush with the distal ends 34 of the lead electrode 20.

Abstract: The invention relates to a method for contacting a flexible sheet to a first element with improved lateral alignment. The method includes a step of measuring a first lateral misalignment after establishing a first contact between the flexible sheet and either of the first element and a sheet parking surface called anchor in the first stage. If the 5 misalignment exceeds a predetermined threshold the flexible sheet is parked at the anchor such that it is not in contact with the first element, and the relative position of the first element and the anchor is altered during the second stage for correcting the mismatch during a contact between the flexible sheet and the first element to be established within the next step of the method. During the steps of shifting the contact point to obtain the second stage 10 the contacting process is more accurate and reproducible than the process for establishing the initial contact.

Abstract: A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.

Abstract: A display substrate includes a signal line, a thin-film transistor (“TFT”), a key pattern, a light-blocking pattern, a color filter, a pixel electrode and an alignment key. The signal line and the key pattern are formed on a substrate. The TFT is electrically connected to the signal line. The light-blocking pattern is formed on the substrate and covers the signal line, the TFT and the key pattern. The color filter is formed in a unit pixel area of the substrate. The pixel electrode is formed on the color filter and is electrically connected to the TFT. The alignment key is formed on the light-blocking pattern, and a position of the alignment key on the substrate corresponds to a position of the key pattern on the substrate.

Abstract: An assembly and method of making the same wherein the assembly incorporates a rare-earth oxide film to form a [110] crystal lattice orientation semiconductor film. The assembly comprises a substrate, a rare-earth oxide film formed on the substrate, and a [110]-oriented semiconductor film formed on the rare-earth oxide film. The rare-earth oxide film having a [110] crystal lattice orientation. The substrate has a [001] crystal lattice orientation.

Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate (201). In an illustrative implementation, a laser diode is oriented on a GaN substrate (201) wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <1120> or the <1100> family of directions. For a <1120> off-cut substrate, a laser diode cavity (207) may be oriented along the <1100> direction parallel to lattice surface steps (202) of the substrate (201) in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For <1100> off-cut substrate, the laser diode cavity may be oriented along the <1100> direction orthogonal to lattice surface steps (207) of the substrate (201) in order to provide a cleave laser facet that is aligned with the surface lattice steps.

Abstract: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.

Abstract: A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed on the GaN substrate, a semiconductor device, and a method of manufacturing the GaN substrate are provided. A GaN substrate has a main surface and contains a low-defect crystal region and a defect concentrated region adjacent to low-defect crystal region. Low-defect crystal region and defect concentrated region extend from the main surface to a back surface positioned on the opposite side of the main surface. A plane direction [0001] is inclined in an off-angle direction with respect to a normal vector of the main surface.

Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

Abstract: Continuous wave laser apparatus with enhanced processing efficiency is provided as well as a method of manufacturing a semiconductor device using the laser apparatus. The laser apparatus has: a laser oscillator; a unit for rotating a process object; a unit for moving the center of the rotation along a straight line; and an optical system for processing laser light that is outputted from the laser oscillator to irradiate with the laser light a certain region within the moving range of the process object. The laser apparatus is characterized in that the certain region is on a line extended from the straight line and that the position at which the certain region overlaps the process object is moved by rotating the process object while moving the center of the rotation along the straight line.

Abstract: A light emitting diode includes a substrate tilted toward first and second directions simultaneously, a first cladding layer formed with a semiconductor material of a first conductive type on the substrate, an active layer formed on the first cladding layer, and a second cladding layer formed with a semiconductor material of a second conductive type on the active layer, wherein concavo-convexes are formed on the interfaces of the first cladding layer, the second cladding layer, and the active layer.

Abstract: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.

Abstract: A method for sidewall etching includes providing a substrate having a trench defined therein, with the trench having fill material disposed over a bottom thereof, along a sidewall thereof, and at the trench opening. The fill material along the sidewall of the trench and at the trench opening is removed without removing the fill material disposed over the bottom of the trench. The fill material along the sidewall and at the trench opening may be removed without removing the fill material disposed over the bottom of the trench by inhibiting a reaction between an etchant and the fill material over the bottom of the trench. The reaction between the etchant and the fill material may be inhibited by causing an air bubble to form at the bottom of the trench. The air bubble may be formed by inverting the substrate, and immersing the inverted substrate in an etchant.

Abstract: A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate areas. After this physical separation, only the first area is amorphized. A donor wafer is placed in contact with the first and second areas. The semiconductor device is annealed to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas. The donor wafer is removed and at least one semiconductor structure is formed in each of the first and second physically separate areas. In another form, the separate regions are a bulk substrate and an electrically isolated region within the bulk substrate.

Abstract: It is an object of the present invention to provide a semiconductor laser device with high-yielding in which a clack generated in an epitaxial growth layer is restrained and to the manufacturing method thereof, the semiconductor laser device includes a GaN substrate 1, an n-type GaN layer 2, an n-type AlGaN cladding layer 3, a n-type GaN guide layer 4, an InGaN multiple quantum well active layer 5, an undoped-GaN guide layer 6, a p-type AlGaN electron overflow suppression layer 7, a p-type GaN guide layer 8, a SiO2 blocking layer 9, an Ni/ITO cladding layer electrode 10 as a transparent electrode, a Ti/Au pad electrode 11, and a Ti/Al/Ni/Au electrode 12. The SiO2 blocking layer 9 is formed above the InGaN multiple quantum well active layer 5 so as to have an opening. The Ni/ITO cladding layer electrode 10 is formed inside the opening, and which is transparent for the light from the InGaN multiple quantum well active layer, and serves as a cladding layer.

Abstract: Continuous wave laser apparatus with enhanced processing efficiency is provided as well as a method of manufacturing a semiconductor device using the laser apparatus. The laser apparatus has: a laser oscillator; a unit for rotating a process object; a unit for moving the center of the rotation along a straight line; and an optical system for processing laser light that is outputted from the laser oscillator to irradiate with the laser light a certain region within the moving range of the process object. The laser apparatus is characterized in that the certain region is on a line extended from the straight line and that the position at which the certain region overlaps the process object is moved by rotating the process object while moving the center of the rotation along the straight line.

Abstract: A purpose of the invention is to provide a manufacturing method for a semiconductor substrate in which a high quality strained silicon channel can easily be formed without sacrificing the processing efficiency of a wafer and to provide a manufacturing method for a semiconductor device wherein the driving performance of a PMOS transistor, in addition to that of an NMOS transistor, can be improved. The invention provides a manufacturing method for a semiconductor substrate with the steps of: forming a SiGe film on the top surface of a substrate having a silicon monocrystal layer in the (111) or (110) plane direction as the surface layer; introducing buried crystal defects into the above described substrate by carrying out ion implantation and annealing treatment; and forming a semiconductor film on the above described SiGe film.

Abstract: In a semiconductor pressure sensor manufacturing method of disposing an etching mask (50) at one-face (11) side of a monocrystal silicon substrate 10 in which the face-direction of the one face 11 corresponds to the (110)-face, and then carrying out anisotropic etching to form a recess portion (20) and a diaphragm (30) at the bottom surface side of the recess portion (20), the etching mask (51) is designed to have a cross-shaped opening portion (51) at which a first area extending along the <110> crystal axis direction and a second area extending along the <100> crystal axis direction cross each other, the area of the opening portion (51a) of the overlap area between the first and second areas in the opening portion (51) being set to be smaller than the area of the diaphragm (30).

Abstract: A method and apparatus for reducing or eliminating the formation of air pockets or voids in a flowable material provided in contact with at least one substrate. The flowable material is provided in a non-horizontal direction and flows from a lower portion to an upper portion. As a result, the flowable material is provided uniformly with a single, uniform flow front due to gravity acting thereon and gravity thereby substantially preventing voids and air pockets from forming in the flowable material. In one embodiment, the at least one substrate is provided in the cavity of a transfer mold in which the cavity is filled from a gate at a lower portion of the cavity to a vent at an upper portion of the cavity. In another embodiment, a bumped semiconductor device is attached to a substrate having a gap therebetween, in which the gap is oriented longitudinally perpendicular to a horizontal plane so that the flowable material may fill the gap in a vertical direction.

Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.

Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

Abstract: The present invention is related to a method for producing micromachined devices for use in Microelectromechanical Systems (MEMS), comprising the steps of providing a crystalline wafer, and processing from said wafer at least one micromachined device comprising at least one elongated opening and/or cavity, having a longitudinal axis, so that said longitudinal axis is at an angle to a direction which lies along the intersection of the front plane of the wafer and a cleavage plane, said cleavage plane being defined as a plane along which cleavage of the wafer is most likely to occur.

Abstract: Between a source/drain heavily-doped diffusion layer and a region below a side face of a gate electrode in an epitaxial semiconductor substrate, an extension heavily-doped diffusion layer where N-type As ions are diffused is formed to have shallower junction than the source/drain heavily-doped diffusion layer. A pocket heavily-doped diffusion layer where P-type indium ions, that is, heavy ions having a relatively large mass number, are diffused is formed under the extension heavily-doped diffusion layer.

Abstract: A light emitting diode is made by a compound semiconductor in which light is emitted from an active region with a multiple quantum well structure. The active region is sandwiched by InGaAlP-based lower and upper cladding layers. Emission efficiency of the active region is improved by adding light and electron reflectors in the light emitting diode. These InGaAlP-based layers are grown epitaxially by Organometallic Vapor-Phase Epitaxy (OMVPE) on a GaAs substrate with a misorientation angle toward <111>A to improve the quality and surface morphology of the epilayer and performance in light emitting. The lower cladding layer of first conductivity type forms on a misoriented substrate with the same type of conductivity. Light transparent and current diffusion layers with a second conductivity is formed on top of the upper cladding layer for the spreading of current and expansion of the emission light.

Abstract: A method of forming a shallow trench isolation region in a silicon wafer which results in the elimination of long range slip dislocations in the wafer and reduces leakage current across the isolation regions. Long shallow trenches are formed in a silicon wafer at a 45 degree angle to the (111) plane of the wafer. This is achieved by moving the primary flat of the wafer to the (100) plane prior to the formation of the trenches, which causes the bottom edges of the long trenches to intersect with several (111) planes, so that stresses do not propagate along any one single (111) plane. The trenches are then filled with an insulative material, such as oxide.

Abstract: A new method of producing strained crystalline semiconductor microelectronic devices. Microelectronic devices can either be formed within a membrane, prior to straining or processed after straining. The method includes the steps of straining a membrane along at least one axis and straining using wafer-bonding techniques.

Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.

Abstract: A method of producing a strained crystalline semiconductor microelectronic device(s). Microelectronic device(s) are formed within a membrane. The method includes the steps of straining a membrane along at least one axis and bonding the membrane to a base substrate.

Abstract: Apparatuses and methods for use in adjusting a substrate centering system to center a substrate on a rotatable chuck in a semiconductor processing machine, the chuck including at least one reference point. One apparatus comprises a plate configured to be placed on the chuck and at least one centering mark formed on the plate, wherein the at least one centering mark is configured so that it may be compared to the at least one reference point on the chuck to determine if the plate is centered. The plate often is at least partially transparent so that its position relative to the at least one reference point on the chuck may be seen.

Abstract: A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate where silicon surfaces have at least two different crystallographic orientations of the silicon crystal. Atomic oxygen (O) is formed for oxidizing the surfaces. An oxide is formed on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.

Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film has features that it exhibits {110} orientation and that almost all crystal lattices have continuity at a crystal boundary. This type of grain boundaries greatly contribute to improving the carrier mobility, and make it possible to realize semiconductor devices having very high performance.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.

Abstract: A method for determining the crystal orientation of a wafer using anisotropic etching in which an etching mask having mask openings such as circle scale marks arranged one beside the other is applied in relation to a preexisting marking of the wafer. Mask openings are configured in a double-T shape and are arranged one beside the other so that their first, transversely extending segments and the second transversely extending segments are situated at a predetermined distance apart and the areas connecting the segments are situated equidistant. The crystal orientation is determined with the distance of the two particular adjacent mask openings, the intervening space of which is least undercut, from the preexisting marking.

Abstract: Partial wafer processing is achieved by down loading the wafer map of the whole wafer from a host (12) and if the partial wafer contains the reference die (14) move table to a locator die (15) and upload locator die coordinates to wafer map data host (16) and remove other partial wafer die coordinates from the map (17). If the partial wafer does not have the reference die and is not the last partial wafer, position wafer table to auxiliary reference die (18), validate the auxiliary reference die position (19) and compute auxiliary reference die coordinates from locator die coordinates (20) and move wafer table to locator die (22) and upload locator die coordinates to wafer map data host (23) and then using auxiliary reference die and locator die coordinates as information remove other partial wafer die coordinates from the map (24).

Abstract: Partial wafer processing is achieved by down loading the wafer map of the whole wafer from a host (2) and display the whole wafer in the die bonder monitor (3) move the wafer table to a first die pickup position (4) and move the display cursor to the first die pickup position (5) and teach two limit die coordinates in X direction (6) and teach two limit die coordinates in Y direction (7) and then using limit die coordinates as information remove other partial wafer die coordinates from the map (8) and select die pickup sequence (9).

Abstract: A process for producing a semiconductor device comprising the steps of forming a titanium film having a (002) orientation, forming a titanium nitride film on the titanium film to such a thickness as allows the titanium nitride film to follow the orientation of the titanium film, and forming an aluminum alloy film on the titanium nitride film, thereby to form a layer structure for wiring including the aluminum alloy film having a (111) orientation.

Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.

Abstract: This invention relates to the manufacture of a strain gauge sensor using the piezoresistive effect, comprising a structure (1) made of a monocrystalline material acting as support to at least one strain gauge (2) made of a semiconducting material with a freely chosen doping type. The strain gauge (2) is an element made along a crystallographic plane determined to improve its piezoresistivity coefficient. The structure (1) is a structure etched along a crystallographic plane determined to improve its etching. The strain gauge (2) is fixed to the structure (1) by bonding means capable of obtaining said sensor.

Abstract: The present invention relates to a method of cleaning wafers bonded on a fixing member in the form of an ingot, and then sliced by a wire saw from a direction perpendicular to the longitudinal dimension to form a row of wafers. The method includes: a cleaning process for cleaning the wafers bonded on the fixing member in the form of the row of wafers (workpiece W) by a cleaning mechanism; and a separating process includes: a softening step for softening an adhesive in a softening vessel; a first moving step for turning and moving a wafer in a planar direction using an end point of the glued portion of the wafer and the fixing member as the fulcrum; and a second moving step for further moving the wafer in a planar direction by a suction-cup rotary actuator to thereby bring the wafer out of the region of the row of wafers.

Abstract: A method of increasing the performance of an FET device by aligning the channel of the FET with the [110] crystal direction of a {100} silicon wafer. The {100} silicon wafer and the image of a lithographic mask are rotated 45.degree. relative to each other so that, instead of the channel being aligned parallel with the [100] crystal direction in the conventional fabrication, the channel is aligned approximately parallel with the [110] crystal direction. The mobility of the carriers is higher in the [110] crystal direction thereby increasing the performance of the FET with only a minor modification in the lithographic process. The novel FET results with its channel aligned approximately parallel with the [110] crystal direction.

Abstract: A method of fabricating ultra-small semiconductor devices including providing a mesa on a substrate. A plurality of overlying layers of semiconductor material are grown in overlying relationship to the mesa so that a perpendicular discontinuity is produced in the layers at the mesa sidewall and the first layer overlying the mesa is in contact with the last layer overlying the substrate adjacent the mesa. A spacer of nonconductive material is formed on the discontinuity and the plurality of overlying layers are etched, using the spacer as a mask, so as to form a contact area overlying the mesa and a contact area overlying the substrate adjacent the mesa, and a semiconductor device positioned adjacent the sidewall beneath the spacer and between the contact areas.