Producing Josephson Junction, Per Se (e.g., Point Contact, Bridge, Barrier Junction, Sis, Sns, Sss, Etc.) Patents (Class 505/329)
  • Patent number: 11309480
    Abstract: An ultra-thin film superconducting tape and method for fabricating same is disclosed. Embodiments are directed to a superconducting tape being fabricated by processes which include removing a portion of the superconducting tape's substrate subsequent the substrate's initial formation, whereby a thickness of the superconducting tape is reduced to 15-80 ?m.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 19, 2022
    Assignee: University of Houston System
    Inventor: Venkat Selvamanickam
  • Patent number: 11121303
    Abstract: Methods related to the treatment of a quantum computing device to increase channel mobility are described. An example method includes forming a superconducting metal layer on a surface of a wafer. The method further includes selectively removing a portion of the superconducting metal layer to allow a subsequent formation of a gate dielectric associated with the device, where the selectively removing causes a decrease in channel mobility associated with the quantum computing device. The method further includes prior to forming the gate dielectric, subjecting the wafer to a plasma treatment, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 14, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Maja C. Cassidy, Sebastian J. Pauka, Cioffi Nicole Allen
  • Patent number: 10460988
    Abstract: A removal method is provided for selectively removing a plurality of types of metal oxide films in a plurality of recesses formed in a substrate that is arranged in a processing chamber. The removal method includes repeatedly performing process steps of exposing the plurality of types of metal oxide films to BCl3 gas or a BCl3 gas plasma generated by introducing BCl3 gas, stopping introduction of the BCl3 gas and performing a purge process, exposing the plurality of types of metal oxide films and/or a plurality of types of metal films underneath the metal oxide films to one or more different plasmas, at least one of which is generated by introducing a single gas of an inert gas, and stopping introduction of the inert gas and performing the purge process.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 29, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Takeshi Itatani, Tadahiro Ishizaka, Kandabara Tapily, Kai-Hung Yu, Wanjae Park
  • Patent number: 10189745
    Abstract: Provided are a corrosion-resistant member and an electrostatic chuck device using the same, in which corrosion resistance to halogen corrosive gas such as fluorine corrosive gas or chlorine corrosive gas and plasma thereof is high, dielectric constant and volume resistivity are high, and dielectric loss is low. The corrosion-resistant member is formed of a composite oxide sintered compact containing aluminum, samarium, and a rare earth metal element other than samarium, in which the rare earth metal element other than samarium has an ionic radius of 0.88×10?10 m or more.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: January 29, 2019
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Kentaro Takahashi, Yoshiaki Moriya, Megumi Ootomo
  • Patent number: 9312052
    Abstract: Superconducting wire material, superconducting wire material connection structure, superconducting wire material connection method, and treatment method of superconducting wire material end are shown. According to one implementation, a superconducting wire material connection structure includes, a first superconducting wire material, a second superconducting wire material, and a third superconducting wire material. The first superconducting wire material and the second superconducting wire material each include an end provided with a concave section in which at least a superconducting layer is removed and a filling section in which filling material is filled in the concave section. The first superconducting wire material and the second superconducting wire material are positioned so that the ends oppose to each other. A third superconducting wire material is connected to both the first superconducting wire material and the second superconducting wire material.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 12, 2016
    Assignee: FURUKAWA ELECTRIC CO., LTD
    Inventors: Takaharu Mitsuhashi, Masashi Yagi, Ryo Nakayama
  • Publication number: 20150119252
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
    Type: Application
    Filed: March 7, 2013
    Publication date: April 30, 2015
    Inventors: Eric Ladizinsky, Jeremy P. Hilton, Byong Hyop Oh, Paul I. Bunyk
  • Publication number: 20150119253
    Abstract: A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 30, 2015
    Inventors: Daniel Yohannes, Alexander F. Kirichenko, John Vivalda, Richard Hunt
  • Publication number: 20150080223
    Abstract: A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 19, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Yuichi Yamazaki, Tadashi Sakai
  • Publication number: 20140315723
    Abstract: A method for fabricating a tunnel junction includes depositing a first electrode on a substrate, depositing a wetting layer having a thickness of less than 2 nm on the first electrode, using atomic layer deposition (ALD) to deposit an oxide layer on the wetting layer, and depositing a second electrode on the oxide layer. The wetting layer and the oxide layer form a tunnel barrier, and the second electrode includes a superconductor.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 23, 2014
    Applicant: The Regents of the University of California
    Inventors: Stephanie Moyerman, Brian Keating
  • Publication number: 20140302995
    Abstract: In one aspect, the present invention relates to a method of forming a reworkable, thermally conductive and electrically resistive material as a bonding structure in a module and application of the same. In certain embodiments, a homogeneous solution is prepared with an anisotropic structure, such as single-wall carbon nanotubes (SWCNTs), and an epoxy resin. The homogeneous solution is applied between a carrier and a chip of the module, and cured at a curing temperature for a curing time period to form a reworkable epoxy bonding layer, which has an anisotropic structure loading factor of about 0.1%-1.0% such that the reworkable epoxy bonding layer is thermally conductive and electrically resistive. When the chip is identified as a faulty chip, the module may be heated at a debonding temperature for a debonding time period such that the reworkable epoxy bonding layer debonds, and the chip becomes detachable from the carrier.
    Type: Application
    Filed: January 27, 2014
    Publication date: October 9, 2014
    Applicant: BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS
    Inventors: Ajay P. Malshe, Vishwas N. Bedekar, Ranjith John
  • Patent number: 8633472
    Abstract: Terahertz radiation source and method of producing terahertz radiation, said source comprising a junction stack, said junction stack comprising a crystalline material comprising a plurality of self-synchronized intrinsic Josephson junctions; an electrically conductive material in contact with two opposing sides of said crystalline material; and a substrate layer disposed upon at least a portion of both the crystalline material and the electrically-conductive material, wherein the crystalline material has a c-axis which is parallel to the substrate layer, and wherein the source emits at least 1 mW of power.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: January 21, 2014
    Assignee: Los Alamos National Security, LLC
    Inventors: Lev Boulaevskii, David M. Feldmann, Quanxi Jia, Alexei Koshelev, Nathan A. Moody
  • Patent number: 8178472
    Abstract: The present invention provides a superconducting device including a substrate, a first superconducting pattern formed on the substrate, an insulating pattern formed on the first superconducting pattern, and a second superconducting pattern formed at the uppermost level in the multilayered superconducting pattern. A barrier layer of a Josephson junction is formed on the lower side of, or within the second superconducting pattern. The second superconducting pattern constitutes a circuit element on the insulating pattern.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: May 15, 2012
    Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Yoshihiro Ishimaru, Yoshinobu Tarutani, Keiichi Tanabe
  • Publication number: 20110287944
    Abstract: Methods of forming superconducting devices are disclosed. In one embodiment, the method can comprise depositing a protective barrier layer over a superconducting material layer, curing the protective barrier layer, depositing a photoresist material layer over the protective barrier layer and irradiating and developing the photoresist material layer to form an opening pattern in the photoresist material layer. The method can further comprise etching the protective barrier layer to form openings in the protective barrier layer based on the opening pattern, etching the superconductor material layer based on the openings in the protective barrier layer to form openings in the superconductor material layer that define a first set of superconductor material raised portins and stripping the photoresist material layer and the protective barrier layer.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 24, 2011
    Inventors: Erica Folk, Patrick B. Shea, Andrew C. Loyd
  • Patent number: 8055318
    Abstract: A new family of superconducting materials with critical temperature up to 55 K have recently been discovered, comprising a crystal structure with atomic layers of iron and arsenic alternating with atomic layers of rare-earth oxide or alkaline earth. The present invention identifies structures for integrated circuit elements (including Josephson junctions) in these and related materials. These superconducting circuit elements will operate at a higher temperature than low-temperature superconductors such as niobium, and may be easier to manufacture than prior-art high-temperature superconductors based on copper-oxides.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: November 8, 2011
    Assignee: Hypres, Inc.
    Inventor: Alan M. Kadin
  • Patent number: 8032196
    Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where in cations within the material forming the barrier layer, a Cu content is in a range of 35 At. % to 55 At. % and an RE content is in a range of 12 At. % to 30 At. %, and the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: October 4, 2011
    Assignees: Chugoku Electric Power Co., Inc., International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Hironori Wakana, Seiji Adachi, Koji Tsubone, Keiichi Tanabe
  • Patent number: 7979101
    Abstract: It is possible to improve the negative resistance characteristic that can be expected when an SNS (superconductor-normal conductor-superconductor) structure is used as a structure unit for series connection. On the top of a first superconducting electrode, a second superconducting electrode is superimposed so as to sandwich an insulation film between the first and second superconducting electrodes, with parts of cross sections of the second superconducting electrode and insulation film placed on the top. A normal superconducting line electrically connects the first and second superconducting electrodes passing along the cross section of the insulation film, thereby constituting a structure unit having a single weak link. A plurality of such structure units connected in series are prepared. At the both ends of the series the first or second superconducting electrode is an element connected to a leading line.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: July 12, 2011
    Assignee: National Institute of Information and Communications Technology, Incorporated Administrative Agency
    Inventors: Toshiaki Matsui, Hiroshi Ohta, Akira Kawakami
  • Patent number: 7816303
    Abstract: A laminated superconductor wire includes a superconductor wire assembly, which includes a first superconductor insert comprising a first high temperature superconductor layer overlaying a first substrate and a second superconductor insert comprising a second high temperature superconductor layer overlaying a second substrate. The first and second superconductor inserts are joined together at their respective substrates. An electrically conductive structure substantially surrounds the superconductor wire assembly.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: October 19, 2010
    Assignee: American Superconductor Corporation
    Inventors: Cornelis Leo Hans Thieme, Alexis P. Malozemoff, Martin W. Rupich, Urs-Detlev Schoop, Elliott D. Thompson, Darren Verebelyi
  • Patent number: 7741634
    Abstract: A Josephson junction (JJ) device includes a buffered substrate comprising a first buffer layer formed on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer includes a hexagonal compound structure. A trilayer structure is formed on the buffered substrate comprising at least two layers of a superconducting material. A thin tunnel barrier layer is positioned between the at least two layers. The buffered substrate is used to minimize lattice mismatch and interdiffusion in the trilayer structure so as to allow the JJ device to operate above 20 K.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 22, 2010
    Assignee: Massachusetts Institute of Technology
    Inventors: Heejae Shim, Jagadeesh S. Moodera
  • Publication number: 20090247410
    Abstract: A Josephson junction (JJ) device includes a buffered substrate comprising a first buffer layer formed on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer includes a hexagonal compound structure. A trilayer structure is formed on the buffered substrate comprising at least two layers of a superconducting material. A thin tunnel barrier layer is positioned between the at least two layers. The buffered substrate is used to minimize lattice mismatch and interdiffusion in the trilayer structure so as to allow the JJ device to operate above 20 K.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 1, 2009
    Inventors: Heejae Shim, Jagadeesh S. Moodera
  • Publication number: 20080051292
    Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where in cations within the material forming the barrier layer, a Cu content is in a range of 35 At. % to 55 At. % and an RE content is in a range of 12 At. % to 30 At. %, and the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.
    Type: Application
    Filed: August 23, 2007
    Publication date: February 28, 2008
    Inventors: Hironori Wakana, Seiji Adachi, Koji Tsubone, Keiichi Tanabe
  • Patent number: 7060508
    Abstract: A superconductor integrated circuit (1) includes an anodization ring (35) disposed around a perimeter of a tunnel junction region (27) for preventing a short-circuit between an outside contact (41) and the base electrode layer (18). The tunnel junction region (27) includes a junction contact (31) with a diameter of approximately 1.00 ?m or less defined by a top surface of the counter electrode layer (24). The base electrode layer (18) includes an electrode isolation region (36) disposed approximately 0.8 ?m in horizontal distance from the junction contact (31) for providing device isolation.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: June 13, 2006
    Assignee: Northrop Grumman Corporation
    Inventor: George L. Kerber
  • Patent number: 6999806
    Abstract: A Josephson junction having a barrier layer sandwiched by two superconductors wherein the superconductors include one or more elements selected from the group of Y, La, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, one or more elements selected from the group of Ba, Sr and Ca, and Cu and oxygen, wherein the two superconductors each include at least five elements with compositions different from each other, or the barrier layer (5) includes one or more elements selected from the group of La, Nd, Sm and Eu, and one or more elements selected from the group of Y, Gd, Dy, Ho, Er, Tm, Yb and Lu.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: February 14, 2006
    Assignee: International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Seiji Adachi, Hironori Wakana, Keiichi Tanabe
  • Patent number: 6926921
    Abstract: One aspect of this disclosure relates to a method of building a superconductor device on a substrate, comprising depositing an imprint layer on at least a portion of the substrate. The imprint layer is imprinted to provide an imprinted portion of the imprint layer and a non-imprinted portion of the imprint layer. A superconductor layer is deposited on at least a portion of the imprinted portion of the imprint layer.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: August 9, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James Stasiak, Pavel Kornilovich
  • Patent number: 6839578
    Abstract: A method of forming a novel high temperature superconducting Josephson junction which is capable of achieving a formation of a Josephson junction having high characteristics conveniently and quickly without necessitating costly micromachining facilities. Two high temperature superconducting whisker crystals are crossed with each other on a substrate and subjected to thermal treatment to form a Josephson junction between the two high temperature superconducting whisker crystals.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: January 4, 2005
    Assignee: National Institute for Materials Science
    Inventors: Yoshihiko Takano, Takeshi Hatano, Akira Ishii, Syunichi Arisawa, Kazumasa Togano
  • Patent number: 6734454
    Abstract: A Josephson junction has inherent resistance which effectively shunts the junction and thereby obviates a separate shunt resistor and thus reduces surface area in an integrated circuit including a plurality of Josephson junctions. The Josephson junction comprises a stacked array of layers of Nb and a superconductor with Tc>9° K having a penetration depth greater than that of Nb, for example NbyTil-yN, with a layer of a conducting material having a resistivity between 200 &mgr;&OHgr;-cm, 1 &OHgr;-cm, such as TaxN in the stack. The Josephson junction can be formed on a supporting substrate such as silicon with a ground plane such as Nb on the substrate and an insulating layer such as SiO2 separating the ground plane from the stacked array.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: May 11, 2004
    Assignees: The Regents of the University of California, The Arizona Board of Regents
    Inventors: Theodore Van Duzer, Xiaoxan Meng, Nathan Newman, Lei Yu, Anupama Bhat Kaul
  • Patent number: 6682621
    Abstract: A method of forming a novel high temperature superconducting Josephson junction which is capable of achieving a formation of a Josephson junction having high characteristic conveniently and quickly without necessitating costly micromachining facilities. Two high temperature superconducting whisker crystals are crossed with each other on a substrate and subjected to thermal treatment to form a Josephson junction between the two high temperature superconducting whisker crystals.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: January 27, 2004
    Assignee: National Institute for Materials Science
    Inventors: Yoshihiko Takano, Takeshi Hatano, Akira Ishii, Syunichi Arisawa, Kazumasa Togano
  • Patent number: 6605225
    Abstract: A three-dimensional element is fabricated from a high-temperature superconductor. The method and apparatus can fabricate, for example, a single-electron tunnel device or an intrinsic Josephson device which utilize the layer structure peculiar to the high-temperature superconductor, with machining from the side surface of a monocrystal or thin film. In the focused-ion beam etching, a substrate holder which is rotatable about 360°, is rotated, at the minimum, through an angle of about 90°, and the thin film or monocrystal on the substrate is etched from the side surface thereof so as to fabricate the element. After the thin film or monocrystal is machined from above by means of an focused-ion beam to thereby form a bridge having a junction length, the sample is rotated by about 90° (270°). Subsequently, a multi-layer current path layer is formed through side-surface machining. The junction length is accurately controlled through measurement of the current path length from an image display.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: August 12, 2003
    Assignee: Japan Science and Technology Corporation
    Inventors: Tsutomu Yamashita, Sang-Jae Kim
  • Patent number: 6423473
    Abstract: A method for fabricating a high temperature superconducting step-edge Josephson junction includes the steps of: (i) preparing a step-edge on an SrTiO3 (STO) substrate; (ii) depositing a YBa2Cu3O7−x (YBCO) thin film on the step-edge substrate obtained; and (iii) forming a micro-bridge pattern on the, deposited metal thin film by photolithography and ion milling and then performing a heat treatment. This makes it possible to fabricate a step edge having a linear portion inclined at a large angle with good reproducibility during the ion-milling step. Furthermore, the two-stepped process of post heat treatment is carried out after the metal electrode of the junction is formed so that the high temperature superconducting step-edge junction can have its own characteristics enhanced.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: July 23, 2002
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gun Yong Sung, Jun Sik Hwang, Kwang Yong Kang
  • Patent number: 6388268
    Abstract: A semiconducting yttrium-barium-copper-oxygen(YBCO) device which locally converts a semiconducting YBCO film to a nonconducting YBCO film by a conductive atomic force microscope (AFM), a superconducting YBCO device which locally converts a superconducting YBCO film to nonsuperconducting YBCO by an AFM, and manufacturing methods thereof are provided. According to a method of manufacturing a semiconducting YBCO device or a superconducting YBCO device locally converted by an AFM tip, a voltage is applied to the local region of a semiconducting YBCO channel or a superconducting YBCO channel by an AFM tip. This can produce a nonconducting YBCO region or nonsuperconducting YBCO region to thereby manufacture a tunnel junction easily without any patterning process by microfabrication including photolithography and dry/wet etching.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: May 14, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byong-man Kim, Insang Song
  • Patent number: 6242387
    Abstract: High temperature superconductor composite thin film devices with easily moved Josephson vortices are described having high Tc and good magnetic vortex properties. A preferred composite material was YBCO/CeO2 thin film on a MgO substrate. The superconductor composites were preferably formed by off-axis co-sputtering. A surprising recovery in properties was seen after plasma etching with oxygen.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: June 5, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Edward J. Cukauskas, Laura H. Allen
  • Patent number: 6207067
    Abstract: A method for fabricating an oxide superconducting device includes the steps of: forming a V-shaped groove on a substrate by a converging ion beam and forming a barrier with reduced superconductivity on the oxide superconducting thin-film on the groove to form a Josephson Junction, wherein the irradiation ion amount of the converging ion beam is varied according to the position of the beam within the groove in such a manner that an inclination angle of the inclined portion of the substrate is fixed. An oxide superconducting device (a Josephson Junction device) having a high degree of flexibility in arrangement and with high reproducibility, and having a high degree of uniformity is provided.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: March 27, 2001
    Assignees: Mitsubishi Denki Kabushiki Kaisha, International Superconductivity Technology Center
    Inventors: Naoki Yutani, Katsumi Suzuki, Youichi Enomoto, Jian-Guo Wen
  • Patent number: 6188919
    Abstract: A SNS Josephson junction (10) is provided for use in a superconducting integrated circuit. The SNS junction (10) includes a first high temperature superconducting (HTS) layer (14) deposited and patterned on a substrate (18), such that the first HTS layer (14) is selectively removed to expose a top surface of the substrate (18) as well as to form an angular side surface (22) on the first HTS layer (14) adjacent to the exposed top surface of the substrate (18). Ion implantation is used to form a junction region (12) having non-superconducting properties along the angular side surface (22) of the first HTS layer (14). A second HTS layer (16) is then deposited and patterned over at least a portion of the first HTS layer (14) and the exposed top surface of the substrate (18), thereby forming a SNS Josephson junction.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: February 13, 2001
    Assignee: TRW Inc.
    Inventors: John R. LaGraff, James M. Murduck, Hugo W-K. Chan
  • Patent number: 6066600
    Abstract: A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ion-milling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: May 23, 2000
    Assignee: TRW Inc.
    Inventor: Hugo W. Chan
  • Patent number: 6004907
    Abstract: The present invention forms a superconducting junction using a cubic YBa.sub.2 Cu.sub.3 Ox thin film as a barrier layer. The present invention forms a first YBCO superconducting thin film, a SrTiO.sub.3 insulating layer thin film on the substrate, etches a side of them in the form of inclination, subsequently integrates a non-superconducting cubic YBCO barrier thin film, a second YBCO superconducting thin film, a SrTiO.sub.3 protecting layer thin film in series on the whole surface of the substrate, etches an opposite side of the etched part of the SrTiO.sub.3 insulating layer thin film in the form of inclination, fabricates a superconducting junction by forming a metal electrode to said aperture after forming apertures which expose said first YBCO superconducting thin film, the second YBCO superconducting thin film, fabricates a superconducting junction upon forming the metallic electrode to the apertures, and deposits a cubic YBa.sub.2 Cu.sub.3 Ox barrier thin film at a temperature of 600-650.degree. C.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: December 21, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong Dae Suh, Gun Yong Sung
  • Patent number: 5981443
    Abstract: A bicrystal substrate is formed by joining end faces of a first single crystal substrate and a second single crystal substrate, the end faces having different crystal orientations. A high critical temperature superconducting thin film is then epitaxially formed on the bicrystal substrate. The superconducting thin film is etched so as to form a first superconducting electrode on the first single crystal substrate, a second superconducting electrode on the second single crystal substrate, and a superconducting bridge across a joint between the first and second single crystal substrates and connecting the first electrode and the second electrode. A conductive film is formed on the superconducting bridge by vapor deposition, and is then etched so as to form a weak link on a part of the superconducting bridge over the joint.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: November 9, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Zhongmin Wen
  • Patent number: 5962866
    Abstract: A superconductor device has a substrate with an inclined surface that divides the substrate surface into a lower planar substrate surface and an upper planar substrate surface. A lower layer of an anisotropic superconductor material is epitaxially deposited on the lower planar substrate surface so that an a-axis of the anisotropic superconductor material of the lower layer is exposed at a top edge of the lower layer. An upper layer of an anisotropic superconductor material is epitaxially deposited on the upper planar substrate surface so that an a-axis of the anisotropic superconductor material of the upper layer is exposed at a top edge of the upper layer. A layer of a non-superconductor material overlies the inclined surface and the layers of anisotropic superconductor material.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: October 5, 1999
    Assignee: Biomagnetic Technologies, Inc.
    Inventors: Mark S. DiIorio, Shozo Yoshizumi, Kai-Yueh Yang
  • Patent number: 5945383
    Abstract: A method of producing a high temperature superconductor Josephson element and an improved SNS weak link barrier element is provided. A YBaCuO superconducting electrode film is deposited on a substrate at a temperature of approximately 800.degree. C. A weak link barrier layer of a nonsuperconducting film of N--YBaCuO is deposited over the electrode at a temperature range of 520.degree. C. to 540.degree. C. at a lower deposition rate. Subsequently, a superconducting counter-electrode film layer of YBaCuO is deposited over the weak link barrier layer at approximately 800.degree. C. The weak link barrier layer has a thickness of approximately 50 .ANG. and the SNS element can be constructed to provide an edge geometry junction.
    Type: Grant
    Filed: March 19, 1992
    Date of Patent: August 31, 1999
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: Brian D. Hunt
  • Patent number: 5916848
    Abstract: An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: June 29, 1999
    Assignee: TRW Inc.
    Inventor: Dale J. Durand
  • Patent number: 5885937
    Abstract: This invention provides a superconducting tunnel junction element showing satisfactory Josephson effect. The element includes a Bi-based layered compound such as Bi.sub.2 Sr.sub.2 (Ca.sub.0.6 Y.sub.0.4)Cu.sub.2 O.sub.8, Bi.sub.2 Sr.sub.2 Cu.sub.2 O.sub.6 and Bi.sub.2 Sr.sub.2 CaCu.sub.2 O.sub.8 as the barrier layer between the superconducting oxide electrodes. The structural matching of the superconducting oxide with the Bi-based compound is supposed to be good. Some kinds of Cu-based superconducting oxides such as YSr.sub.2 Cu.sub.2.7 Re.sub.0.3 O.sub.7, Sr.sub.2 CaCu.sub.2 O.sub.6 and (La.sub.0.9 Sr.sub.0.1).sub.2 CuO.sub.4 are used for the electrodes to obtain a Josephson element which can work at a high temperature. When using the superconducting oxides including Ba such as YBa.sub.2 Cu.sub.3 O.sub.7 for the electrode, forming a thin film between the electrode and the barrier is better to prevent Ba from reacting with Bi in the barrier layer.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: March 23, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Adachi, Masahiro Sakai, Akihiro Odagawa, Kentaro Setsune
  • Patent number: 5883051
    Abstract: A superconducting Josephson junction element including a first, a-axis oriented, superconductive metal oxide crystal grain having a first area of a {001} plane, and a second, c-axis oriented, superconductive metal oxide crystal grain having a second area of a {110} plane, wherein the first and second crystal grains are in contact with each other at the first and second areas to form a grain boundary therebetween.
    Type: Grant
    Filed: October 22, 1996
    Date of Patent: March 16, 1999
    Assignee: International Superconductivity Technology Center
    Inventors: Yoshihiro Ishimaru, Jian-Guo Wen, Kunihiko Hayashi, Youichi Enomoto, Naoki Koshizuka, Shoji Tanaka
  • Patent number: 5880069
    Abstract: A desired pattern is formed on a non-superconducting oxide film after the non-superconducting oxide film has been formed on a magnesia substrate. A superconducting oxide film is formed over the exposed parts of the substrate and the non-superconducting oxide film. The epitaxial orientation of the superconducting oxide film section on the non-superconducting oxide film is different from that of the superconducting oxide film section on the substrate. A tilt-boundary junction is produced at a boundary between the superconducting film sections which are different in epitaxial orientation from each other. Thus, a Josephson junction having a desired pattern can be obtained.
    Type: Grant
    Filed: February 1, 1994
    Date of Patent: March 9, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masao Nakao, Hiroaki Furukawa, Ryohkan Yuasa, Shuji Fujiwara
  • Patent number: 5877122
    Abstract: An oxide superconductor element, produced by forming a damaged region on a substrate surface by the Ga.sup.+ focusing ion beam method and then depositing an oxide superconductor thin-film over it, is characterized in that a NdBa.sub.2 Cu.sub.3 O.sub.7-y (0.ltoreq.y.ltoreq.0.5) oxide superconductor is used in a tunnel junction having a tunneling barrier region with weak superconductivity.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: March 2, 1999
    Assignees: Fujitsu Ltd., Sharp Kabushiki Kaisha, NEC Corp., International Superconductivity Technology Center
    Inventors: Yoshihiro Ishimaru, Yuuji Mizuno, Katsumi Suzuki, Youichi Enomoto, Shoji Tanaka
  • Patent number: 5872368
    Abstract: The order parameter of a superconductor is reduced by injecting spin-polarized carriers into the superconductor. The reduction in the order parameter is used to modulate the critical current of the superconductor. In a typical embodiment, a current is caused to flow through a superconductor. Spin polarized electrons are then injected into the path of the current in the superconductor by biasing a magnetic metal with respect to a terminal of the superconductor. The bias current may be varied to modulate the injection and thus the flow of current through the superconductor.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: February 16, 1999
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Michael Osofsky, Robert J. Soulen, Jr., Raymond Auyeung, James S. Horwitz, Doug B. Chrisey, Mark Johnson
  • Patent number: 5821200
    Abstract: A lattice matching device includes a substrate having thereon monocrystal regions having different lattice mismatches with respect to a LnBa.sub.2 Cu.sub.3 O.sub.x superconductor. A superconducting thin film is formed on the substrate, which film consists essentially of a superconductor of LnBa.sub.2 Cu.sub.3 O.sub.x wherein Ln represents yttrium or a lanthanide, and 6<x<7. The first and second superconducting thin film portions have different axes of orientation perpendicular to a main surface of the substrate, and arranged in contact with each other or at a distance which allows transmission of electron pairs from one to another.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 13, 1998
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masashi Mukaida, Shintaro Miyazawa, Junya Kobayashi
  • Patent number: 5811375
    Abstract: A superconducting multilayer interconnection comprises a substrate having a principal surface, a first superconducting current path of a c-axis orientated oxide superconductor thin film formed on the principal surface of the substrate, an insulating layer on the first superconducting current path, and a second superconducting current path of a c-axis orientated oxide superconductor thin film formed on the insulating layer so that the first and second superconducting current paths are insulated by the insulating layer. The superconducting multilayer interconnection further comprises a superconducting interconnect current path of an a-axis orientated oxide superconductor thin film, through which the first and second superconducting current paths are electrically connected each other.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: September 22, 1998
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5795849
    Abstract: A method for producing a superconductor assembly includes preparing a first bulk ceramic superconductor having a first essentially random pattern of superconductor domains of a copper-oxide ceramic superconductor and non-superconductor domains at a critical temperature, and preparing a second bulk ceramic superconductor having a second essentially random pattern of superconductor domains of a copper-oxide ceramic superconductor and non-superconductor domains at the critical temperature. The method further includes juxtaposing a first surface of the first bulk ceramic superconductor proximate with a first surface of the second bulk ceramic superconductor to form a superconductor assembly where superconductor domains of the first bulk ceramic superconductor and superconductor domains of the second bulk ceramic superconductor are only randomly aligned due to the different first essentially random pattern and second essentially random pattern.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 18, 1998
    Inventor: Paul L. Hickman
  • Patent number: 5789346
    Abstract: Method for manufacturing a superconducting device including forming on a surface of a substrate a non-superconducting oxide layer, a first oxide superconductor thin film, etching the first oxide superconductor thin film so as to form a concave portion, implanting ions to the first oxide superconductor thin film at the bottom of the concave portion so as to form an insulating region such that the first oxide superconductor thin film is divided into two superconducting regions by the insulating region, and forming a second oxide superconductor thin film on the insulating region and the two superconducting regions, which is continuous to the two superconducting regions.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: August 4, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5776863
    Abstract: A method of in-situ fabrication of a Josephson junction having a laminar structure, the method comprising the steps of: (1) etching a planar substrate to yield a first planar segment, a second planar segment and a ramp segment, the ramp segment connecting the two planar segments at an angle thereto and the substrate having a constantly-decreasing thickness in the ramp segment; (2) depositing a first superconductive layer on the substrate; (3) depositing a non-superconductive layer on the first superconductive layer; and (4) depositing a second superconductive layer on the non-superconductive layer, wherein both the first and second superconductive layers, and the non-superconductive layer are epitaxial with a c-axis in a direction substantially normal to the plane of the first and second planar segments, and the layers are of substantially uniform thickness in the three segments.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: July 7, 1998
    Assignee: TRW Inc.
    Inventor: Arnold H. Silver
  • Patent number: 5750474
    Abstract: A superconductor-insulator-superconductor Josephson tunnel junction, comprising: a single crystalline substrate having a perovskite crystal structure; a template layer formed of a b-axis oriented PBCO thin film on the substrate; and a trilayer structure consisting of a lower electrode, a barrier layer and an upper electrode, which serve as a superconductor, an insulator and a superconductor, respectively, the lower electrode and the upper electrode each being formed of an a-axis oriented YBCO superconducting thin film and having an oblique junction edge at an angle of 30.degree. to 70.degree., the barrier layer being formed of an insulating thin film between the two superconducting electrodes, can be operated at a low power with an exceptional speed in calculation and data processing.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: May 12, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gun-Yong Sung, Jeong-Dae Suh
  • Patent number: RE37587
    Abstract: A SQUID includes a substrate and a superconducting current path of a patterned oxide superconductor material thin film formed on a surface of the substrate. A c-axis of an oxide crystal of the oxide superconductor material thin film is oriented in parallel to the surface of the substrate.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: March 19, 2002
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Takashi Matsuura, Saburo Tanaka, Hideo Itozaki