Abstract: A superconducting quantum computing circuit package (1). The package contains a substrate (2) on which a circuit is formed, the circuit including a plurality of circuit elements. The substrate (2) includes holes (8) arranged between the circuit elements which extend through a thickness of the substrate (2). The package also contains a holder (3) with a surface (9) on which the substrate (2) is received, and a cover (4) arranged on an opposite side of the substrate (2). The holder (3) and the cover (4) are formed from a metal and/or a superconductor. The holder (3) also contains projections (12) arranged on and projecting from the surface (9). The projections (12) protrude through the holes (8) in the substrate (2) and contact the cover (4) so to suppress electromagnetic modes in the frequency range of operation of the quantum computing circuit.

Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.

Abstract: Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.

Abstract: Techniques related to a three-dimensional integration for qubits on crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first wafer comprising a first crystalline silicon layer attached to a first patterned superconducting layer, and a second wafer comprising a second crystalline silicon layer attached to a second patterned superconducting layer. The second patterned superconducting layer of the second wafer can be attached to the first patterned superconducting layer of the first wafer. A buried layer can comprise the first patterned superconducting layer and the second patterned superconducting layer. The buried layer can comprise one or more circuits. The superconductor structure can also comprise a transmon qubit that can comprise a Josephson junction and one or more capacitor pads comprising superconducting material. The Josephson junction can comprise a first superconductor contact, a tunnel barrier layer, and a second superconductor contact.

Abstract: There is provided a method for producing a substrate (600) suitable for supporting an elongated superconducting element, wherein, e.g., a deformation process is utilized in order to form disruptive strips in a layered solid element, and where etching is used to form undercut volumes (330, 332) between an upper layer (316) and a lower layer (303) of the layered solid element. Such relatively simple steps enable providing a substrate which may be turned into a superconducting structure, such as a superconducting tape, having reduced AC losses, since the undercut volumes (330, 332) may be useful for separating layers of material. In a further embodiment, there is placed a superconducting layer on top of the upper layer (316) and/or lower layer (303), so as to provide a superconducting structure with reduced AC losses.

Abstract: A low AC-loss multi-filament superconducting wire material of the invention includes an elongated base material, an intermediate layer formed on the base material; a superconducting layer formed on the intermediate layer, and a metal stabilizing layer formed on the superconducting layer, wherein a plurality of grooves extending along a long direction of the base material is formed in parallel in a width direction of the base material, and reach the intermediate layer from the metal stabilizing layer via the superconducting layer to expose the intermediate layer; and a difference ?d (=d1?d2) between a width d1 of the grooves at a lower part of the superconducting layer and a width d2 of the grooves at a lower part of the metal stabilizing layer is not more than 10 ?m.

Abstract: Methods of forming superconducting devices are disclosed. In one embodiment, the method can comprise depositing a protective barrier layer over a superconducting material layer, curing the protective barrier layer, depositing a photoresist material layer over the protective barrier layer and irradiating and developing the photoresist material layer to form an opening pattern in the photoresist material layer. The method can further comprise etching the protective barrier layer to form openings in the protective barrier layer based on the opening pattern, etching the superconductor material layer based on the openings in the protective barrier layer to form openings in the superconductor material layer that define a first set of superconductor material raised portins and stripping the photoresist material layer and the protective barrier layer.

Abstract: A multifilament high temperature superconductor with thick, striated stabilizer is disclosed, including a substrate, a buffer layer, a multifilament superconductor layer, and at least one thick stabilizer layer. Also disclosed are components incorporating superconducting tapes and methods for manufacturing same.

Abstract: Aspects of the invention can provide a patterning forming method capable of patterning a thin film by a simple and inexpensive device. The thin film can be provided on a base member including a photothermal conversion material that converts optical energy into thermal energy and light is radiated onto the base member to remove the thin film corresponding to a light-radiated region, such that the thin film is patterned.

Abstract: Provided are a novel halogenoacetoxyadamantane derivative which is useful as a modifying agent for a resin for a photoresist and a dry etching resistance-improving agent in the photolithography field, agricultural and medical intermediates and a compound for other various industrial products and a process for producing the same. To be specific, provided are a halogenoacetoxyadamantane derivative having a halogenoacetoxy group in an adamantane skeleton and a process for producing a halogenoacetoxyadamantane derivative, comprising the step of reacting a hydroxyl group of an adamantane skeleton with halogenoacetic halide or reacting the above hydroxyl group with a lithiation agent to derive it into a lithiumoxy group and then reacting halogenoacetic halide to introduce a halogenoacetoxy group.

Abstract: A method of fabricating high aspect ratio ceramic structures in which a selected portion of perovskite or perovskite-like crystalline material is exposed to a high energy ion beam for a time sufficient to cause the crystalline material contacted by the ion beam to have substantially parallel columnar defects. Then selected portions of the material having substantially parallel columnar defects are etched leaving material with and without substantially parallel columnar defects in a predetermined shape having high aspect ratios of not less than 2 to 1. Etching is accomplished by optical or PMMA lithography. There is also disclosed a structure of a ceramic which is superconducting at a temperature in the range of from about 10° K. to about 90° K. with substantially parallel columnar defects in which the smallest lateral dimension of the structure is less than about 5 microns, and the thickness of the structure is greater than 2 times the smallest lateral dimension of the structure.

Abstract: An SrTiO3 monocrystal substrate having a crystallographic plane (100) or (110) is anisotropically etched in an H3PO4 solution using an SiO2 thin film as an etching mask. The H3PO4 solution is maintained at a boiling point of approximately 150 deg. C. for increasing an etching rate and enhancing selectivity for protection with the SiO2 thin film mask.

Abstract: A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ion-milling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge.

Abstract: A method for forming a superconducting device using a selective etching technique on superconducting thin films. The method utilizes rapid etching which combines ion implantation with chemical etching. The portions of the superconducting film to be retained are masked from the ion implantation process. The chemical etching process then removes the implanted portions of the superconducting film at a much faster rate than the portions not implanted so that only the un-implanted portions remain. The resulting superconducting devices can be used, e.g., as nanostructures and nano tips, bolometers, multilayer RF coils, microwave waveguides and filters.

Abstract: A superconducting multilayer interconnection comprises a substrate having a principal surface, a first superconducting current path of a c-axis orientated oxide superconductor thin film formed on the principal surface of the substrate, an insulating layer on the first superconducting current path, and a second superconducting current path of a c-axis orientated oxide superconductor thin film formed on the insulating layer so that the first and second superconducting current paths are insulated by the insulating layer. The superconducting multilayer interconnection further comprises a superconducting interconnect current path of an a-axis orientated oxide superconductor thin film, through which the first and second superconducting current paths are electrically connected each other.

Abstract: A superconductor-insulator-superconductor Josephson tunnel junction, comprising: a single crystalline substrate having a perovskite crystal structure; a template layer formed of a b-axis oriented PBCO thin film on the substrate; and a trilayer structure consisting of a lower electrode, a barrier layer and an upper electrode, which serve as a superconductor, an insulator and a superconductor, respectively, the lower electrode and the upper electrode each being formed of an a-axis oriented YBCO superconducting thin film and having an oblique junction edge at an angle of 30.degree. to 70.degree., the barrier layer being formed of an insulating thin film between the two superconducting electrodes, can be operated at a low power with an exceptional speed in calculation and data processing.

Abstract: Fine epitaxial patterns of yttrium barium copper oxide on a strontium titanate substrate are provided by using a silicon nitride mask to define the pattern to be formed. A thin film of yttrium barium copper oxide is placed on the silicon nitride mask and exposed portions of strontium titanate substrate. Where the yttrium barium copper oxide is in contact with the silicon nitride mask, it is nonepitaxial in crystal structure. Where the yttrium barium copper oxide contacts the strontium titanate substrate in the openings, it is epitaxial in structure forming fine patterns that become superconducting below the critical transition temperature. A channel can be formed in the strontium titanate substrate. The epitaxial yttrium barium copper oxide pattern is formed in this channel to minimize possible exposure to the silicon nitride mask.

Abstract: A method for selectively etching insulative material composed of SrTiO3 or MgO in the presence of a copper oxide perovskite superconductive material includes treating the insulative material with a liquid selective etchant solution containing hydrogen fluoride in water for a period of time, the insulative material being etched at a substantially faster rate than the superconductive material etch rate, then treating the superconductive material exposed to the insulative selective with another etchant to remove a surface layer.

Abstract: Electrical interconnect structures comprised of high temperature superconducting signal layers on a substrate bonded to one another or optionally to a base substructure containing power and ground planes and processes for their preparation are disclosed.

Abstract: Disclosed are methods of forming superconducting devices including a type having a structure of a superconductor--a normal-conductor (or a semiconductor)--a superconductor, and a type having a superconducting weak-link portion between superconductors.The superconductors constituting the superconducting device are made of an oxide of either of perovskite type and K.sub.2 NiF.sub.4 type crystalline structures, containing at least one element selected from the group consisting of Ba, Sr, Ca, Mg, and Ra; at least one element selected from the group consisting of La, Y, Ce, Sc, Sm, Eu, Er, Gd, Ho, Yb, Nd, Pr, Lu, and Tb; Cu; and O. In addition, the c-axis of the crystal of the superconductor is substantially perpendicular to the direction of current flowing through this superconductor.

Abstract: A method for forming a patterned oxide superconductor thin film on a substrate comprises steps of forming a metal or semi-metal layer on a portion of the substrate, on which the oxide superconductor thin film will be formed, forming a layer of a material including silicon on a portion of the substrate, on which an insulating layer will be formed, removing the metal or semi-metal layer and depositing an oxide superconductor thin film over the substrate.

Abstract: A novel method for fabricating nanometer geometry electronic devices is described. Such Josephson junctions can be accurately and reproducibly manufactured employing photolithographic and direct write electron beam lithography techniques in combination with aqueous etchants. In particular, a method is described for manufacturing planar Josephson junctions from high temperature superconducting material.

Abstract: A process for patterning layered thin films comprising a bottom oxide superconductor (1) layer deposited on a substrate (3) and another thin film (2) deposited on the bottom superconductor layer and consisting of insulator, ordinary conductor or oxide superconductor having a different crystal orientation from the bottom superconductor layer. The bottom superconductor layer (1) is subjecting to heat-treatment before another thin film (2) is deposited thereon. The heat-treatment can be carried out under a first condition in ultra high-vacuum at a temperature which is lower than the oxygen-trap temperature (T.sub.trap) at which oxygen can enter into the oxide superconductor but is higher than a temperature which is lower by 100.degree. C. than the oxygen-trap temperature (T.sub.trap -100.degree. C.) or under a second condition in an atmosphere containing oxygen of high purity at a temperature which is higher than the oxygen-trap temperature (T.sub.

Abstract: This device or junction is essentially constituted by a substrate made from an electrically insulating material (2), a vertical wall (4) formed on the substrate and extending in a given direction (x), said wall being made from said insulating material, a superconducting material ribbon (8) in two separate parts (10, 12) located on either side of the wall and bearing on the latter, the ribbon being oriented in a direction perpendicular to the said direction, and two interconnection contacts (14, 16) respectively placed on the two portions of the ribbon.