Abstract: A wafer map is classified using the machine learning based model and a signature on the wafer map. The machine learning based model uses transfer learning. The machine learning based model can be trained using images from various sources that are extracted and augmented and their features extracted. These extracted features can be classified into defects that occur during semiconductor manufacturing.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: Systems and methods include a penetration testing device. The device comprises: a memory and a processing unit arranged to perform operations including: determining a device mode of operation from one of a headless and remote mode. In the headless mode, the operations comprise: determining a test script customized for a target application; in response to receiving an instruction to perform a penetration test, executing the script to perform the test on the application; based on results of the test, and compiling data indicative of security vulnerabilities in the application. And in the remote mode, the operations comprise: establishing a secure connection between the device and a remote computing device; receiving from the remote computing device instructions for performing a remote penetration test on the application; performing the instructions to determine the security vulnerabilities of the application; and providing the remote computing device with a compilation of the security vulnerabilities.

Abstract: The present disclosure models the testing of oilfield electronic equipment that operate in high temperature downhole environments (possibly with large vibrational loading) in order to quantify the damage to the electronic equipment over its expected operational lifetime. The simulated downhole environment is complex and includes coupled random vibration and thermal cycling followed by repeated shock at high temperature. In embodiments, the proposed methods and system measure non-linear damage accumulation of the electronic equipment in this simulated downhole environment.

Abstract: A testing apparatus for Data Storage Devices (DSDs) includes a chassis and at least one interface module configured to be removably inserted into the chassis and house a plurality of interface boards. Each interface board includes a DSD connector for connecting a DSD to the interface board and a backplane connector for connecting to a backplane for communicating with a respective computing unit. In one aspect, the at least one interface module includes a housing and a plurality of openings in a side of the housing with each opening configured to receive a respective interface board. A plurality of guide member pairs is positioned to guide respective interface boards when inserted into respective openings such that the backplane connector is located at a respective predetermined location for connecting to the backplane. In another aspect, the interface boards are removable from the interface module.

Abstract: A system and method are provided for automated application testing. The method is executed by a device having a communications module and includes requesting via the communications module, from a repository for a development environment, a current build file for each of at least one device type. The method also includes receiving via the communications module, from the repository, the current build file for each device type; deploying via the communications module, each current build file on a respective device type; and initiating at least one test on each device type based on a simulation of the device operating according to the current build file.

Abstract: A system converts high level source code into an arithmetic circuit that represents the functionality expressed in the source code, such as a smart contract as used in relation to a blockchain platform. The system processes a portion of high level source code to generate an arithmetic circuit. The arithmetic circuit comprises one or more arithmetic gates arranged to represent at least some of the functionality expressed in the source code.

Abstract: This application provides example scrambling-based data transmission methods and apparatuses. A scrambling manner is determined based on a sending waveform. The scrambling manner can include frequency domain scrambling, time domain scrambling, or time-frequency domain scrambling. To-be-scrambled data can be scrambled based on the scrambling manner, to obtain scrambled output data. The scrambled output data can be sent. The sending waveform can be a discrete Fourier transform spreading orthogonal frequency division multiplexing (DFT-s-OFDM) waveform or a cyclic prefix orthogonal frequency division multiplexing (CP-OFDM) waveform.

Abstract: In some examples, test relevancy prediction for code changes may include ascertaining files for a commit for a build, and for each test of a plurality of tests, determining a score based on a weight assigned to a file of the ascertained files. Test relevancy prediction for code changes may further include ordering each test of the plurality of tests according to the determined score, and identifying, based on the ordering of each test of the plurality of tests, tests from the plurality of tests for which the score exceeds a specified threshold. The identified tests may represent tests that are to be applied to the build.

Abstract: To implement a single-chip ultrasonic imaging solution, on-chip signal processing may be employed in the receive signal path to reduce data bandwidth and a high-speed serial data module may be used to move data for all received channels off-chip as digital data stream. The digitization of received signals on-chip allows advanced digital signal processing to be performed on-chip, and thus permits the full integration of an entire ultrasonic imaging system on a single semiconductor substrate. Various novel waveform generation techniques, transducer configuration and biasing methodologies, etc., are likewise disclosed. HIFU methods may additionally or alternatively be employed as a component of the “ultrasound-on-a-chip” solution disclosed herein.

Abstract: Described embodiments provide systems and methods for indicating virtual workspace performance on a graphical user interface of a computer system. In one such method, the computer system identifies one or more components of a virtual workspace executed on behalf of a user of the computer system, and analyzes a plurality of performance measurements of the identified one or more components of the virtual workspace. For each of the identified one or more components, the computer system determines an aggregated performance measurement for the component based on the plurality of performance measurements of the component, compares the aggregated performance measurement to a threshold, and selects a graphical indicator from a plurality of predetermined graphical indicators responsive to the comparison. The computer system renders, within a graphical user interface of the computer system, an identifier of the component and the selected graphical indicator.

Abstract: Embodiments include methods, systems and computer program products for performing a two-phase commit conformance test for a cloud based online transaction processing system (OLTP). Aspects include receiving, by a test case manager of the OLTP from a transaction manager of the OLTP, a transaction event including metadata regarding a transaction and determining a state of the transaction. Aspects also include identifying a test case based on the metadata and the state of the transaction and issuing state events to the transaction manager, wherein the state events are determined based on the test case. Aspects further include obtaining log information from the transaction manager and determining compliance by the transaction manager with the two-phase commit conformance test based at least in part on the log information.

Abstract: A network-based scalable production load test service may be implemented on a provider network including a plurality of computing devices in order to provide load testing for network-based production systems. In some embodiments, the plurality of computing devices is configured to receive a request to capture to a load test data repository items of transaction data for a network-based production service. In some embodiments, the plurality of computing devices is configured to capture to the load test data repository the items of transaction data. The transaction data include input to the network-based production service over a network. In some embodiments, in response to a load test specification received by the scalable production load test service, the plurality of computing devices is configured to dynamically allocate one or more resources to perform a load test of the network-based production service according to the load test specification.

Abstract: An apparatus and method are described for intelligent cloud based testing of graphics hardware and software. For example, one embodiment of an apparatus comprises: a hardware pool comprising a plurality of test machines to perform cloud-based graphics validation operations; a virtual resource pool comprising data associated a plurality of different graphics hardware resources; a resource manager to coordinate between the hardware pool and the virtual resource pool to cause one or more virtual machines (VMs) to be executed on one or more of the test machines using resources from the virtual resource pool; and a task dispatcher to dispatch graphics validation tasks to the VMs responsive to user input.

Abstract: Techniques for providing analytics regarding software application usage by client computers are presented. The techniques can include providing to at least one of a plurality of client computers at least one license for a usage of at least one of a plurality of software applications; storing transaction information for each usage of the at least one of the plurality of software applications by the at least one of the plurality of client computers, where the transaction information for a particular usage includes a respective chargecode, a respective site name, and a respective indication of license entitlement criteria test results for each of a plurality of license entitlement criteria tests; receiving search criteria at a user interface; searching stored transaction information using the search criteria to obtain search results; and providing the search results.

Abstract: A measuring device comprises a user input device, which comprises a first number of first user inputs for a user of the measuring device, a shortcut input device, which comprises a second number of shortcut user inputs for the user, and an assignment device, which assigns a respective one of the first user inputs to a respective one of the shortcut user inputs based on a received user command.

Abstract: A chip testing method, device, electronic apparatus, and computer readable medium are provided, relating to the field of chip testing. The method includes: determining a language rule of a chip to be tested; determining product and timing specifications of the chip to be tested; selecting a test pattern from a test pattern library according to the language rule and the product and timing specifications; generating a test code according to the product and timing specifications and the test pattern; and automatically testing the chip to be tested by using the test code. The chip testing method, device, electronic apparatus and computer readable medium can automatically generate a big-data test code for complex memories, and rapidly generate, in a standardized way, test codes for DDR4 memories of different specifications, thereby improving the efficiency of chip product verification analysis.

Abstract: Various examples are described for enrollment data visualization using enhanced graphical user interface elements. In one example, a management service can receive device data from devices enrolled with the management service, where the management service is configured to remotely oversee operation of the devices. The management service can determine operational metrics using the device data describing operation of the client devices and generate a metric visualization region for display in a user interface. In some examples, the metric visualization region can include a graph plotting the operational metrics over a predefined period of time and a circle having a predefined width circumscribing the graph, where at least a portion of the circle is filled based on the operational metrics.

Abstract: A system and computer-implemented method for container provenance tracking uses a build instruction file of a container image to output a new provenance document associated with the container image for distribution. For each file system layer of the container image specified in the build instruction file, an existing provenance document for the file system layer is inserted into the new provenance document. If there is no existing provenance document, information about each software component included in the file system layer is retrieved and inserted into the new provenance document.

Abstract: The present invention discloses an information management method and system for IC tests, and a storage medium. The method comprises steps of: providing test data generated by performing an IC test by an IC test platform, the IC test platform being an IC test platform having more than one stage, each stage of the IC test platform comprising a plurality of test devices: providing resource data related to the IC test, other than the test data; and analyzing the IC test according to the test data of the IC test and the resource data, to obtain result data related to the IC test. In this way, the present invention can provide technical support for utilizing the value of test data generated in IC tests.

Abstract: A method for equalizing command/address signals in a memory device includes receiving a status of a termination pin for a memory device and automatically performing equalization on signals received on a command/address bus channel of the memory device based on the status. An apparatus for equalizing command/address signals in a memory device includes an input buffer circuit configured to receive the signals from a command/address bus channel. The apparatus also includes a filter circuit configured to automatically perform equalization on the signals based on a status of a termination pin.

Abstract: A method for designing a system on a target device includes performing high-level compilation on a high-level language source file to generate a hardware description language (HDL) of the system and a serial testbench for the system. Verification is performed on the system that examines a parallel nature of the system by using the serial testbench.

Abstract: A method for monitoring communications between a device under test (DUT) and an automated test equipment (ATE) is disclosed. The method comprises programming an interface core and a protocol analyzer module onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test a DUT, wherein the interface core is operable to generate signals to communicate with the DUT using a protocol associated with the DUT. The method also comprises monitoring data and command traffic associated with the protocol in the interface core using the protocol analyzer module and storing results associated with the monitoring in a memory comprised within the protocol analyzer module. The method finally comprises transmitting the results upon request to an application program associated with the protocol analyzer module executing on the system controller.

Abstract: A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.

Abstract: Fast parallel CRC determination to support SSD testing includes a test data pattern generator for generating test data for storage onto a memory storage device under test (DUT), wherein the generator is operable to generate, every clock cycle, a respective N bit word comprising a plurality of M bit subwords, a digest circuit operable to employ a digest function on each N bit word to produce, every clock cycle, a respective word digest for each N bit word, and a storage circuit operable to store each N bit word along with an associated word digest to the DUT.

Abstract: Disclosed embodiments provide techniques for restoring an interrupted automated assistance session. Session contexts including pertinent metadata are periodically saved for each session, including a session reentry point. When a user calls an automated response system, metadata is collected from the user and compared with metadata from saved session contexts. If the user is determined to be associated with a saved session context, the user is connected to a conversation starting at the session reentry point, thereby eliminating the need to repeat the entirety of previously provided information.

Abstract: A method and apparatus for enabling control of execution of software applications is described. The method may include receiving an identifier for a user system, an identifier of a feature of an application running on the user system, and one or more definition values that define a treatment to be applied to the application feature. The method may also include storing the identifier for the user system, the identifier of the feature of an application running on the user system, and the definition values to be applied to the application feature. Furthermore, the method may include applying the definition values to the application feature at the user system based on the identifier for the user system stored in the memory, wherein the definition values configures the feature within the application while the application is running at the user system.

Abstract: A method for performing a secure boot of a data processing system, and the data processing system are provided. The method includes: processing a command issued from a processor of the data processing system, the command directed to a memory; determining that the command is a command that causes the memory to be modified; performing cryptographic verification of the memory; and incrementing a first counter in response to the determining that the command is a command that causes the memory to be modified. The data processing system includes a processor, a memory, and a counter. The memory is coupled to the processor, and the memory stores data used by a bootloader during a secure boot. The counter is incremented by a memory controller in response to a command being a type of command that modifies the data stored by the memory.

Abstract: An application module is read and parsed into a text file to store source code lines included into the implementation of the application module. The text file is analyzed and predicate conditions are identified in one or more of source code lines. Key values associated with a predicate condition from the predicate conditions are determined. Key values are associated with a key field defined for the application module. A plurality of paths of execution of the application module is determined based on the text file analysis and on the determined predicate conditions. A path includes one or more lines from the source code lines corresponding to a sequence of execution steps of the application module. Based on determining key values for the predicate conditions and the plurality of paths, generating test cases corresponding to the path and corresponding predicate conditions.

Abstract: A method and apparatus applies an action to a software application by determining a target object for the input action. The determination of the target object is performed by identifying the target object through socially identifying object information relative to a reference object. Then, the input action is applied to the target object.

Abstract: A method for receiving data using an FPGA receiver circuit comprises receiving payload data from a DUT using a first rate of a plurality of line rates during a first burst, wherein the DUT is communicatively coupled to the FPGA receiver circuit. The method further comprises transitioning to a power saving state at an end of the first burst and receiving synchronization data from the DUT using a second rate of a plurality of line rates during a second burst. Further, the method comprises establishing synchronization with a clock data recovery (CDR) circuit of the FPGA receiver circuit at the second rate and receiving payload data from the DUT at the second rate.

Abstract: An apparatus with a standard zone and a test zone, where the standard zone includes a standard execution environment providing access to genuine resources of the apparatus and the test zone includes a test execution environment providing access to mock resources, with a mock resource modeling a genuine resource of the apparatus. The application has access to the genuine resources when the application is executed in the standard zone. The application has access to the mock resources when the application is executed in the test zone and the application does not have access to the genuine resources when the application is executed in the test zone.

Abstract: An engineering tool coordination device includes a first tool interface configured to acquire first data having a first data format usable to an engineering tool, a data converter configured to convert the first data into second data usable to the control program, the second data having a second data format, a program provider configured to provide the second data to the control program, a second tool interface configured to acquire a first test request having a first test request format from the engineering tool, a test converter configured to convert the first test request into a second test request executable in the control program, the second test request having a second test request format, and a test manager configured to cause to execute an operation test program in the control program and to operate an operation test using the second data on a basis of the second test request.

Abstract: A computing system determines a first set of registers having constant next-state functions in the netlist. The computing system identifies an observable gate in fan-out of a register in the first set, wherein an observable gate is a gate that is critical to a verification or synthesis context. The computing system identifies a second set of reducible registers in the fan-in of the observable gate. The computing system modifies at least one of an initial value and a next-state function of at least one reducible register of the second set to reflect an observable value of the at least one reducible register observed at the observable gate. The computing system simplifies one or more logic gates implementing the observable gate and the fan-in of the observable gate by eliminating a reference to a constant next-state function register in the first set of registers.

Abstract: An architecture and processes enable computer learning and developing an understanding of arbitrary natural language text through collaboration with humans in the context of joint problem solving. The architecture ingests the text and then syntactically and semantically processes the text to infer an initial understanding of the text. The initial understanding is captured in a story model of semantic and frame structures. The story model is then tested through computer generated questions that are posed to humans through interactive dialog sessions. The knowledge gleaned from the humans is used to update the story model as well as the computing system's current world model of understanding. The process is repeated for multiple stories over time, enabling the computing system to grow in knowledge and thereby understand stories of increasingly higher reading comprehension levels.

Abstract: A system for performing an automated test is disclosed. The system comprises a first user computer operable to load a first test plan from a first user to a control server and a second user computer operable to load a second test plan from a second user to the control server. The system further comprises a tester comprising at least one rack for deploying a plurality of primitives. The control server is communicatively coupled to the first user computer, the second user computer and to the tester, wherein the control server is operable to allocate a first subset of primitives to the first test plan and manage execution of the first test plan on the first subset of primitives, and also operable to concurrently allocate a second subset of primitives to the second test plan and manage execution of the second test plan on the second subset of primitives.

Abstract: An optimization engine builds a set of test forms, called a pallet for use in a qualification test setting. The pallet is generated using a optimization engine programmed with constraints and goals for each test form in the pallet and for the pallet in general. A test information floor is set at the cut point of the test which causes test items to be focused at the area of the test where the pass/fail decision is made. Further constraints may be programmed to maximize the item diversity, that is, to spread the use of available test items as uniformly as possible.

Abstract: An application testing developer system provides a platform for generating real-time suggestions for allocating test cases to testers in a distributed environment based on monitored characteristics from previous testing of a test application. The application testing developer system includes a smart advisory tool that optimizes test case allocation in real-time, adaptively assigns incentives in real-time to test cases for prioritizing testing of certain test cases over others, and monitors and validates testing activities.

Abstract: A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.

Abstract: In a system operations management apparatus, a burden to a system administrator when providing a decision criterion in detection of a failure in the future is reduced. The system operations management apparatus 1 includes a performance information accumulation unit 12, a model generation unit 30 and an analysis unit 31. The performance information accumulation unit 12 stores performance information including a plurality of types of performance values in a system in time series. The model generation unit 30 generates a correlation model including one or more correlations between the different types of performance values stored in the performance information accumulation unit 12 for each of a plurality of periods having one of a plurality of attributes.

Abstract: Disclosed are an apparatus and a method for encryption. The apparatus includes a key table generator configured to generate random values based on a seed value and generate a key table including the generated random values; and an encryptor configured to apply the generated key table to a round function, generate a block encryption algorithm having a Feistel structure based on the round function, and encrypt a plaintext data block based on the generated block encryption algorithm.

Abstract: For discovering and safely transitioning transactors to a run mode, a message module determines if a message received from a communication master after a reset is a discovery message and determines if the message is an initial message received from the communication master. A command module, in response to the message not being the discovery message and the message being the initial message, activates a safety fault. In addition, the command module, in response to the message not being the discovery message and not being the initial message, determines whether the message comprises a valid safety command. In response to the message including a valid safety command, the command module enters the run mode.

Abstract: Disclosed are various approaches for injecting resources into wrapped applications. A computing device first obtains a compiled version of a target application package. The computing device then decompiles the compiled version of the target application package to generate a source code version of the target application package. Then, the computing device combines the source code version of the target application package with management component source code. Next, the computing device generates an application resource index. Subsequently, the computing device, modifies the management component source code based at least in part on the application resource index. Finally, the computing device compiles the combined source code version of the target application package and the management component source code to generate a managed application package.

Abstract: A method for characterizing a FM chirp signal generated by a device under test (DUT) is disclosed. The method comprises receiving a selection of a sample frequency and chirp duration for capturing the FM chirp signal. The method also comprises down converting the FM chirp signal and capturing the FM chirp signal using a digital pin electronics card. The method comprises obtaining a plurality of period measurements from the captured FM chirp signal using a timing measurement unit (TMU) of an automated test equipment (ATE) and converting each of the plurality of period measurements into corresponding frequency values.

Abstract: Optimization method with parallel computations, including performing multiple stages of calculating target function of P independent parameters using GPUs, wherein entire one-dimensional array of the calculated values of the target function of length ? j = 1 P ? W j that needs to be computed is divided into groups of size ? and calculated in parallel at L = ? j = 1 ? ? W j ? parameter points; a number of simultaneously calculated parameters ? in each group and a number of calculation points Wj of the target function at interval Dj for each j-th desired parameter in the group is selected based on a possible number of parallel calculations R=G·M·T, where G is number of GPUs, M is number of cores in each GPU, T is number of threads in each core; and outputting the calculated P parameters for the global extremum of the target function, wherein a full cycle of calculating points is carried out for consecutive iterations, defined as integer division ? L R ? , rounding up.

Abstract: Embodiments are generally directed to a protocol aware testing engine for high speed link integrity testing. An embodiment of a processor includes a processing core for processing data; and a protocol aware testing engine, wherein the protocol aware testing engine includes a protocol aware packet generator to generate test packets in compliance with an IO protocol, and a packet aligning and checking unit to align test packets generated by the packet generator with returned test packets and to compare the generated test packets with the returned data packets.

Abstract: Systems and methods for use in evaluating health associated with one or more applications are disclosed. One exemplary method includes exposing, by a computing device, an application programming interface (API) where the API defines a standard form associated with health indicator packets, and receiving, at the computing device, via the API, a health indicator packet for a health indicator from at least one application where the health indicator packet conforms to the standard form and including a value for the health indicator for the at least one application. The method also includes causing an interface to be displayed to a user where the interface includes a visual effect representative of the value, whereby the user is able to assess health of the application, at least in part based on the value, by viewing the interface.

Abstract: An integrated circuit (IC) automatic test system and an IC automatic test method storing test data in scan chains are revealed. The automatic test system includes at least one scan chain, a test controller and a test decompressor connected. Each scan chain consists of a storage portion with a plurality of scan units and a scan input corrector. The storage portion is for storing test data and the scan input corrector is used to adjust test patterns to be shifted into the scan chains. The test controller is for control of test flow while the test decompressor reconstructs and decompresses the test data stored in the storage portions of the scan chains to generate test patterns for the circuit under test. Thereby the IC electrical test is performed automatically and the test cost and the test cost is reduced.

Abstract: A test decompressor and a test method thereof for converting original input data of one single test input into test vectors for testing a circuit under test (CUT) containing scan chains are revealed. The test decompressor includes a test data spreader, a test configuration switch, and a test controller. The test data spreader converts the original input data into a plurality of test data. The test configuration switch receives the original input data and the plurality of test data and transfers these data to scan chains of the CUT. The test controller receives the original input data and outputs a select signal to the test configuration switch for switching current test configuration to another test configuration. The scan chains in the CUT are divided into several scan groups and the scan chains in each scan group share the same test data. Thus the test data volume can be significantly reduced.

Abstract: An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.