Including Program Set Up Patents (Class 702/123)
  • Publication number: 20140343886
    Abstract: Various embodiments provide systems, methods, and computer program products for diagnosing an operational functionality and/or performance of one or more building controlled systems. Such are generally configured to: correlate one or more control system points with one or more test variables associated with one or more test sequences; execute at least one of said one or more test sequences based at least in part upon said correlation and at least in part upon one or more user-defined parameters, the execution generating test data indicative of one or more results; at least in part analyze the test data to identify whether one or more discrepancies exist therein, the identification being based at least in part upon a comparison of the test data with the one or more control system point properties; and generate at least one of one or more reports, one or more alerts, or one or more instructions.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 20, 2014
    Inventors: Reed Berinato, Sandin Joseph Feuss
  • Patent number: 8892388
    Abstract: A method can include providing spatial data for a base case of a subsurface geologic formation; providing spatial data for a simulation case of the subsurface geologic formation; performing box counting for the spatial data for the base case; performing box counting for the spatial data for the simulation case; based on the box counting for the spatial data for the base case, determining a fractal dimension for the base case; based on the box counting for the spatial data for the simulation case, determining a fractal dimension for the simulation case; comparing the simulation case to the base case based at least in part on the fractal dimensions; and, based on the comparing, adjusting one or more simulation parameters to generate spatial data for an additional simulation case of the subsurface geologic formation. Various other apparatuses, systems, methods, etc., are also disclosed.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Schlumberger Technology Corporation
    Inventors: Sergio Fabio Courtade, Alina-Berenice Christ, Horacio Ricardo Bouzas
  • Patent number: 8878561
    Abstract: This invention is to detect defective products of semiconductor devices with high accuracy even when the characteristics of the semiconductor devices vary according to their positions on each of wafers.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuhiro Sakaguchi
  • Publication number: 20140324378
    Abstract: A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining information concerning a test class using a graphical user interface. Further, it comprises generating a first header file automatically, wherein the first header file comprises the information concerning the test class. Next, it comprises importing the first header file into a test plan operable to execute using a tester operating system wherein the test plan comprises instances of the test class. It further comprises, generating a second header file from the first header file automatically, wherein the second header file is a header file for the test class. The method also comprises validating the test plan using the tester operating system. Finally, the method comprises loading the test plan and a compiled module onto the tester operating system for execution, wherein the compiled module is a compiled translation of the test class.
    Type: Application
    Filed: April 30, 2013
    Publication date: October 30, 2014
    Applicant: Advantest Corporation
    Inventors: Mark ELSTON, Ankan PRAMANICK, Leon CHEN, Chandra PINJALA
  • Patent number: 8868371
    Abstract: A method for determining test sets of operating parameter values for an electronic component, the method including: determining a first set of intermediate sets, each intermediate set containing a combination of a first number of operating parameters of the electronic component; determining a second set of reference sets, wherein the second set contains a union of sets, each set comprising all possible combinations of parameter values for the parameters of a respective intermediate set; selecting a third set with a second number of test sets out of a set of predefined sets, wherein each predefined set comprises a different combination of the parameter values for all parameters from the predefined parameter set, such that the second set is a subset of a union of a number of sets, each set comprising all possible combinations of the first number of parameter values for all parameters of a respective test set.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Georg Pelz, Thomas Nirmaier
  • Patent number: 8856749
    Abstract: A test case can be run with actions from the test case being executed in multiple execution paths. This can be done with the aid of an action broker. For example, the broker may identify available automation implementations for the actions and use a priority list to select between available automation implementations for executing an action from the test case. The broker may also perform conversions of results of actions for use by implementations executing other actions in different execution paths, as well as passing results between implementations in different execution paths.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: October 7, 2014
    Assignee: Microsoft Corporation
    Inventors: Kristopher A. Makey, Ryan J. Cavanaugh, Dmitri A. Klementiev, Xuechun Li, Scott Louvau, Eric I Maino
  • Publication number: 20140288872
    Abstract: A testing device includes a display and a storage that stores a testing table. The testing table records at least one testing project and a test value of each of a plurality of parameters corresponding to the at least one testing project. Each parameter corresponding to a reference value range. The test value of each parameter is compared with the corresponding reference value range to determine whether the test value of each parameter is within the corresponding reference value range. The display displays test information of each test project according to a comparison result between the test value of each parameter and the corresponding value range.
    Type: Application
    Filed: March 18, 2014
    Publication date: September 25, 2014
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: DONG-YAN LI, BING ZHOU
  • Patent number: 8843341
    Abstract: In a method and to a device for identifying an erroneous algorithm (A), data output by a1) of the algorithm (A) to be tested and/or a2) a reference algorithm (B) are categorized, and the reference frequency (R(A), R(B)) at which data of at least one category (Kx) occur during operation for the case a1) of the algorithm (A) to be tested or for case a2) of the reference algorithm (B) is determined in a reference phase. The test frequency (T(A)) at which data of at least one category (Kx) occur during operation of the algorithm (A) to be tested is determined in a test phase. Finally, an error message is output if the deviation of the test frequency (T(A)) of at least one category (Kx) from the reference frequency (R(A), R(B)) of the same category (Kx) exceeds a specific threshold value (THR).
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: September 23, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventor: Frank Rometsch
  • Publication number: 20140257739
    Abstract: A method and apparatus are provided for implementing random content of program loops in random test generation for processor verification. A converged branch instruction stream is used by a test generator to ensure that all random conditional branches converge to a main program loop. A built in exception handling mechanism of the test generator enables program interrupts to converge to the main program loop. Mandatory read only registers applied to the test generator allow all register based storage addresses to use registers that maintain a value and thus stabilize the storage address translations through subsequent iterations of the loop. A global class restriction mechanism defines specific restricted instruction classes applied to the test generator avoids inherently problematic operations for the program loops. Machine state detection and restoration mechanisms in the test generator are provided to preserve storage addressability.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adi Dagan, Avishai Fedida, Olaf K. Hendrickson, Oz Hershkovitz
  • Patent number: 8825433
    Abstract: A method and system is provided for automatically generating valid at speed structural test (ASST) test groups. The method includes loading a netlist for an integrated circuit into a processor. The method further includes determining a plurality of clock domain crossings between a plurality of clock domains within the integrated circuit. The method further includes generating a first test group. The method further includes adding a first clock domain of the plurality of clock domains to the first test group. The method further includes adding a second clock domain of the plurality of clock domains to the first test group when the second clock domain does not have a clock domain crossing into the first clock domain.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Konda R. Baalaji, Malede W. Berhanu, Vikram Iyengar, Douglas C. Pricer
  • Patent number: 8825270
    Abstract: Provided is a method for determining the urgency for repairing a diagnostic condition in a vehicle. Upon determining the repair urgency, a driver may decide to continue driving (in the case of a “low” urgency determination), or cease driving (in the case of a “high” urgency determination). The urgency status may also enable a driver to shop around for the repair (in the event of a “low” urgency status), or to seek immediate assistance (in the event of a “high” urgency status).
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: September 2, 2014
    Assignee: Innova Electronics, Inc.
    Inventor: Leon Chen
  • Patent number: 8819493
    Abstract: Test configurations are generated based on information regarding hardware or software. A desired test configuration is selected. Test elements are automatically generated based on the desired test configuration, the test elements for testing at least one of the hardware or software. A plurality of test vectors is generated to test the hardware or software for the desired test configuration. The desired test configuration is converted to a script file. At least one of the hardware or software is automatically tested using the script file. Automatically testing the at least one of the hardware or the software includes using a first set of one or more test vectors from the plurality of test vectors to perform a plurality of test iterations of one or more of the actions of one or more generated test elements, and includes using at least a second set of one or more test vectors from the plurality of test vectors to determine the number of test iterations. A result of the testing is produced.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: August 26, 2014
    Assignee: The MathWorks, Inc.
    Inventors: Thomas Gaudette, Michelle T. Hirsh, Christian A. Portal
  • Patent number: 8793097
    Abstract: A graphical representation of a feature and associated tolerance includes a memory storing a description of the feature including at least one nominal dimension of the feature and an associated tolerance; a graphical representation of a nominal definition of the feature; and a graphical representation of the tolerance zones, derived from the nominal definition of the feature.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: July 29, 2014
    Assignee: Quality Vision International, Inc.
    Inventor: Kenneth L. Sheehan
  • Publication number: 20140207403
    Abstract: A method includes obtaining, via an inspection instrument, identifying information relating to an object that is to be inspected; querying, via the inspection instrument, a data source for relevant inspection information using at least the identifying information; receiving, via the inspection instrument, the relevant inspection information; and configuring the inspection instrument, via changes automatically implemented by the inspection instrument, based upon the received relevant inspection information.
    Type: Application
    Filed: January 22, 2013
    Publication date: July 24, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Jason Howard Messinger, Sekhar Soorianarayanan, Robert Carroll Ward, Michael Christopher Domke, Scott Leo Sbihli
  • Publication number: 20140207404
    Abstract: A method, computer program product, and computing system for, upon the occurrence of a computer-related event, comparing code utilized by one or more subsystems included within a scalable test platform to code available from a remote location. If the code available from the remote location is newer than the code utilized by one or more subsystems, the code available from the remote location is obtained, thus defining newer code. The code utilized by one or more subsystems is updated with the newer code.
    Type: Application
    Filed: January 24, 2013
    Publication date: July 24, 2014
    Applicant: LTX-Credence Corporation
    Inventors: William A. Fritzsche, Jeffery D. Currin, Russell Elliott Poffenberger, Timothy Alton, Michael Gordon Davis
  • Patent number: 8788239
    Abstract: Example methods, apparatus and articles to test batch configurations are disclosed. A disclosed example method includes identifying, using a processor, an execution path through a batch configuration of a process control system, generating a test plan for the execution path, stimulating the process control system to execute the test plan, and recording a result of the test plan.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: July 22, 2014
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: Brian Crandall, Dirk Thiele, Noel Bell
  • Patent number: 8781783
    Abstract: A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: July 15, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Hsien-Chuan Liang, Shen-Chun Li, Chun-Jen Chen, Shou-Kuo Hsu, Yung-Chieh Chen, Wen-Laing Tseng
  • Publication number: 20140172347
    Abstract: System, method and computer readable medium are described. The method may include obtaining user defined distribution traits characterizing a random sub-space of a space of assignments for a set of generative variables. The method may further include applying the user defined distribution traits on the space of assignments for a set of generative variables to generate the random sub-space of the space of assignments for a set of generative variables. The method may also include testing a device under test using the generated random sub-space of the space of assignments for a set of generative variables.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicants: XILINX INC., CADENCE DESIGN SYSTEMS, INC.
    Inventors: Efrat GAVISH, Yael Kinderman, Meirav O. Nitzan
  • Publication number: 20140163919
    Abstract: A testing device (10), an infusion pump or another medical device function testing method, to an anesthesia apparatus or respirator (AB) and to a computer program product are provided for testing the function of an infusion pump (G). The testing device (10) is preferably implemented on the anesthesia apparatus or respirator (AB) and comprises a memory (MEM), a test module (T) and a controller (C). The test module (T) sends a test command (20) to the infusion pump (FG), which sends a response (30) back to the controller (C) after execution of the command. The control (C) can then compare the response (30) received with a reference response (30?) for agreement in order to send a successful function test result.
    Type: Application
    Filed: November 26, 2013
    Publication date: June 12, 2014
    Applicant: DRÄGER MEDICAL GMBH
    Inventors: Jürgen MANIGEL, Markus STRÄHLE
  • Patent number: 8739089
    Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: May 27, 2014
    Assignees: Synopsys, Inc.
    Inventors: Hung Chun Chiu, Meng-Chyi Lin, Kuen-Yang Tsai, Sweyyan Shei, Hwa Mao, Yingtsai Chang
  • Patent number: 8731745
    Abstract: A method of generating a test sequence diagram includes: linking a first action of the plurality of actions with a second action of the plurality of actions and generating a test sequence diagram which maintains the linking.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: May 20, 2014
    Assignee: Aerojet Rocketdyne of DE, Inc.
    Inventors: Steven C. Fisher, Tim Brodeur
  • Publication number: 20140129173
    Abstract: Systems and methods described here include embodiments for generating component test code for use in an application test generation program used to test an application under test. Certain embodiments include a computer server running the application test generation program with an integrated custom engine and function libraries, the custom engine configured to allow a user to define a component, allow the user to select at least one application area, allow the user to define a component step for the defined component, wherein defining a component step includes, an object repository associated with the selected application area, at least one object option associated with the selected object repository, wherein the selection of the object option determines subsequent sets of object options for selection by the user, repeating, and to generate the component test code, via associations in the function libraries between component test code portions and the defined component steps.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 8, 2014
    Applicant: Software Development Technologies
    Inventor: Edward Francis KIT
  • Publication number: 20140107925
    Abstract: The present solution provides a new tool to facilitate the tracking of experiments and development of data-driven algorithms. The tool may obtain algorithms, parameters and data sets to execute one or more experiments to produce an outcome. The tool may identify differences between two or more experiments, such as differences in parameters, algorithms, or data sets to facilitate identifying the optimal combination of algorithms or parameters.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: Flyberry Capital LLC
    Inventors: Tsung-Yao Chang, Tsung-Hsiang Chang
  • Publication number: 20140107963
    Abstract: A method and apparatus for optimizing the yield of tested electronics devices is provided. A sample device is characterized to derive a specification for each device in the group. The sample size is chosen to provide reliable data and to minimize the effect of outlier devices on the characterization. After characterization, boundaries are set for the group of tested devices. Boundaries may be set based on voltages optimized for power consumption. The group of devices may be further subdivided into sub-groups based on the results of testing. The sub-groups are each assigned a unique code that reflects the results of the testing. This code is programmed into automated test equipment and is also stored in system software in order to ensure consistent values across the group of tested devices. The automated test equipment and system software are correlated using the same code to ensure higher test yield.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Sachin D. Dasnurkar, Prasannakumar Seeram, Prasad Rajeevalochanam Bhadri
  • Patent number: 8676530
    Abstract: A performance testing framework enables multiple components working together to test a deployed application automatically in an unattended manner and to analyze the test results easily. At very high level, the performance testing framework can run performance tests on a tested system with one or more variations without user intervention and save the test results and configuration metadata to a database for later analysis. Each of the variations is composed of a set of logical dimensions and values associated with each of those dimensions to be tested.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: March 18, 2014
    Assignee: Oracle International Corporation
    Inventors: Steven Leslie Roth, Matthew S. Maccaux
  • Patent number: 8670952
    Abstract: A non-destructive inspection (NDI) instrument includes a sensor connection system configured to receive test signals from at least two different types of NDI sensors which are configured to obtain test signals from an object being tested. The sensor connection system has sensor-specific connection circuits and at least one common sensor connection circuit. A data acquisition circuitry is coupled to the sensor connection and has sensor-specific data acquisition circuits and at least one common data acquisition circuit. It is further coupled to a common digital data processor which executes sensor-specific processing modules and at least one common processing module. A common display screen and user interface is coupled to the data processor and enables programs including sensor-specific user interface modules and at least one common user interface module. The sensor types preferably include all of or any combination of an ultrasound sensor, an eddy current sensor and acoustic sensor.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: March 11, 2014
    Assignee: Olympus NDT Inc.
    Inventor: Michael Drummy
  • Patent number: 8666691
    Abstract: Provided is a test apparatus that tests a device under test, comprising a testing section that stores a program in which commands to be executed branch according to detected branching conditions and that tests the device under test by executing the program; and a log memory that stores test results of the testing section in association with command paths of the program executed to obtain the test results. The testing section sequentially changes a characteristic of a test signal supplied to the device under test, and judges pass/fail of the device under test for each characteristic of the test signal, and the log memory stores a test result of the testing section in association with a command path of the program, for each characteristic of the test signal.
    Type: Grant
    Filed: May 30, 2011
    Date of Patent: March 4, 2014
    Assignee: Advantest Corporation
    Inventors: Shinichi Ishikawa, Tetsu Katagiri, Masaru Goishi, Hiroyasu Nakayama, Masaru Tsuto
  • Patent number: 8649995
    Abstract: A system and method for providing an efficient test case generator is disclosed. A test case project is established upon request from a user, via a user interface, to test an item. The test case project includes a plurality of fields and corresponding designated values to be tested. A first set of identified fields of the plurality are received, wherein the first set includes two or more fields identified by the user as having a dependent relationship with at least one another. A first relational field cluster for the first set of related fields and their values is created. A test case generation technique is performed on the first relational field cluster to compute all relevant test conditions for the first relation field cluster. Results of the computed test conditions for the first relational field cluster are displayed to the user via the user interface.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: February 11, 2014
    Assignee: Infosys Technologies, Ltd.
    Inventors: Nair Pradosh Thulasidasan, Tenkarai Sankaran Venkataramanan
  • Publication number: 20140039826
    Abstract: System and method for testing units under test (UUTs). A test sequence is provided that includes an acquisition sequence and a processing sequence. The acquisition sequence may include a sequence of acquisition functions for performing acquisitions on one or more UUTs. The processing sequence may include a sequence of processing functions for processing measurement data resulting from the acquisitions. Each acquisition function may be performed, including performing a plurality of acquisitions, thereby generating respective measurement data sets, and storing the respective measurement data sets in order of the acquisitions. Each processing function may be performed, including retrieving and processing each respective measurement data set in order of acquisition. At least one processing function of the processing sequence may be performed concurrently with at least one acquisition function of the acquisition sequence.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Inventors: Gerardo Orozco Valdes, Michael J. Lyons, Norman J. Kirchner, JR., Craig E. Rupp
  • Patent number: 8639467
    Abstract: A measuring system for determining a value of a physical or chemical, measured variable of a medium, includes: a base unit; at least one relay unit connected with the base unit and a sensor unit connected with the relay unit. The sensor unit includes a circuit having at least one microcontroller, at least a first memory region, and a second memory region. The upload software is embodied, in interaction with the microcontroller, to perform an updating of the basic software with at least one software module provided from the base unit. The relay unit includes a circuit having at least one microcontroller, and at least a first memory region, in which a basic software of the relay unit is stored. The circuit of the relay unit further includes a second memory region, in which an upload software of the relay unit is stored.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: January 28, 2014
    Assignee: Endress + Hauser Conducta Gesellschaft für Mess- und Regeltechnik mbH + Co. KG
    Inventors: Ronny Michael, Hermann Gunther, Sven-Matthias Scheibe, Hendrik Zeun
  • Publication number: 20140005974
    Abstract: A system and method for configuring a test for a program is provided. The method, for example, may include receiving, by a processor, an identification of an electronic device, retrieving, by the processor, a configuration of the electronic device from a memory, modifying, by the processor, at least one step of the test based upon the configuration of the electronic device.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 2, 2014
    Inventors: Kunal Vyas, Vijay Singh, Nataraj Paila, Scott Glaser
  • Publication number: 20130346011
    Abstract: A fault analysis method includes: using a matrix of two sets of microgrid power distribution networks to analyze and solve a fault current, and for various types of faults of the distributed power distribution system, obtaining appropriate boundary conditions to calculate a variety of different types of single or simultaneous fault currents of load points. The present invention may be further applied to a situation where a bus or impedance or parallel loop is added. The present invention has good robustness and execution speed, and requires small memory space for calculation of analysis and identification of a power flow fault of the distributed power distribution system, and may be actually applied to an instrument control system for identification and analysis of a fault of a large-scalemicrogrid distribution system.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Applicant: Institute of Nuclear Energy Research Atomic Energy Council, Executive Yuan
    Inventor: TING-CHIA OU
  • Patent number: 8612171
    Abstract: A method of automatic formulation by a computer of test cases for verifying at least one function of a piece of software in relation to a specification including requirements relating input values and output values of the software, the method including the steps of: distinguishing combinatorial requirements and sequential requirements; modeling combinatorial requirements by a truth table and sequential requirements by a finite state machine to obtain a modeled specification; establishing an operation matrix relating the input values of the software with a probability of them being in succession and a transition time between them; selecting the successions of input values to be tested by performing a Monte Carlo draw on the operation matrix; determining a test case including test rows relating each selected succession with the output values expected given the modeled specification; stopping the determination process when the test case being determined makes it possible to reach a predetermined threshold for
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: December 17, 2013
    Assignee: Johnson Controls Technology Company
    Inventors: Roy Awedikian, Bernard Yannou, Philippe Lebreton, Line Bouclier, Mounib Mekhilef
  • Patent number: 8606538
    Abstract: A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench is connected to the system and controlled in application of a command sequence established from at least one informal functional specification; while preparing the test, the informal functional specification, the command sequence, and a link identifying the informal functional specification from which the command sequence was established are all recorded so that after execution of the command sequence and after the test results have been recorded, it is possible to read the link and identify unambiguously the informal functional specification that corresponds to the test results obtained.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: December 10, 2013
    Assignee: Eurocopter
    Inventors: Gilles Cahon, Christian Gaurel
  • Publication number: 20130311128
    Abstract: An example of the invention is a test support system for supporting testing of a function of a program that works depending on a position of a mobile object in map information. A storage device holds event generation requirements information defining requirements for generation of an event in the program. The requirements specify a position designated in the map information and requirements on movement of the mobile object with respect to the designated position. A processor creates a plurality of test cases to be referred to in creating test data to be input to the program for checking whether the event is generated in accordance with the requirements with reference to the map information and the requirements. Each of the plurality of test cases specifies the designated position in the map information and movement of the mobile object with respect to the designated position.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 21, 2013
    Applicant: Hitachi Automotive Systems, Ltd.
    Inventors: Hideki TAKANO, Tsuneo SOBUE, Shunichiro FURUHATA
  • Patent number: 8589886
    Abstract: The present invention relates to a system and a method for creating hardware and/or software test sequences and in particular, to such a system and method in which modular building blocks are used to create, sequence and schedule a large scale testing sequence using a matrix like platform.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: November 19, 2013
    Assignee: Qualisystems Ltd.
    Inventors: Eitan Lavie, Assaf Tamir, Moshe Moskovitch
  • Patent number: 8554507
    Abstract: A method for obtaining an optimized process solution from a set of design of experiments in a cost effective manner is provided. An actual experiment is performed and data from the experiments is obtained. Through statistical analysis of the data, coefficients are obtained. These coefficients are input into an experiment simulator where input parameters and conditions are combined with the coefficients to predict an output for the input parameters and conditions. From simulated results, conclusions can be drawn as to sets of input parameters and conditions providing desired results. Thereafter, physical experiments utilizing the input parameters and conditions may be performed to verify the simulated results.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: October 8, 2013
    Assignee: Intermolecular, Inc.
    Inventor: Prashant B. Phatak
  • Publication number: 20130262019
    Abstract: A method includes designing probing signals for testing an alignment of actuators in a web manufacturing or processing system with measurements of a web of material being manufactured or processed by the system. The method also includes providing the probing signals during alignment testing to identify the alignment of the actuators with the measurements of the web. Designing the probing signals includes designing the probing signals based on both spatial and dynamic characteristics of the web manufacturing or processing system.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Applicant: Honeywell ASCa Inc.
    Inventors: Danlei Chu, Cristian Gheorghe
  • Publication number: 20130253876
    Abstract: A method and a control sequence determination device for the determination of a magnetic resonance system activation sequence including at least one high-frequency pulse sequence to be transmitted by a magnetic resonance system are provided. A current B0 map and optionally a target magnetization are acquired. In addition, a k-space trajectory type is determined. An error density is calculated in a k-space based on the current B0 map and optionally based on the target magnetization using an analytic function. This analytic function defines an error density in the k-space as a function of the current B0 map and optionally the target magnetization. Taking account of the error density in the k-space, a k-space trajectory of the specified k-space trajectory type is determined. The high-frequency pulse sequence is determined for the k-space trajectory in an HF pulse optimization process.
    Type: Application
    Filed: March 19, 2013
    Publication date: September 26, 2013
    Inventors: Josef Pfeuffer, Rainer Schneider
  • Patent number: 8538719
    Abstract: In a method for testing device descriptions for field devices of automation technology, a finite state machine is produced from a device description to serve as a basis for a test script. For testing the device description, the test script is executed, with data being sent to and received from the device description. In such case, it is tested whether desired values set in the test script agree with actual values delivered e.g. from the field device.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: September 17, 2013
    Assignee: CodeWrights GmbH
    Inventors: Immanuel Vetter, Michael Gunzert
  • Publication number: 20130238274
    Abstract: The present invention relates to a method (50) for controlling an integrated circuit (20) comprising a microprocessor, in which the integrated circuit (20) is configured to execute by default a general program, said integrated circuit being controlled by activation of a mode of operation of the integrated circuit, called “bootstrap mode”, in which said integrated circuit (20) executes a program for loading a specific program to be executed. The method (50) comprises: i) a step (51) of sending at least one bootstrap mode activation message to a test module (200) of the integrated circuit (20) via a test bus (310), ii) a step (52) of activating the bootstrap mode of the integrated circuit (20), executed by the test module (200) of the integrated circuit (20), and iii) a step (53) of loading the specific program via a communication bus (320) different from the test bus (310). The present invention also relates to an integrated circuit (20) and a computer (30) including such an integrated circuit (20).
    Type: Application
    Filed: August 18, 2011
    Publication date: September 12, 2013
    Applicants: CONTINENTAL AUTOMOTIVE GMBH, CONTINENTAL AUTOMOTIVE FRANCE
    Inventors: Bertrand Danet, Stéphane Laborie-Fulchic
  • Patent number: 8532953
    Abstract: A method and apparatus for determining a trigger in a test and measurement apparatus are provided. The method comprises the steps of loading a first trigger configuration to a first trigger element of the test and measurement apparatus and loading a second trigger configuration to a second trigger element of the test and measurement apparatus so that these trigger elements operate substantially simultaneously, It is then determined whether the input signal generates a trigger in accordance with the one or more trigger configurations.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: September 10, 2013
    Assignee: Teledyne LeCroy, Inc.
    Inventors: Anthony Cake, Peter J Pupalaikis, David Graef, William Driver, Michael Hertz, Laxmikant Joshi
  • Publication number: 20130231888
    Abstract: Provided is a test apparatus that tests a device under test, comprising a test module that communicates with the device under test to test the device under test; and a control apparatus that executes a plurality of test programs, causes the test module to perform tests corresponding respectively to the test programs, receives test results from the test module, and performs predetermined result processes on the test results. The control apparatus stores an execution order of the test programs, and executes at least a portion of the result processes in an order indicated by the stored execution order.
    Type: Application
    Filed: March 27, 2012
    Publication date: September 5, 2013
    Applicant: ADVANTEST CORPORATION
    Inventors: Hajime SUGIMURA, Takeshi YAGUCHI, Takahiro NAKAJIMA
  • Patent number: 8527232
    Abstract: Methods of diagnostic test pattern generation for small delay defects are based on identification and activation of long paths passing through diagnosis suspects. The long paths are determined according to some criteria such as path delay values calculated with SDF (Standard Delay Format) timing information and the number of logic gates on a path. In some embodiments of the invention, the long paths are the longest paths passing through a diagnosis suspect and reaching a corresponding failing observation point selected from the failure log, and N longest paths are identified for each of such pairs.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: September 3, 2013
    Assignee: Mentor Graphics Corporation
    Inventors: Ruifeng Guo, Wu-Tung Cheng, Takeo Kobayashi, Kun-Han Tsai
  • Patent number: 8521432
    Abstract: A performance assessment system for deep geologic repository for radioactive waste disposal is introduced to integrate a number of independent sub-system to perform the repository assessments in a systematic way under computer-based environment. Basically, the sub-system includes the input data file preparation sub-system for near-field/far-field multiple running, the near-field/far-field multiple running sub-system and the uncertainty and sensitivity analysis sub-system. With the system, the assessment for the deep geologic repository for radioactive waste disposal in many aspects can be achieved more completely and precisely.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: August 27, 2013
    Assignee: Institute of Nuclear Energy Research Atomic Energy Council
    Inventor: Shin-Jon Ju
  • Publication number: 20130218510
    Abstract: A method and structure for operating a magnetoresistive sensor system includes applying a set-reset process wherein the set-reset signal is phased through the magnetoresistive element in such a way that the set-reset field of each region is not released until the adjacent field is aligned. Starting at one end of the magnetoresistive element, the set-reset signal is activated. This aligns the domains directly underneath the first of the set-reset elements. Before this field is released, the adjacent set-reset is activated, which aligned the domains in the adjacent field. Once the adjacent field has been realigned, the set-reset field in the first region can be released, and the set-reset field in the next region can be activated. In this way, no more than two set-reset elements must be active at any one time.
    Type: Application
    Filed: February 1, 2013
    Publication date: August 22, 2013
    Applicant: mCube, Incorporated
    Inventor: mCube, Incorporated
  • Publication number: 20130218509
    Abstract: Customizing a test instrument. A plurality of pairs of code modules may be provided. Each pair of code modules may include a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware element of the test instrument. For each pair of code modules, the first code module and the second code module may collectively implement a function in the test instrument. User input may be received specifying modification of a second code module of at least one of the plurality of pairs of code modules. Accordingly, a hardware description may be generated for the programmable hardware element of the test instrument based on the modified second code module.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Inventors: Charles G. Schroeder, Christopher F. Graf, Ciro T. Nishiguchi, Nigel G. D'Souza, Daniel J. Baker, Thomas D. Magruder
  • Patent number: 8515706
    Abstract: A method and apparatus for controlling driving of a test device that analyzes a sample are provided. The method includes identifying a test device, executing a script containing a plurality of operations to be performed to analyze the sample contained in the test device, wherein the script includes a plurality of operation commands, wherein at least one operation command among the plurality of operation commands includes a conditional statement, and wherein at least one operation command among the plurality of operation commands is designated to be executed according to whether the conditional statement is satisfied.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: August 20, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Rip Lee, Hyug Rae Cho, Seok Ho Kim, Sung Hwa Lee
  • Publication number: 20130211770
    Abstract: A method for performing a plurality of tests on a device under test comprises performing a plurality of tests on a device under test. Each test of the plurality of tests comprises a foreground process and a background process. The foreground process comprises a setup process during which a desired test mode is set. The background process comprises an upload process during which data captured from the device under test is provided. The foreground process is executed with a higher priority than the background process, thereby minimizing a delay between a start of consecutive tests of the device under test.
    Type: Application
    Filed: April 8, 2011
    Publication date: August 15, 2013
    Inventors: Martin Dresler, Johannes Hauf, Martin Schmitz
  • Patent number: 8510714
    Abstract: A method, apparatus, and computer program product to implement integrated documentation and functional application testing are provided. An integrated test engine drives both functional application testing and documentation testing for the application. The integrated test engine uses documentation instructions, which are embedded with metadata and represent how to automate each step in the documentation and the expected results, and runs a series of tests that ensure that the application works as expected and that the documentation accurately reflects how the application works.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Amber Rebecca Field King, John Peter Merges, III, Diane Elaine Olson, Alwood Patrick Williams, III