Abstract: An extension to a simulator (801) that allows the user to specify real numbers, voltages, and currents (808) on ports of an electrical net is presented. The computer using the analog wire functionality routines (805), the routines for determining nets (804), the net manager (803), and the pin manager (802) resolves unspecified values on said electrical nets. The user may specify at least one value on said port and may specify whether said port is driven. The extension includes additional math functions (1901).

Abstract: A hybrid simulation model includes a real model, a bus interface and an acceleration model. The real model simulates a group of instructions. The acceleration model includes a trace generation unit, a trace replay unit, a selection unit, a snapshot generation and load unit and a virtual breakpoint control unit. The trace generation unit records at least one trace file of the real model in a first simulation. The trace replay unit reads and accordingly accesses the at least one trace file. The selection unit dynamically switches to perform a real simulation or a trace simulation. The snapshot generation and load unit generates at least one status snapshot file and loads the at least one status snapshot file to the real model in repeated simulations. The virtual breakpoint control unit controls the selection unit to switch between the trace simulation and the real simulation according to a virtual breakpoint.

Abstract: Software for controlling processes in a heterogeneous semiconductor manufacturing environment may include a wafer-centric database, a real-time scheduler using a neural network, and a graphical user interface displaying simulated operation of the system. These features may be employed alone or in combination to offer improved usability and computational efficiency for real time control and monitoring of a semiconductor manufacturing process. More generally, these techniques may be usefully employed in a variety of real time control systems, particularly systems requiring complex scheduling decisions or heterogeneous systems constructed of hardware from numerous independent vendors.

Abstract: Aspects of a method and system for traffic management via virtual machine migration include detecting an abnormal traffic pattern in traffic communicated by a first virtual machine that utilizes a first set of network resources. Responsive to the detection of the abnormal pattern, a second virtual machine that utilizes a second set of network resources may be initialized. The second virtual machine may take over functions performed by the first virtual machine and initialization of the second virtual machine is based on an analysis of the traffic. The second virtual machine may be initialized utilizing stored virtual machine state information in instances that the abnormal traffic is a result of a malicious attack. The second virtual machine may be initialized utilizing current virtual machine state information in instances that the abnormal traffic is not a result of a malicious attack.

Abstract: Software for controlling processes in a heterogeneous semiconductor manufacturing environment may include a wafer-centric database, a real-time scheduler using a neural network, and a graphical user interface displaying simulated operation of the system. These features may be employed alone or in combination to offer improved usability and computational efficiency for real time control and monitoring of a semiconductor manufacturing process. More generally, these techniques may be usefully employed in a variety of real time control systems, particularly systems requiring complex scheduling decisions or heterogeneous systems constructed of hardware from numerous independent vendors.

Abstract: A system, method, and computer program for validating a rule set for applicable checks of a part, comprising querying a validation rule set; correlating a part data to said validation rule set; comparing a part against said part data; and whereby said part is approved at an event, and appropriate means and computer-readable instructions.

Abstract: A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are b

Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract: A system and method for simulating a state of a distributed storage system is provided. A current state of a distributed storage system and replication policies for the objects in the distributed storage system is obtained. Proposed modifications to the current state of the distributed storage system are received. The state of the distributed storage system is simulated over time based on the current state of the distributed storage system, the replication policies for the objects in the distributed storage system, and the proposed modifications to the current state of the distributed storage system. Then reports relating to the time evolution of the current state of the distributed storage system are generated based on the simulation.

Abstract: Systems and methods for simulating and verifying a design are contemplated. Various embodiments determine a set of verification rules for a design, wherein the verification rules use a PSL or SVA syntax in a SPICE netlist to describ a property of the circuit design. The state of a circuit at a simulated first time, t1, can be determined. The state at the first time, t1, may be analyzed to determine if a triggering event has occurred. Based on the occurrence of the triggering event, the systems and methods can verify the state at the first time, t1, against the set of verification rules. Some embodiments of the systems and methods described herein can include a mixed-signal circuit including an analog portion and a digital portion, and the analog portion, the mixed-signal portion, or both, may be simulated and verified.

Abstract: In an embodiment, input data is received from a user and reference data is calculated based on an original simulation state. An adjustment amount is determined based on the difference between the input data and the reference data. An event value is generated via a probability function, and the event value is adjusted by the adjustment amount into an adjusted event value. A next simulation state is then determined based on the adjusted event value, and the next simulation state is presented to a user. In an embodiment, the adjustment amount is proportional to the difference. In this way, direct and realistic feedback to the user is provided via the simulation state, which positively reinforces correct behavior and negatively reinforces incorrect behavior, more so than does an unadjusted simulation.

Abstract: Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.

Abstract: An exemplary system and method are disclosed for interactively teaching software development processes to multiple users. The exemplary system may include a discrete event simulator for teaching software development that allows a software development team to simulate an entire software development project much faster than real time. The system teaches an entire software development team a set of formal or informal processes using a project simulation. In the course of using the system, each member of the team learns the processes, and together, the entire team learns how to use the processes as a team. The system enables each team member to learn software development processes as well as how those processes translate into team interactions in practice. The system also enables the team to learn how to apply the processes in difficult situations.

Abstract: Methods implementable in a computer system for simulating the transmission of signals across a plurality of data channels (bus) are disclosed. The disclosed techniques simulate the effects of Intersymbol Interference (ISI), cross talk, and Simultaneous Switching Output (SSO) noise by generating Probability Distribution Functions (PDFs) for each. The resulting PDFs are convolved to arrive at a total PDF indicative of the reception of data subject to each of these non-idealities. The total PDF, and its underlying terms, can be indexed to particular channels of the bus as well as to particular logic states. Use of the disclosed technique allows bit error rates and sensing margins to be determined with minimal computation and simulation.

Abstract: A non-transitory computer-readable recording medium stores therein a program that causes a processor to execute inputting a driving capability value, a lumped-constant capacitance value, and an input capacitance value included in the lumped-constant capacitance value, respectively defined in a circuit model, and further inputting a first delay time of the circuit model, based on the driving capability value and the lumped-constant capacitance value; setting in the circuit model, the driving capability value, the lumped-constant capacitance value, and the input capacitance value; acquiring a second delay time of the circuit model, by providing to a simulator, the circuit model having values set therein; calculating a relative evaluation value for the first delay time and the second delay time; and storing to a storage apparatus and as a delay time correcting coefficient, the relative evaluation value correlated with the driving capability value, the lumped-constant capacitance value, and the input capacitance

Abstract: Methods and apparatus are provided for use with thermal electric cooling devices (TECDs). An apparatus is mapped so as to identify the heat dissipating entities and zones thereof. A first cooling plan is devised in accordance with the mapping, the cooling plan being dependant upon TECDs. At least one other cooling plan is devised that is distinct from the first cooling plan. The coefficient of performance (COP) for each of the cooling plans is calculated. One of the cooling plans is selected and implemented in accordance with a comparison of the COPs. Precision, zone-oriented cooling is provided, avoiding excessive material scale and wasted energy.

Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Abstract: The compositional event based modeling of integrated applications (CINEMA) tool provides a way to extend a modeling environment using legacy event based applications, such as Graphical User Interface (GUI) APplications (GAPs). CINEMA allows modelers to extend the toolbox of the modeling environment by creating modeling elements that represent GUI objects of GAPs. CINEMA generates source code that allows an integrated system to control and manipulate the GUI objects of GAPs represented by the modeling elements used to create a model of the integrated system.

Abstract: A mechanism is provided in an integrated circuit simulator for tracking array data contents across three-value read and write operations. The mechanism accounts for write operations with data values and address values having X symbols. The mechanism performs writes to a tree data structure that is used to store the three-valued contents to the array. The simulator includes functionality for updating the array contents for a three-valued write and to read data for a three-valued read. The simulator also includes optimizations for dynamically reducing the size of the data structure when possible in order to save memory in the logic simulator.

Abstract: Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.

Abstract: Software for controlling processes in a heterogeneous semiconductor manufacturing environment may include a wafer-centric database, a real-time scheduler using a neural network, and a graphical user interface displaying simulated operation of the system. These features may be employed alone or in combination to offer improved usability and computational efficiency for real time control and monitoring of a semiconductor manufacturing process. More generally, these techniques may be usefully employed in a variety of real time control systems, particularly systems requiring complex scheduling decisions or heterogeneous systems constructed of hardware from numerous independent vendors.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.

Abstract: Mechanisms are provided for controlling a fidelity of a simulation of a computer system. A model of the system is received that has a plurality of components. A representation of the plurality of individual components of the system is generated. A component is assigned to be a fidelity center having a highest possible associated fidelity value. Fidelity values are assigned to each other component in the plurality of individual components based on an affinity of the other component to the fidelity center. The system is simulated based on assigned fidelity values to the components in the plurality of individual components.

Abstract: One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.

Abstract: Methods and systems for modeling a multiprocessor system in a graphical modeling environment are disclosed. The multiprocessor system may include multiple processing units that carry out one or more processes, such as programs and sets of instructions. Each of the processing units may be represented as a node at the top level of the model for the multiprocessor system. The nodes representing the processing units of the multiprocessor system may be interconnected to each other via a communication channel. The nodes may include at least one read element for reading data from the communication channel into the nodes. The node may also include at least one write element for writing data from the nodes into the communication channel. Each of the processing unit can communicate with other processing unit via the communication channel using the read and write elements.

Abstract: A method of improved simulator processing is provided. The method according to the current invention includes grouping frequently accessed data into one set id to improve memory hierarchy performance. The method further includes simulating predication in a non-predicated architecture to improve CPU performance. The simulated predication includes pseudo-predicated implementation of read-operation vector element access pseudo-predicated implementation of write-operation vector element access, and predicated implementation of multi-way branches with assignment statements having a same left-hand-side (lhs). The method further includes determining a selection path in a multi-sensitive “always” block to reduce taken branches. The multi-sensitive “always” block selection path determination includes generating instance-specific code to save port allocation storage, and generating inlined instance-specific code to combine sensitive actions.

Abstract: A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts.

Abstract: System and method for performing a videoconference. One or more computers are utilized to passively monitor a videoconference call between a plurality of participants at respective participant locations, where the videoconference call is performed using a plurality of videoconferencing endpoints at respective ones of the participant locations, and where the monitoring includes monitoring one or more parameters from each of the videoconferencing endpoints. The videoconference call is actively monitored upon detecting values of the one or more parameters from a first videoconferencing endpoint indicating a lack of call quality, thereby generating active monitor data. The active monitor data is automatically analyzed to determine at least one problem causing lack of call quality, and at least one action is automatically determined and performed to address the at least one problem. The active monitoring may also be invoked manually, e.g., in response to user input.

Abstract: The present invention concerns a mainframe data stream proxy (MDSP) (1) for caching communication of at least one emulator (2) directed to at least one mainframe (3), wherein the MDSP (1) comprises: a. a runtime application server (10), adapted for receiving (101, 201) at least one emulator action from the at least one emulator (2) and for sending (105, 209) at least one corresponding mainframe action to the at least one emulator (2); b. wherein the runtime application server (10) is further adapted for retrieving (102, 103) the at least one corresponding mainframe action to be sent to the at least one emulator (2) from a cache (20) of the MDSP (1).

Abstract: A system and method are described for converting a circuit description into transaction-based description at a higher level of abstraction. Thus, a designer can readily view a series of transactions that occurred in the simulation of a circuit. In one aspect, the simulated signals are analyzed and converted into messages of a protocol used by the design. A combination of the messages represents a transaction. Thus, the simulated signals are then converted into a series of protocol transactions. In another aspect, a message recognition module performs the analysis of the simulated signals and converts the simulated signals into messages (e.g., request for bus, bus acknowledge, etc.). A transaction recognition module analyzes the messages and converts the messages into transactions (e.g., Read, Write, etc.). Using both the system and method the circuit description is converted into a higher level of abstraction that allows more comprehensive system-level analysis.

Abstract: Embodiments of the present invention provide a method, system and computer program product for duration estimation of simulating a process model embodied in a directed graph. In an embodiment of the invention, a method for estimating a duration of simulation for a process model embodied in a directed graph can include loading a directed graph for traversal in a simulation engine, identifying nodes in the directed graph, estimating a duration of simulation by the simulation engine for individual ones of the nodes, summing a duration of simulation for the individual ones of the nodes to produce an estimate of a duration of traversal of the directed graph, and presenting the estimate in association with the traversal of the directed graph by the simulation engine.

Abstract: A hybrid simulation system to model cascading events within a black box system may include a tessellated field operable to allow a plurality of black box components to execute on a processor and communicate without needing a direct connection between the black box components. The black box components have transfer functions defined over a common coordinate system and time.

Abstract: A hybrid simulation system to model cascading events within a black box system may include a tessellated field operable to allow a plurality of black box components to execute on a processor and communicate without needing a direct connection between the black box components. The black box components have transfer functions defined over a common coordinate system and time.

Abstract: Emulator computer program machines including an emulator module are disclosed. A machine includes a computer usable medium having computer readable program code for emulating a process of a machine having actuators and mechanical elements. The computer readable program code includes computer readable code instructions configured to display a graphical user interface having input fields corresponding to the actuators and mechanical elements, and to display a graphical representation of output response data of the machine using inputted parameters. Computer readable code instructions for receiving a plurality of parameters inputted into the plurality of input fields, and for emulating a mechanical operation of the machine using the plurality of parameters inputted into the plurality of input fields by simulating the programmable logic controller code are included. Output response data based on an emulation of the mechanical operation of the machine is generated and displayed.

Abstract: A technique for reliably replaying operations in electronic-design-automation (EDA) software is described. In this technique, the EDA software stores operations performed by a user during a design session, as well as any replay look-ahead instructions, in a log file. When repeating the first operation, the replay look-ahead instruction ensures that the same state is obtained in the EDA environment as was previously obtained. For example, if an interrupt occurred when the first operation was previously performed, the replay look-ahead instruction may specify when the interrupt occurred during the performance of the operation so that the effect of the interrupt may be simulated when replaying the first operation.

Abstract: In a method of synthesizing components to design a system meeting an exergy loss target value, one or more candidate sets of components are synthesized and an exergy loss value for each of the one or more candidate sets of components are calculated. A determination as to whether at least one of the candidate set of components meets the exergy loss target value is made and at least one candidate set of components determined to meet the exergy loss target value is identified as the set of components for use in the design of the system.

Abstract: A method and apparatus for modeling radio propagation is provided. In the method, when a wall having a thickness is modeled as a line having no thickness, an error in a shade area is minimized by considering the thickness of a wall while maintaining simplicity in a ray-tracing method.

Abstract: A system, method, and software program for facilitating the assignment of cell specifications to a plurality of cells of a system design. The methods include generating a plurality of candidate cell specifications that meet the specification for the system design. In one embodiment, the method entails using information related to intra-range preference for cell specifications to generate a set of alternative system pareto-optimal solutions which define a boundary of a region of candidate cell specifications. In another embodiment, the method entails generating a substantially uniform set of candidate cell specifications using a prediction-based performance model, such as support vector regression model or cluster-weighted model, an optimizing algorithm such as conjugate-gradient or Markov Chain Monte Carlo Method, and a sample density model.

Abstract: Local clock modeling for a discrete event simulator is described. A local clock generator provides realistic clock characteristics in terms of clock precision and clock drift and clock mapping utilities provide API for other modules and/or protocols in the discrete event simulator to schedule events on local clocks instead of global clock of the simulator.

Abstract: A system and method for generating test vectors includes generating traces of a system model or program stored in memory using a simulation engine. Simulated inputs are globally optimized using a fitness objective computed using a computer processing device. The simulation inputs are adjusted in accordance with feedback from the traces and fitness objective values by computing a distance between the fitness objective value and a reachability objective. Test input vectors are output based upon optimized fitness objective values associated with the simulated inputs to test the system model or program stored in memory.

Abstract: A method for implementing production processes includes a step of programming a state machine for each production process. The programming step includes a definition of a plurality of states and a definition of a plurality of transitions between states, corresponding to possible actions which the corresponding production process may execute. The programming step further includes the steps of detecting whether or not one or more states to be defined for a state machine have already been defined for state machines already programmed for other production processes, and executing the definition of states only for states not detected in the detecting step.

Abstract: The different advantageous embodiments provide a system for network communication testing comprising a communication effects server, a number of radio emulators, a number of radios, and a wireless link simulator. The communication effects computer is configured to provide a number of communication network effects. The number of radio emulators have a number of Ethernet signal-in-space emulators configured to output a number of Ethernet packets to the communication effects server. The number of radios is configured to transmit and receive messages over a radio frequency. The wireless link simulator is configured to provide simulated distance between the number of radios using real-time changes in a simulation running on a number of platforms.

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract: A technique for enhancing the execution efficiency of simulation of a hybrid system. A continuous system simulator receives a request for evaluation of an event generating conditional expression for an event to be processed by a discrete system simulator, from the discrete system simulator. The event generating conditional expression is evaluated by referring to the value of a first variable describing a continuous system. Until evaluation of the event generating conditional expression indicates true, the continuous system simulator repeats simulation of advancing the current time by a step time interval and evaluation of the event generating conditional expression. When evaluation of the event generating conditional expression indicates true, the continuous system simulator sends current time data and the value of a second variable describing the continuous system which is referred to by the discrete simulator, to the discrete simulator.

Abstract: Computer-based simulation of a real time system which includes an application software to be executed on a target hardware platform (hardware and operating system). The application software has tasks of different priority and a set of instructions. An access point is defined for each task at an instruction representing an entry point of a task, a termination point of a task, an access to shared memory, an access to a register of the target hardware platform, and/or a system call or a driver function call, thus dividing the tasks into consecutive instruction blocks. A target execution time is assigned to each instruction block. A discrete event simulation is performed using a queue of events, each associated with a task, an access point of a task, and an event timestamp. During event processing, the instruction block corresponding to the access point associated with the event is executed without interruption.

Abstract: The present invention features a technique comprising the design of a glass antenna having a desired performance regardless of the kind of vehicle and the glass size and the shape of vehicle, by operating an EM (engineering model) simulation tool with an optimization algorithm.

Abstract: Methods, systems, and computer-executable instructions for event synchronized reporting in an process control system are disclosed. Events may be synchronized by a synchronization parameter, whose instances of occurrence may be non-contiguous in time. Examples of synchronization parameters may include a work shift, a work group, an individual's on-duty time, a logged-on period of an individual, the execution times of a process control entity, a batch run type, and a procedure or sub-unit of a batch run. Instances of occurrence of the synchronization parameter may be recorded into a process control event database. Event synchronized reports may contain at least one synchronization value based on both the instances of occurrence of the synchronization parameter as well as historical process control data. Data from various historian databases may be accessed from process control system tools and integrated into a single report.

Abstract: A complex two-dimensional layout of a photomask or other three-dimensional object is systematically decomposed into a finite number of elementary two-dimensional objects with the ability to cause one-dimensional changes in light transmission properties. An algorithmic implementation of this can take the form of creation of a look-up table that stores all the scattering information of all two-dimensional objects needed for the synthesis of the electromagnetic scattered field from the original three-dimensional object. The domain is decomposed into edges, where pre-calculated electromagnetic field from the diffraction of isolated edges is recycled in the synthesis of the near diffracted field from arbitrary two-dimensional diffracting geometries. The invention has particular applicability in die-to-database inspection where an actual image of a mask is compared with a synthesized image that takes imaging artifacts of comers, edges and proximity into account.