Power System Patents (Class 703/18)
  • Publication number: 20080040091
    Abstract: A method of simulating a semiconductor integrated circuit (IC) at gate level includes providing a net list including information about a variable power source and a variable ground source, providing a circuit model including the variable power source and the variable ground source, and simulating the net list by using the circuit model at gate level.
    Type: Application
    Filed: July 11, 2007
    Publication date: February 14, 2008
    Inventors: Tak-Yung Kim, Sun-Yung Jang, Hyoung-Soo Song
  • Publication number: 20080021692
    Abstract: A power estimation system uses a hardware accelerated simulator to advance simulation to a point of interest for power estimation. The hardware accelerated simulator generates a checkpoint file, which is then used by a software simulator to initiate simulation of the processor design model for power estimation. An on-the-fly power estimator provides power calculations in memory. Thus, the power estimation system described herein isolates instruction sequences to determine portions of software code that may consume excess power or generate noise and to provide a more accurate power estimate on the fly.
    Type: Application
    Filed: July 21, 2006
    Publication date: January 24, 2008
    Inventors: Rajat Chaudhry, Sang H. Dhong, Gilles Gervais, Danny J. Klema
  • Patent number: 7319946
    Abstract: New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: January 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Bowen, Alina Deutsch, Gerard V. Kopcsay, Byron L. Krauter, Barry J. Rubin, Howard H. Smith, David J. Widiger
  • Patent number: 7315804
    Abstract: A car engineering assist system and method establish a master data and set a computer-generated virtual car model to represent at least a portion of a product design specification (PDS) of a test car. A real time simulator performs computer simulation of a test module using the car model, which has been set to represent at least the portion of the PDS of the test car, to produce a simulation result. A logic unit performs conformity assessment of the test module based on the simulation result and the master data.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: January 1, 2008
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Osamu Sato, Takeshi Katayama, Hirokazu Matano, Kouji Imai, Haruki Saito
  • Patent number: 7310572
    Abstract: A control method includes modeling a power generation apparatus, monitoring the generation of a total amount power from the power generation apparatus, monitoring internal consumption of power for a power generation apparatus, acquiring a power generation requirement for a first selected time period of a power generation apparatus to meet a power contract, and projecting an amount of total power needed over a diminishing time varying prediction horizon based on the model, the power generation requirement and the internal consumption.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: December 18, 2007
    Assignee: Honeywell International Inc.
    Inventors: Vladimir Havlena, Jiri Findejs
  • Patent number: 7305639
    Abstract: A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: December 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael Stephen Floyd, Joshua David Friedrich, Elspeth Anne Huston, Wolfgang Roesner, Rick John Weiss
  • Patent number: 7305335
    Abstract: Disclosed is a permanent recloser simulator feature for use in a single-pole trip capable recloser control. The permanent recloser simulator feature includes a first logic circuit capable of enabling and disabling operation of the permanent recloser simulator feature in response to receipt of a binary logic signal, and a second logic circuit coupled to the first logic circuit where the second logic circuit is configured to provide an indication of a status of a first pole to a logic engine of the single-pole trip capable recloser control. The permanent recloser simulator feature may further include a third logic circuit associated with a second pole, and a fourth logic circuit associated with a third pole where both are coupled to the first logic circuit. Disabling means of the first logic circuit allow the first, second, third and fourth logic circuit to permanently reside in logic of the recloser control.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: December 4, 2007
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventor: James T. (Ted) Warren
  • Publication number: 20070271081
    Abstract: In general the invention is directed to systems and methods to identify conductors that may be used as part of a power transmission line system. In one embodiment, the invention is directed to a computer-implemented method of evaluating an electric conductor for an overhead power transmission line, comprising: receiving requirements data defining requirements for an overhead power transmission line; receiving conductor data that define at least two conductors to be evaluated; after receiving conductor data for the plurality of conductors to be evaluated, automatically modeling expected operating performance for at least two conductors using conductor assessment software running on a computer, wherein modeling at least comprises, for at least one of the conductors to be evaluated, calculating the conductor's maximum ampacity within the constraints defined by the requirements data; and, based on the modeling, identifying at least one conductor that meets the requirements for the power transmission line.
    Type: Application
    Filed: May 19, 2006
    Publication date: November 22, 2007
    Inventors: Douglas E. Johnson, Elisa J. Collins, Anton F. Jachim
  • Patent number: 7286971
    Abstract: A method for visualizing and efficiently making comparisons of communication system performance utilizing predicted performance, measured performance, or other performance data sets is described. A system permits visualizing the comparisons of system performance data in three-dimensions using fluctuating elevation, shape, and/or color within a three-dimensional computer drawing database consisting of one or more multi-level buildings, terrain, flora, and additional static and dynamic obstacles (e.g., automobiles, people, filing cabinets, etc.). The method enables a design engineer to visually compare the performance of wireless communication systems as a three-dimensional region of fluctuating elevation, color, or other aesthetic characteristics with fully selectable display parameters, overlaid with the three-dimensional site-specific computer model for which the design was carried out.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: October 23, 2007
    Assignee: Wireless Valley Communications, Inc.
    Inventors: Theodore Rappaport, Roger Skidmore, Brian Gold
  • Patent number: 7277841
    Abstract: An adaptive subgridding method for power/ground plane simulations. The method includes superimposing a grid of cells onto a circuit plane. For each cell, the method may determine a fill ratio representing the amount of area in a given cell that overlaps with the circuit plane. For each cell having a fill ratio that is less than a predetermined upper limit or a predetermined lower limit the cell may be divided into a plurality of subcells. The method may then determine the fill ratio for each of the subcells. As with the original cells, each of the subcells having a fill ratio less than the predetermined upper limit and greater than the predetermined lower limit may be further subdivided into additional subcells. The loop may repeat itself until a predetermined integer value is reached, wherein the integer value indicates the number of times a cell may be subdivided.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: October 2, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Istvan Novak, Jason R. Miller, Eric L. Blomberg, Deborah Foltz, Kenneth Laird
  • Patent number: 7249331
    Abstract: A method for estimating power dissipated by processor core processing a workload includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual workload to generate an actual workload characteristic, performing a power analysis for the reference test case to establish a reference power dissipation value and estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: July 24, 2007
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Tejas S. Karkhanis, Srinivasan Ramani, Malcolm Scott Ware, Ken Vu
  • Patent number: 7243006
    Abstract: A control system and method selects a switch configuration for a power circuit having N binary switches, based in part on a finite state machine. The control system includes an embedded simulator, and present and next state contemplators. The various switch states of the power circuit are modeled by the finite state machine such that at any time, the power circuit switches are in a Present State and there are a plurality of Next States which are one or more switch transitions away from the Present State. The embedded simulator estimates the operating conditions of the load based on measured operational characteristics and the Present State. The present state contemplator determines, based on the operating conditions, whether a switch state transition should be contemplated. If so, the next state contemplator determines the optimal next state based on performance criteria and sends a state switch command to the power circuit.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: July 10, 2007
    Assignee: Zetacon Corporation
    Inventor: Michael J. Richards
  • Patent number: 7243054
    Abstract: A network which includes electromagnetic components, such as a wireless communications system, is designed, optimized, modified and/or saved or exported to another applications program using a graphical interface. A display may present a graphical rendering of performance characteristics in a site specific manner showing elements such as walls, doors, windows, furniture, people, foliage, and terrain. The locations where performance characteristic information are presented can be automatically selected and adjusted to present more or less information. The display can be viewed at multiple perspectives, and the viewing angle can be adjusted. In one embodiment, the display can graphically present information related to two different performance characteristics.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: July 10, 2007
    Assignee: Wireless Valley Communications, Inc.
    Inventors: Theodore S. Rappaport, Roger R. Skidmore
  • Patent number: 7236920
    Abstract: A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, David Sager, Vivek Tiwari, Ian Young, David J. Ayers
  • Patent number: 7231281
    Abstract: A dynamic power control system for controlling power utilization on a local level in a power sub-network of a power grid is presented. The power sub-network is configured with switchable power nodes, each having an associated priority level and each having a switch element that operates to switch coupling and uncoupling of first and second subsets of power lines in the sub-network. A sub-network controller monitors utility information that is associated with one of a plurality of system priority levels each of which is associated with one of a plurality of switch state configurations of the respective switch states of the switchable power nodes in the power sub-network, and effects the switch states of the switchable power nodes to comply with the switch state configuration associated with the received utility information.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: June 12, 2007
    Assignee: Costa Enterprises, L.L.C.
    Inventor: Brian Costa
  • Patent number: 7231280
    Abstract: A dynamic power control system for controlling power utilization on a local level in a power sub-network of a power grid is presented. The power sub-network is configured with switchable power nodes, each having a switch element that operates to switch coupling and uncoupling of first and second subsets of power lines in the sub-network. A sub-network controller monitors utility information that is associated with one of a plurality of switch state configurations of the respective switch states of the switchable power nodes in the power sub-network, and effects the switch states of the switchable power nodes to comply with the switch state configuration associated with the received utility information.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: June 12, 2007
    Assignee: Costa Enterprises, L.L.C.
    Inventor: Brian Costa
  • Patent number: 7222061
    Abstract: In the method, a set of limits applicable to a test rod pattern design are defined, and a sequence strategy for positioning one or more subsets of the test rod pattern design is established. Reactor operation on a subset of the test rod pattern design, which may be a subset of fuel bundles in a reactor core for example, is simulated to produce a plurality of simulated results. The simulated results are compared against the limits, and data from the comparison is provided to indicate whether any of the limits were violated by the test rod pattern design during the simulation. A designer or engineer may use the data to determine which operator parameters need to be adjusted (e.g., control blade notch positions for example) in order to create a derivative rod pattern design for simulation, and eventually perfect a rod pattern design for a particular core.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: May 22, 2007
    Assignee: Global Nuclear Fuel - Americas, LLC
    Inventors: William Earl Russell, II, David Joseph Kropaczek, Steven Barry Sutton, Christian Carlos Oyarzun, William Charles Cline, Carey Reid Merritt
  • Patent number: 7191113
    Abstract: A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair within a CMOS circuit. Input and output voltage waveforms provided from results of a timing analysis are used to model the behavior one device of the complementary pair. The device is selected as the limiting device (the device transitioning to an “off state) from the direction of the logic transition being modeled, which is also the device that is not charging or discharging the output load. Therefore, the current through the selected device can be determined from the input and output waveforms and is equal to the short-circuit current prior to the saturation of the selected device.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: March 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Emrah Acar, Ravishankar Arunachalam, Sani Richard Nassif
  • Patent number: 7177783
    Abstract: The invention allows the inclusion of cross-talk coupling and other noise in circuit simulation by considering a resultant glitch in more detail than just its peak value. A set of parameters represents the noise, with an exemplary embodiment using a triangle approximation to a glitch based on a set of three parameters: the peak voltage value, the leading edge slope and the trailing edge slope. These values are then used as the input stimulus to a given cell instance in the network in which the resulting propagated noise values, also in a triangle approximation, are determined by a simulation. The results can be stored as a library so that, given the parameters of the input noise and the particular cell, a simulation can determine the propagated noise through a look-up process. To reduce the space requirements of the library, the dimensionality of the look-up tables can be reduced through the introduction of a set of auxiliary functions to offset error from this reduction.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: February 13, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Lifeng Wu, Jianlin Wei, I-Hsien Chen
  • Patent number: 7158919
    Abstract: A remote monitoring system including a sub-system, local to a nuclear power plant and a remote sub-system at an operations base. Process data is collected manually by a hand-held computer and automatically by instrumentation on the power plant. The data collected is stored on a storage device before being transmitted via a communication link to a remote computer. The remote computer runs data analysis and diagnostic simulations on the process data from the power plant to predict future events.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: January 2, 2007
    Assignee: Rolls-Royce plc
    Inventors: Gary S Wright, John P Shoesmith
  • Patent number: 7152025
    Abstract: A method is provided to automatically identify noise events in a channel of a communication system comprising the steps of: receiving an input signal from the channel; determining the mean energy of the input signal; determining the recent energy of the input signal; identifying a beginning of the noise event when the recent energy is greater than the product of the mean energy and a predefined first threshold; identifying an end of a noise event when the recent energy is less that the product of the mean energy and a predefined second threshold; and providing for output the beginning of the noise event and the end of the noise event. Other systems and methods are disclosed.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: December 19, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Itay Lusky, Daniel Wajcer, Yosef Bendel, Yigal Bitran, Naftali Sommer, Ofir Shalvi, Zvi Reznic, Ariel Yagil, Eli Haim
  • Patent number: 7149637
    Abstract: The detection of electromechanical oscillations in power systems and the estimation of their frequency and damping parameters are based on a linear time-varying model. The parameters of the linear model are on-line adapted by means of Kalman filtering techniques to optimally approximate the measured signal representing the behavior of the power system based on a quadratic criterion. The estimated model parameters are then the basis for the calculation of parameters of the oscillations. Adaptive algorithms are based on a recursive calculation of the estimated parameter vector for each time-step based on the new value of the measured signal and the old values of the estimated parameters.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: December 12, 2006
    Assignee: ABB Research Ltd
    Inventors: Petr Korba, Mats Larsson, Christian Rehtanz
  • Patent number: 7146303
    Abstract: A technique for incorporating power information in a register transfer level design involves defining a module representing an integrated circuit block having its own power grid. The integrated circuit block, when in a power off mode effectuated by a deactivation of a clock signal to the integrated circuit, uses a device dependent on a power grid of an adjoining integrated circuit block to preserve output information from the integrated circuit block to the adjoining integrated circuit block.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: December 5, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Aninda Roy, Vipul Parikh
  • Patent number: 7138878
    Abstract: A semiconductor integrated circuit is provided in which power consumption of each functional block can be determined. The semiconductor integrated circuit comprises: first through third signal processing circuits each operating in synchronization with first through third externally supplied clock signals; first through third counters each counting first through third clock signals; a bus interface circuit outputting a plurality of count values that the first through third counters counted; a clock enable signal generating circuit to generate first through third clock enable signals each controlling the supply of the first through third clock signals to the first through third signal processing circuits; and a counter control circuit supplying a plurality of counter reset signals and a plurality of counter enable signals for resetting and operating the first through third counters, respectively.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: November 21, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Atsushi Obinata
  • Patent number: 7110932
    Abstract: A method and circuit arrangement for determining performance of a digital circuit to a critical degree by the transit time of signals of the longest signal path, also called the critical path. Since the signal transit time is influenced by the operating voltage, by regulating the operating voltage, to compensate for the effects caused by temperature and process fluctuations on the signal transit time in the digital circuit. In particular, the operating voltage can be regulated as a function of the signal transit time in such a way that a required minimum operating frequency can always be achieved. To determine signal transit time, the digital circuit has associated with it a number of replicas of the critical path in the digital circuit upon which the signal transit time is determined. In order to determine the transit time, the signal path replicas are exposed to the same operating conditions as the digital circuit.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: September 19, 2006
    Assignee: Infineon Technologies AG.
    Inventors: Joerg Berthold, Henning Lorch
  • Patent number: 7110930
    Abstract: A method, system and program product for creating a simplified equivalent model for an IC that can be used for detailed analysis. The equivalent model takes into consideration the effects of all the I/O placement regardless of the non-uniformity of I/O placement. The equivalent model is generated, in part, by partitioning the IC into simulation windows and converting I/Os within each simulation window to a current source having the same current change rate, and then running a simulation on this intermediate model. A current change rate observed for a simulation window is then used to convert back to actual I/Os to create the equivalent model. The equivalent model can be simulated using conventional software, e.g., SPICE, for more detailed analysis such as signal integrity, timing of I/Os and noise.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: September 19, 2006
    Assignee: International Business Machines Corporation
    Inventors: Charles S. Chiu, Umberto Garofano, James E. Jasmin
  • Patent number: 7107197
    Abstract: A wiring harness design is analyzed and module data is created automatically and stored for a plurality of harness modules representing wire and component element requirements for those modules, the modules being capable of assembly in selected combinations to create a complete harness.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: September 12, 2006
    Assignee: Mentor Graphics Corporation
    Inventor: Arthur Edward Shropshire
  • Patent number: 7099721
    Abstract: A development tool (2) includes a plurality of measuring tools (71) to (76) and an industrial process simulation device (60). The simulation device (60) simulates a whole industrial scale bioprocess in order to obtain acceptable operating parameters for the industrial scale bioprocess. The measuring tools (71) to (76) enable various significant properties of the biomaterial to be measured and evaluated using only a small test quantity of the biomaterial.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: August 29, 2006
    Assignee: University College London
    Inventors: Peter Dunnill, Mike Hoare, Nigel Titchener-Hooker
  • Patent number: 7096165
    Abstract: A network map is determined, either in the operating direction from the feed circuit to the load in the load circuit, or backward on the basis of the loads in the load circuit to the data for the feed circuit. The feed circuit and the load circuit are coupled to a virtual interface, at which secondary distribution panels can be interconnected. The schematic procedure, in conjunction with appropriate computation rules and visualization in a network map that is obtained, allows the configuration process to be carried out even by those who are unskilled.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: August 22, 2006
    Assignee: Siemens Aktiengesellschaft
    Inventors: Norbert Pantenburg, Thomas-M Stutzer
  • Patent number: 7096175
    Abstract: A method, device and computer program product for the prediction of the stability of an electric power network, where the method is executed after a fault or contingency has occurred, and comprises the steps of (a) during a time interval in which the network is in a transient condition, determining for at least one load connected to the electric power network, at least one parameter describing an estimated steady state behavior of the load, (b) executing a load flow calculation for the electric power network using the least one parameter describing the estimated steady state behavior the at least one load, (c) determining, if the load flow calculation indicates stability has a solution, that a future stability of the electrical power network exists, or, if the load flow calculation indicates instability does not have a solution, that a future stability of the electrical power network does not exist.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: August 22, 2006
    Assignee: ABB Research LTD
    Inventors: Christian Rehtanz, Valentin Bürgler, Joachim Bertsch
  • Patent number: 7085700
    Abstract: An improved method for debugging of analog and mixed signal behavioral models during simulation using Newton-Raphson iteration replay. The method according to the invention has substantially modified the prior art solution by limiting the interactive debugging steps in a replay of the last iteration of the accepted timepoints. Using this method, the user only interacts with the simulation during the iteration replay, and only for the accepted solution points. If the user is single stepping through this simulation, the simulator enters interactive mode at each statement during the replay. Similarly, if not single stepping, but a breakpoint has been triggered, the simulator enters the interactive mode at the appropriate statement to honor the breakpoint. While the iteration replay is performed, the system of equations does not need to be solved again. Instead, the solution vector is reinstated from the known solution of the last iteration.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: August 1, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Richard Trihy
  • Patent number: 7085702
    Abstract: Method and system for modeling and automatically generating an embedded system from a system-level environment. A plurality of user-selectable system-level design objects are provided in the system-level environment. Each system-level design object is defined by a system-level function and is selectable by a system-level designer. A plurality of hardware-level design objects are also provided. Each hardware-level design object is configured to generate a hardware definition of a hardware-level function. Each system-level design object maps to one or more hardware-level design objects. A processor design object is provided which defines a processor. In response to selections made by the designer, a system-level design is instantiated in a system-level design file. The system-level design includes user-selected ones of the system-level and processor design objects.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: August 1, 2006
    Assignee: Xilinx, Inc.
    Inventors: L. James Hwang, Jeffrey D. Stroomer
  • Patent number: 7079998
    Abstract: A method for analyzing power noise and method for reducing the same are disclosed, wherein the present invention is utilized in an IC design process. First, a DC analysis is performed with a related IC design by utilizing computer aided design (CAD) software and circuit simulation software for obtaining a power network model of the IC design. Then, the power network model is defined as being composed of a plurality of unit blocks. After analysis, the quantity and type, etc., of components connected electrically to each of the unit blocks are recognized and are regarded as component reference data of each of the unit blocks. Afterwards, according to the component reference data of each of the unit blocks, the voltage drop (IR drop) occurring in operation for each of the unit blocks is evaluated and obtained by utilizing an equivalent circuit constructed by components that are connected electrically to each of the unit blocks.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: July 18, 2006
    Assignee: Silicon Integrated Systems Corporation
    Inventors: Hao-Luen Tien, Shang-Yi Chen, Ming-Huan Lu, Chun-An Tu
  • Patent number: 7069162
    Abstract: Constant components and rotation fundamental mode components on the slide plane between a rotor and a stator are derived from a magnetic field distribution at a predetermined time. The analysis space is divided into a rotor space and a stator space. A fundamental mode on the slide plane is rotated by a rotation angle of a rotation magnetic field corresponding to a time-step width. A solution obtained in this state is added to the constant components. By using the addition result as the boundary conditions on the slide plane, non-linear magnetic field analysis is performed by taking into consideration the magnetic saturation in the stator space. The rotation fundamental mode on the slide mode is rotated by an angle obtained by subtracting the rotation angle of the rotor from the rotation angle of the rotation magnetic field corresponding to the time-step width.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: June 27, 2006
    Assignee: Hitachi, Ltd.
    Inventor: Kenji Miyata
  • Patent number: 7069195
    Abstract: A method of designing a small-sized, self-shielding magnetic field gradient coil assembly that is for use in an NMR spectrometer, provides high approximation accuracy, is simple in structure, and has a large inside diameter. The gradient coil assembly consists of tightly wound inner and outer coils. The designing process starts with setting or resetting the number of the inner coils and the number of turns of each inner coil. Their positions are optimized such that the magnetic field gradient strength falls within a tolerable range under shielded condition. Then, the number of the outer coils and the number of turns of each outer coil are set. The Fourier components of a current distribution necessary for the outer coils are calculated.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: June 27, 2006
    Assignee: JEOL Ltd.
    Inventor: Kenichi Hasegawa
  • Patent number: 7054795
    Abstract: A method for optimizing the segment lengths of a segmented transmission line, comprising the steps of modeling the electrical performance of the segmented transmission line, and evaluating the model for incremental changes in electrical performance, selecting a set of segment lengths which meets a set of predefined optimization criteria. The predefined optimization criteria is, for example, minimum peak VSWR.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: May 30, 2006
    Assignee: MYAT Inc.
    Inventor: Donald Aves
  • Patent number: 7050866
    Abstract: A method for providing independent static and dynamic models in a prediction, control and optimization environment utilizes an independent static model (20) and an independent dynamic model (22). The static model (20) is a rigorous predictive model that is trained over a wide range of data, whereas the dynamic model (22) is trained over a narrow range of data. The gain K of the static model (20) is utilized to scale the gain k of the dynamic model (22). The forced dynamic portion of the model (22) referred to as the bi variables are scaled by the ratio of the gains K and k. The bi have a direct effect on the gain of a dynamic model (22). This is facilitated by a coefficient modification block (40). Thereafter, the difference between the new value input to the static model (20) and the prior steady-state value is utilized as an input to the dynamic model (22). The predicted dynamic output is then summed with the previous steady-state value to provide a predicted value Y.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: May 23, 2006
    Assignee: Pavilion Technologies, Inc.
    Inventors: Gregory D. Martin, Eugene Boe, Stephen Piche, James David Keeler, Douglas Timmer, Mark Gerules, John P. Havener
  • Patent number: 7039575
    Abstract: A network-based method for facilitating a selection of at least one power generating facility, using a network-based system including a server and at least one device connected to the server via a network is disclosed. The method includes identifying assumptions to evaluate a power generating facility, receiving power plant facility information, and computing performance metrics of the facility based on received information and the identified assumptions. Other embodiments of the invention utilize a System, a Computer Program, an Apparatus, or a Computer for determining a value for one or more power generating facilities based on pre-determined assumptions that are developed from historical experience.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: May 2, 2006
    Assignee: GE Capital Services Structured Finance Group, Inc.
    Inventor: Mark Anthony Juneau
  • Patent number: 7035785
    Abstract: A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, David Sager, Vivek Tiwari, Ian Young, David J. Ayers
  • Patent number: 7013254
    Abstract: A low-complexity, high accuracy model of a CPU power distribution system has been developed. The model includes models of multiple power converters that input to a board model. The board model then inputs to a package model. Finally, the package model inputs to a chip model. The model provides a high degree of accuracy with an acceptable simulation time.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: March 14, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude R. Gauthier, Brian W. Amick
  • Patent number: 7006962
    Abstract: A method and system for predicting delay of a multi-million gate sub-micron ASIC design is disclosed. The method and system include automatically partitioning a netlist into at least two logic cones, and running respective instances of a delay prediction application on the logic cones on at least two computers in parallel.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: February 28, 2006
    Assignee: LSI Logic Corporation
    Inventors: Saket Goyal, Santhanakrishnan Raman, Prabhakaran Krishnamurthy, Prasad Subbarao, Manjunatha Gowda
  • Patent number: 7000214
    Abstract: A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Joseph A. Iadanza, Raminderpal Singh, Sebastian T. Ventrone, Ivan L. Wemple
  • Patent number: 6996511
    Abstract: A two-dimensional mesh is generated on a plane perpendicular to the rotation axis. At this time, a ring-shaped gap is provided between the rotor and the stator, and portions facing the ring-shaped gap are equally divided into the same number of parts. An initial three-dimensional mesh is generated by joining together a plurality of two-dimensional meshes in the direction of the rotation axis while rotating the two-dimensional meshes. A boundary surface is formed in a cylindrical gap composed of a stack of the ring-shaped gaps, and a three-dimensional mesh is generated by filling the cylindrical gap with a plurality of polyhedrons, including polyhedrons comprising each of surface elements constituting the stator-side mesh surface, rotor-side mesh surface and boundary surface as one face.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: February 7, 2006
    Assignee: The Japan Research Institute, Limited
    Inventors: Koji Tani, Tetsuo Ogawa
  • Patent number: 6961690
    Abstract: The present invention provides a method and mechanism for simulating complex digital circuits using hybrid control and data flow representations. Specifically, the invention provides a method of controlling the simulation of a digital circuit in such a way that desired functions are annotated for subsequent analysis. A hardware design code describing the digital circuit is converted to an assignment decision diagram (ADD) representation that is then annotated with one or more control nodes that are used for maintaining control flow through a simulator. In this way, one or more break points are created that allow the simulator to stop at associated points in the simulation.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: November 1, 2005
    Assignee: Altera Corporation
    Inventors: David Karchmer, Daniel S. Stellenberg
  • Patent number: 6952648
    Abstract: Systems and methods for determining a power disruption index indicative that provides subscribers with a forecast of weather conditions that are likely to cause interruptions to power distributions systems within their specific areas of service. The Power Disruption Index (PDI), is a calculation of a number of forecast weather parameters including severe thunderstorm probabilities and intensities, wind speeds, wind gusts, and snowfall and ice accretion. The index combines each of these input parameters with a specific weighting based on the forecast intensity of each of the parameters, along with alert threshold criteria provided by each client utility. The output PDI is a forecast of local weather conditions for a specific local service area or power distribution network.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: October 4, 2005
    Assignee: WSI Corporation
    Inventors: James Lee Menard, Stephen Anthony Massa, John Gerard Bosse, Paul Douglas Drewniak
  • Patent number: 6937971
    Abstract: A system and method for determining the desired decoupling components for a power distribution system having a voltage regulator module. The system may employ a mathematical model of a voltage regulator circuit, such as a switching voltage regulator. The mathematical model may be a SPICE model, or a circuit model in another format. The method may include simulating the operation of the power distribution system to obtain a estimate of the bulk capacitance required for effective decoupling. For digital systems, the method may include a cycle-by-cycle simulation of the power distribution system, wherein the simulation occurs over a number of clock cycles. The performance of the power distribution system may then be analyzed for each simulated clock cycle. The simulation may also include analyzing the transient responses and loop stability of the power distribution.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: August 30, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Larry D. Smith, Raymond E. Anderson, Tanmoy Roy
  • Patent number: 6931369
    Abstract: A method and apparatus for thermally simulating a circuit over a network is provided. Techniques are provided for designing a circuit that satisfies user-specified functional requirements received over a network. Based on the specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. One or more web pages that identify the components are then delivered to the browser over the network. The component and topology information may be used to generate a schematic diagram that is delivered in a web page to the user over the network. The user may thermally simulate the designed circuit. Many characteristics of the board may be adjusted to provide an accurate thermal simulation.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: August 16, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey Robert Perry, Martin Garrison, Rex L. Allison, III, Richard Levin, Phil Gibson, Vandana A. Sojrani, Khang Nguyen, Wanda Carol Garrett, John D. Perzow
  • Patent number: 6925429
    Abstract: An electric wiring simulation device 1 of the present invention includes an input device 2; a display 5; a characteristics information data base 4 storing parts information on parts and wirings, discharge characteristics of a power supply, current-prearcing time characteristics of protecting parts and current-smoke time characteristics of the wirings; an assigned path searching unit 11 searching an assigned path between a short-circuit point and the power supply on a test object circuit; a current value calculating unit 12 calculating a resistance value on the assigned path based on the parts information, and calculating a short-circuit value based on the resistance value and the discharge characteristics of the power supply; and a judging unit 13 judging whether or nor each protecting part is fused or etch wiring smokes based on the current-smoke time characteristics and the current-prearcing time characteristics, at unit time intervals.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: August 2, 2005
    Assignee: Yazaki Corporation
    Inventor: Yasuo Iimori
  • Patent number: 6922661
    Abstract: The process is intended to optimize the operation of a digital protection system for protecting sets of busbars in the power station and uses a basic schematic of the electrical configuration of the power station obtained from information on the type of components used in the power station, and on the possible connections and accesses to said components. The information is assigned to management units of the digital protection system, said management units comprising peripheral measurement units and at least one centralization unit. A topological compilation process is implemented to provide a compiled schematic topology, and to provide a compiled assignment topology of the components in the power station and of their connections to the management units. A partial graph, whose structure depends on the type of information searched for and the status of each component of the power station, is obtained for each peripheral unit.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: July 26, 2005
    Assignee: Alstom
    Inventor: Jean-Jacques Carrillo
  • Patent number: 6901565
    Abstract: A system for analyzing the power consumption of a behavior description of an electrical design includes a structural element library including a set of technology-independent structural macro elements, a macro power model module providing macro power models for one or more of the structural macro elements in the structural element library, and a power estimation module providing a power consumption value of the electrical design using a netlist of interconnected components representative of the electrical design, and the macro power models. The macro power models are associated with corresponding power models in a user-specified gate-level power model library. The power analysis system enables behavior level or RTL power analysis using a user-specified gate-level cell power model library containing arc-based or pin-based power model descriptions or both.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: May 31, 2005
    Assignee: Sequence Design, Inc.
    Inventor: Serguei A. Sokolov