Abstract: A current control device and a power conversion system employing the current control device are provided. The current control device controls N power conversion unit(s), where N is a positive integer. The N power conversion units are connected in parallel when N is greater than 1. Each power conversion unit includes a signal input terminal and a current-controlled output terminal electrically connected to an external circuit. The current control device includes a first current sensor and an error compensator. The first current sensor samples a current flowing through the external circuit and acquires a sampling value. The error compensator receives the sampling value and a reference value and generates a compensation value accordingly, and outputs N current command(s) to the N power conversion unit(s) respectively according to the reference value and the compensation value.

Abstract: The disclosure describes various techniques to control of small angle Mølmer-Sørensen (MS) gates and to handle asymmetric errors. A technique is described for handling asymmetric errors in quantum information processing (QIP) systems. An exemplary method includes implementing a quantum circuit in the QIP system that has first and second qubit lines, with a first qubit state having a greater measurement error than a second qubit state; swapping the roles of the first and second qubit states at a quantum circuit level in response to at least one of the first qubit line and the second qubit line being expected to be at the first qubit state at a measurement; and enabling a quantum simulation using the quantum circuit with the first and second qubit states reassigned in at least one of the first qubit line and the second qubit line after the swapping of the respective roles.

Abstract: The disclosure describes various techniques to control of small angle Mølmer-Sørensen (MS) gates and to handle asymmetric errors. A technique is described that implements a two-qubit calibration circuit with two MS gates, where a parameter ? represents an amount of entanglement of the MS gate. The calibration circuit is run for several values of ? to measure observed parity signals that are direct measurements of the values of ?. Calibration information is generated that describes the relationship between ? and the parity signals, and such calibration information is then provided to arbitrarily calibrate one or more MS gates in a quantum simulation. Another technique is described for using the calibration information in quantum simulations, including for quantum chemistry simulations.

Abstract: A computer that receives a set of names of coverage events. The computer creates, by a machine learning-based technique, groups from the set of received names of the coverage events based on the set of names of the coverage events. The computer generates a cross product coverage model from the created groups and identifies subgroups of uncovered events for each of the created groups.

Abstract: A system is provided for mobile log heatmap-based auto test case generation. In particular, the system may continuously track and log user actions and data flows for applications within the production environment. Based on the logs, the system may generate a navigation network graph through which the system may identify all possible navigation paths that may be taken by the user to access certain functions or screens of the application. Once the paths have been identified, the system may collect and sanitize testing data based on user session and system interaction data in the production environment. The testing data may then be used to drive the development of the next release or version of the application.

Abstract: Systems and methods are provided for using an integrated circuit design tool to analyze timing requirements of a circuit design for an integrated circuit. A slack is calculated for a timing path in the circuit design that fails to satisfy a timing constraint. The slack is decomposed into multiple categories of delays in the timing path. The categories of delays for the slack may include intrinsic margin, clock skew, logic delay, and fabric interconnect delay. The logic delay may include local interconnect delay and logic circuit delay. The fabric interconnect delay may include delays in interconnect elements that are used to make connections between larger blocks of the logic circuits. Different optimization strategies are provided to solve the timing constraint failure for each of the different categories of slack breakdown. Slack profiles of the entire design in each of the four categories of slack are also provided.

Abstract: A graphical user interface (GUI) is configured for displaying surfaces of simulated objects within a scene. The GUI comprises a selector to choose between displaying the scene as: a plurality of particles, wherein each particle comprises a plurality of attributes; a plurality of ellipsoids formed from the plurality of particles, wherein dimensions and orientation of each ellipsoid depend on the number and direction of neighboring ellipsoids within a search radius of the ellipsoid; or one or more splatted or rasterized surfaces formed from the plurality of ellipsoids. The GUI further includes a display window within which the GUI displays the scene.

Abstract: A method of provisioning mesh communication networks is disclosed. The method involves simulating the performance of a proposed network design to ensure the proposed network design meets service level criteria before provisioning a network in accordance with the proposed network design. Such simulations are required to be comprehensive because highly improbable events can be sufficient to result in a mesh network not meeting the stringent performance criteria which such networks are required to meet. Known methods of provisioning rely on exhaustively listing the mesh network states which would adversely impact the service offered by a proposed network design as part of simulating the performance of the proposed network design—this is an error prone exercise since relevant network states can be missed. A simulation technique is proposed in which the network state after each event is represented by a weighted graph indicating a measure of path cost for each of the links in the mesh network.

Abstract: Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

Abstract: Disclosed is cell-aware defect characterization by considering inter-cell timing. Also disclosed is a method and apparatus that determines whether a defect can be detected in a standard library cell used to design an integrated circuit. A defect detection table is generated that indicates whether particular defects can be detected with particular combinations of input logic states and under varying load conditions. Results are merged to provide a single metric for each combination of input and output logic states that indicates one of three possible results for each defect: (1) whether the defect can be detected under all load conditions, (2) whether the defect can be detected only under some load conditions; or (3) whether the defect cannot be detected for the particular combination of input logic states regardless of the load conditions.

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

Abstract: Example systems and methods are disclosed for performing a timing analysis on a circuit design. A plurality of switching scenarios are identified for the circuit design. One or more predictive models are applied to predict a subset of the plurality of switching scenarios that are likely to cause timing paths with critical timing problems. A dynamic voltage analysis is performed on timing paths based on the subset of switching scenarios. The one or more predictive models are applied to predict a set of critical timing paths based on the subset of switching scenarios that are likely to cause critical timing problems, the one or more predictive models taking into account the dynamic voltage analysis. A timing analysis is the performed on the set of critical timing paths.

Abstract: An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.

Abstract: A method and system for automated design of a physical system are provided. During operation, the system obtains a component library comprising a plurality of physical components, receives design requirements of the physical system, and constructs an initial system model based on physical components in the component library and the design requirements. The system topology associated with the initial system model can include a large number of links that are sufficiently coupled to one another, and a respective link comprises one or more physical components. The system further performs an optimization operation comprising a plurality of iterations, with the system topology being updated at each iteration. Updating the system topology includes removing links and components from the system topology. The system then generates a final system model based on an outcome of the optimization operation and outputs a design solution of the physical system according to the final system model.

Abstract: A timing fixing logic section may select a timing path from among a plurality of timing paths. For the selected timing path, multiple nets along the path may be traversed. For a particular net, multiple metal layers may be traversed. For a particular metal layer, multiple shapes that are associated with the particular net may be traversed. A timing fixing logic section may examine space that is nearby each of the shapes, and identify unused space. The timing fixing logic section may add an extension metal section to the shape. In addition, the timing fixing logic section may identify an existing via of a first type, and select an alternate via of a second type having a resistance that is higher or lower than the existing via. The existing via may be replaced with the alternate via. Accordingly, hold and setup timing of a circuit may be improved.

Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.

Abstract: Systems and methods according to present principles provide a test architecture which is designed to support software and hardware testing in an automated environment. Systems and methods are described which include a functional definition and architecture of the test system including the host environment, host-user interface, test scripts, host-to-target communications, target test module, target test shell, target commands and other supporting aspects.

Abstract: A method is for verifying a logic operation of a target circuit including a circuit module configured to dynamically switch between synchronous transfer and asynchronous transfer. The method includes setting a time window for detecting an erroneous change of a logical value of a data signal. The time window ranges a first time period forward and a second time period backward from an edge of a clock signal and excludes a certain sub range. The method includes, during a simulation, determining whether or not the erroneous change of the logical value of the data signal is detected during the set time window. The method includes, upon detection of the erroneous change, inserting an erroneous sample into a test vector for the simulation, and upon non detection of the erroneous change, continuing the simulation without inserting the erroneous sample.

Abstract: An aspect of the present disclosure aids investigation of performance bottlenecks occurring during execution of software applications. In an embodiment, a set of long sub-sequences of invocations of modules occurring frequently during execution of a software application are identified. Such identified sub-sequences are notified to a user (e.g., administrator) for examination of any performance bottlenecks during execution of the software application. According to another aspect, a log is formed containing super-sequences of invocation of modules formed during execution of the software application. The log is examined to identify a respective frequency of occurrence of multiple sub-sequences of invocations, wherein the set of long sub-sequences are identified based on the identified frequencies and respective length (i.e., number of modules in the sequence) of each of the plurality of sub-sequences of invocations.

Abstract: Techniques for performing root cause analysis in dynamic software testing via probabilistic modeling are provided. In one example, a computer-implemented method comprises initializing, by a system operatively coupled to a processor, a threshold value, a defined probability value, and a counter value. The computer-implemented method also includes, in response to determining, by the system, that a probability value assigned to a candidate payload of one or more candidate payloads exceeds the defined probability value, and in response to determining, by the system, that the counter value exceeds the threshold value: determining, by the system, that a match exists between the candidate payload and an input point based on an application of the candidate payload to the input point resulting in a defined condition, wherein the one or more candidate payloads are represented by population data accessed by the system.

Abstract: According to some possible implementations, a method may include determining one or more inputs to a model of a system and one or more outputs from the model. The method may include identifying a continuous portion of the model to be discretized. The method may include discretizing the continuous portion of the model, using at least one of a continuous linear representation for the model or a frequency response associated with the continuous linear representation, to generate a discrete linear representation for the continuous portion of the model. The method may include outputting information associated with the discrete linear representation to permit the continuous portion of the model to be implemented on one or more processors.

Abstract: Systems and methods are provided for compensating for parasitics in current measurements utilizing series current sense resistors. In one or more embodiments, the techniques include connecting a probe to a terminal of a circuit and a waveform measuring device. A waveform measuring device then acquires, through the probe, a voltage waveform. A virtual probe netlist is generated, where the netlist is descriptive of a series resistance and associated parasitics. A virtual probe processor converts, based on the virtual probe netlist, the voltage waveform to a current waveform representative of a current in the circuit.

Abstract: A static timing analysis controller includes a feedback loop identification module that identifies invariable flip flop feedback loops of an integrated circuit design, and adds the identified feedback loops to false path lists. The static timing analysis controller then performs timing update operations and identifies hold violations based on the invariable flip flop feedback loops included in the false path list. In turn, the static timing analysis controller identifies reduced or less pessimistic numbers of hold violations, resulting in fewer buffers added to the integrated circuit design.

Abstract: Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal.

Abstract: Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.

Abstract: Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system. In one exemplary embodiment disclosed herein, for example, a real-time clock signal is generated and tasks defined by an embedded software application are triggered with the real-time clock signal. In this embodiment, the embedded software application is executed by an embedded processor with a real-time operating system (“RTOS”), and the real-time clock signal is controllable independent of a processor clock signal driving the embedded processor in a manner that allows the real-time clock to have a different time base than the processor clock.

Abstract: A computer-implemented method of extracting parasitics associated with a circuit design layout generated by modifying a previous iteration of the layout, includes, in part, identifying a first multitude of nets that have been changed in the circuit design layout relative to the previous iteration of the circuit design layout. The method further includes, in part, calculating a first multitude of parasitic capacitance values between each of the first multitude of first nets and each of a second multitude of nets disposed in proximity of the first multitude of nets. The method further includes, in part, identifying each net in the second multitude of nets as an aggressor net if a number defined by the net's associated parasitic capacitance value is higher than a threshold value. The method further includes excluding nets in the second multitude of second nets that are not identified as aggressor nets from the parasitic extraction.

Abstract: Examples disclosed herein relate to application testing. The examples may enable identifying a set of tests for testing an application and identifying a set of attributes associated with a particular test of the set of tests. The set of attributes may comprise an average execution duration of the particular test, a last execution time of the particular test, and a last execution status of the particular test. The examples may further enable determining attribute scores associated with individual attributes of the set of attributes and obtaining user-defined weights associated with the individual attributes. The examples may further enable determining a test score associated with the particular test based on the attribute scores and the user-defined weights associated with the individual attributes. The set of tests may be sorted based on the test score associated with the particular test. The sorted set of tests may be executed.

Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives user defined parameters for modifying a power grid layout and identifies a region of the power grid layout for strap insertion based on the user defined parameters. The apparatus may include a track identifier module that identifies track locations in the region of the power grid layout for strap insertion. The apparatus may include a strap placement module that inserts at least one strap in the region of the power grid layout based on pre-determined rules for strap insertion.

Abstract: A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.

Abstract: A circuit description, such as a hierarchical netlist, is obtained for an integrated circuit. Based on the circuit description, a treemap representation is rendered using blocks, nodes, and/or devices from the hierarchical netlist as objects, or leaves, in the treemap representation. Using a virtual layout, the leaves are positioned in the treemap representation independent of their physical layout. Circuit properties for the electronic design are also obtained using various methods such as a circuit simulator. The circuit properties are displayed to a user on the treemap representation.

Abstract: Various techniques implement an electronic design with electrical analyzes with compensation circuit components. A power pin of a power net may be identified in an electronic design. The electronic design may be reduced into a reduced electronic design at least by applying one or more circuit reduction techniques to at least a portion of the electronic design. At least one load device of a plurality of load devices in the reduced electronic design may be transformed into a transformed load device. One or more design closure tasks may be performed on the electronic design using at least the reduced electronic design and the transformed load device.

Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.

Abstract: The present document relates to a method for allocating resources for multi-user or multi-station (STA) data transmission in a wireless LAN system, and an apparatus therefor. To this end, an AP generates a frame including a signaling field and a data field, wherein the signaling field includes a first signaling field (SIG A field) comprising common control information for a plurality of STAs and a second signaling field (SIG B field) comprising user specific control information for each of the plurality of STAs, the second signaling field also comprising data transmission resource allocation information for each of the plurality of STAs. The AP transmits the thus generated frame to the plurality of STAs.

Abstract: The present disclosure relates to a method for waveform based debugging in a formal verification of an integrated circuit. The method may include receiving, using at least one processor, an electronic circuit design and partitioning a cone of influence for a cover property of the electronic circuit design into design logic and property logic. The method may further include applying an X-value to all inputs associated with the cone of influence and performing an X-simulation until a fixed point is reached. The method may also include identifying a non-X node and providing a path of X-diffusion at a property output.

Abstract: A design verification problem includes a design description and a property to be verified. Feature data is identified from the design verification problem and a result is predicted for the design verification problem based on the feature data. A plurality of verification engines is then orchestrated based on the prediction. Supervised machine learning may be used for the result prediction. Feature data and verification results from a plurality of training test cases are used to train a classifier to create a prediction model. The prediction model uses the feature data of the design verification problem to make a result prediction for the design verification model.

Abstract: This application discloses a computing system to identify multiple views of cells in a circuit design for selective utilization during analog fault simulation of the circuit design. The views of the cells can include two or more of macromodel design views, schematic design views, or extracted design views that includes parasitic elements extracted from a physical layout of the circuit design. The computing system can prompt generation of multiple netlists, each netlist generated based on a different combination of the identified views of the cells in the circuit design, or a list of macromodels with pin accurate subcircuit wrappers, parse and organize the cells in each netlist or the list of macromodels, identify one of the cells to inject with a defect, and selectively simulate portions from a plurality of the netlists based, at least in part, on the identified one of the cells to inject with the defect.

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.

Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

Abstract: Systems and techniques for clock tree optimization are described. An electronic design automation (EDA) tool can receive a graph that represents a circuit design, wherein a set of trees in the graph can correspond to a set of clock trees in the circuit design. For each tree in the set of trees, a set of leaf node pairs can be determined. Next, for each leaf node pair, a flow can be created in the graph between the two leaf nodes in the leaf node pair. Aggregate flows can be determined for edges in the graph based on the flows. A set of edges based on the aggregate flows can be identified, and then circuitry corresponding to the set of edges can be identified. Next, the identified circuitry in the circuit design can be optimized.

Abstract: A hybrid timing analysis method includes: receiving a pre-layout netlist, a post-layout netlist and a configuration file associated with an integrated circuit design; generating a first measurement script and an input stimulus waveform file according to the configuration file; performing a first dynamic timing analysis upon the pre-layout netlist by using the first measurement script and the input stimulus waveform file to generate a pre-layout simulation result; identifying at least one data path and at least one clock path according to the pre-layout simulation result; generating a second measurement script according to the at least on data path and at least one clock path; and performing a second dynamic timing analysis upon the post-layout netlist by using the second measurement script and the input stimulus waveform file to generate a first post-layout simulation result. Associated system and non-transitory computer readable medium are also provided.

Abstract: Disclosed herein are embodiments of systems, methods, and products using a center access direction for pin figures during an abutment of instances in an integrated circuit (IC) design. Using a center access direction allows an electronic design automation (EDA) tool to overlap the centers of the pin figures to be merged. Once the centers of the pin figures are overlapped, the EDA tool runs one or more merging and optimization algorithms to abut the circuit devices containing the pin figures. The EDA tool therefore is computationally efficient and yet provides more functionality: unlike the conventional system, the EDA tool does not have to align the pin figures and calculate an offset to overlap the pin figures post alignment. Furthermore, the EDA tool can overlap the pin figures from any angle and is not confined to rectilinear access direction of the conventional systems.

Abstract: Electronic design automation tools may perform static timing analysis on an integrated circuit design. An integrated circuit design may have multiple nodes that can be traversed using a breadth-first search. To reduce the run-time of static timing analysis tools, tags recording arrival times associated with non-critical paths may have their consolidated in order to include only the critical timing information in the tag, thereby reducing the amount of data that is carried through to the analysis of the entire design. In a critical slack based merging method, a maximal arrival time associated with a circuit node may be compared to the remaining arrival times associated with the circuit node. Arrival times less than the maximal arrival time by an amount greater than a threshold amount may be deemed non-critical arrival times and may be removed from the tag for the circuit node.

Abstract: A computing device may be used to create a model that includes a block. The block may represent a function corresponding to a simulation and capable of operating in a fault operational mode. The computing device may also, or alternatively, associate a fault scenario, corresponding to the model, with the fault operational mode of the block. Additionally, or alternatively, the computing device may simulate the fault scenario based on the block diagram model.

Abstract: A method of enabling a simulation of a circuit design is described. The method comprises generating, using a computer, an initial representation of the circuit design; simulating the circuit design using the initial representation by driving input signals to the circuit design based upon a simulation event listing; capturing event data associated with a plurality of timestamps in a first file while simulating the circuit design; identifying a plurality of events associated with a timestamp of a plurality of timestamps; reordering events of the plurality of associated with the timestamp; and generating a replay module used to drives input signals to the circuit design. A system for enabling a simulation of a circuit design is also described.

Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.

Abstract: Methods and/or systems are provided that may be utilized to read from or write to a resource, such as a shared memory, for example.

Abstract: A method includes determining a set of shared memory access instructions and execution frequencies and selecting one or more groups of instructions that access a same memory location. The method also includes finding pairs of instructions from each group, for which another access to the same memory location may occur between execution of the instructions in the pair, and estimating a probability that a data race may occur using a time gap between the instructions and the execution frequencies, and generating a list of instruction tuples that include the pair of instructions. The method includes calculating a score for each instruction in the tuples, the score representing a likelihood of triggering a data race by injecting a delay before an instruction. The method includes selecting instructions having a score indicating a lower than a threshold probability that the instruction will comprise a last access of a data race.

Abstract: Disclosed aspects relate to verifying an integrated circuit design. A set of design constraints may be received with respect to a verification process for the integrated circuit design. Based on the set of design constraints, a constraint model may be constructed. A new global constraint may be determined using the constraint model. The new global constraint may be used to process the verification process for the integrated circuit design.

Abstract: Embodiments include methods, and processing system, and computer program products providing portion isolation design to a chip design to facilitate partial-good portion isolation test of the chip. Aspects include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test.